TDM Pulse Amplitude

Modulation/Demodulation
Trainer ST2102

Operating Manual
Ver 1.0

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ST 2102

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TDM Pulse Amplitude Modulation/Demodulation Trainer

ST2102
TABLE OF CONTENTS

1. Features 4
2. Technical Specifications 4
3. Introduction to Pulse Amplitude Modulation 5
4. Multiplexing 6
a. Experiment 1 11
b. Experiment 2 11
5. Synchronization 13
c. Experiment 3 15
d. Experiment 4 16
6. Complete PAM. Receiver 18
7. Phase Locked Loop 20
8. TDM Synchronization 22
e. Experiment 5 24
f. Experiment 6 25
g. Experiment 7 26
9. Warranty 31
10. List of Service Centers 32
11. List of Accessories 33

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FEATURES

• Crystal controlled clock.

• On-board sine wave generator (synchronized)
• On-board pulse generator.
• 4 Analog input channels sampled and time division multiplexed.
• Pulse duty cycle selectable.
• Internal/External sampling selectable.
• 4 Channel De-multiplexer.
• Generation of clock at receiver by PLL System.
• 4th Order Butterworth L.P. filter.

TECHNICAL SPECIFICATIONS

Crystal Frequency : 6.4 MHz

Analog Input Channels : 4
Multiplexing : Time Division Multiplexing
Modulation : Pulse Amplitude Modulation
On Board Analog Signal : 250Hz, 500Hz, 1 KHz, 2 KHz
(Sine wave synchronized to sampling pulse)
Adjustable amplitude and separate variable DC
level).
Sampling Rate : 16 KHz / Channel
Sampling Pulse : With duty cycle variable from 0-90% in decade
steps.
Clock Regeneration at : Using PLL
Receiver
Low Pass Filter Cut-Off : 3.4 KHz
Frequency
Test points : 52
Interconnections : 4 mm Sockets
Power : 220 V ± 10 % 50 Hz, 4VA
Dimensions (mm) : W420 x H 100 x D255
Weight : 2.4 Kg. (approx)

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INTRODUCTION TO PULSE AMPLITUDE MODULATION

Most digital modulation systems are based on pulse modulation. It involves variation
of a pulse parameter in accordance with the instantaneous value of the information
signal. This parameter can be amplitude, width, repetitive frequency etc.
Depending upon the nature of parameter varied, various modulation systems are used.
Pulse amplitude modulation, pulse width modulation, pulse code modulation are few
modulation systems cropping up from the pulse modulation technique. In pulse
amplitude modulation (PAM) the amplitude of the pulses are varied in accordance
with the modulating signal.
In true sense, pulse amplitude modulation is analog in nature but it forms the basis of
most digital communication and modulation systems. The pulse modulation systems
require analog information to be sampled at predetermined intervals of time.
Sampling is a process of taking the instantaneous value of the analog information at a
predetermined time interval.
The receiver can reconstruct the signal from these samples, provided the sampling
meets the Nyquist criteria. Nyquist criteria states that for a band limited signal with
highest frequency component fm, the signal must be sampled at a rate greater then
twice the highest frequency component in the signal for the sampled signal to be
recovered exactly
i.e fs > 2fm where fs = sampling frequency
The pulse amplitude modulation system can be simulated as shown in fig. 1.

Basic Sampling Process

Fig. 1
The control signal is totally electrically isolated from the information signal. Also the
switch is considered ideal i.e.
• It should offer negligible resistance, when closed and should have infinite
resistance when open.
• The opening and closing operations are delay free.
• The switch is free of contact bounce problem.

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The control signal closes the switch when it is at one level and opens it when it is at
another. When the switch is closed the output voltage is equal to zero volts. The width
of the sample depends upon the time duration for which the switch remained closed.
In practice, the switch is operated electrically. The resulting PAM wave is as shown in
fig. 2.

Use of PLL for TDM Synchronization

Fig. 2
Because of its wideband and analog nature, PAM has restricted of applications for
direct transmission of signals. It is used, for example in instrumentation systems and
in A/D Converters used for computer interfacing. It is also used as an intermediate
stage in the generation of very popular digital modulation system viz. PCM (pulse
code modulation.). Another advantage of PAM is that it allows for multiplexing of the
signals.
MULTIPLEXING
Multiplexing :
Multiplexing is the process of combining signals from different information sources
so that they can be transmitted over a common channel. Multiplexing is advantageous
in cases where it is impracticable and uneconomical to provide separate links for the
different information sources. The price that has to be paid to acquire this advantage
is in the form of increased system complexity and bandwidth.
The two most commonly used methods of multiplexing are
1. Frequency division multiplexing (FDM)
2. Time division multiplexing (TDM)
Frequency Division Multiplexing :
Frequency division multiplexing is the process of combining several information
channels by shifting their signals to different frequency groups within the frequency
spectrum so that they can all be transmitted over a common transmission channel.
The information signals are shifted in different frequency groups by making them
modulate carrier signals at different frequencies e.g. Let us suppose two information

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signals occupy a frequency range of 300 - 3400 Hz speech signal). Only lower side
band is transmitted. The first signal modulates a 64 kHz carrier; the modulated signal
occupies a frequencies band of 60.6 kHz to 63.7 kHz. The second signal modulates a
68 kHz carrier; the modulated signal occupies a frequency band of 64.6 kHz to
67.7kHz. As it can be seen from above example, the modulated signals occupy
different frequency ranges in the frequency spectrum. Hence they can be transmitted
over the same channel. (See fig. 3.)

Frequency Division Multiplexing (FDM)

Fig. 3
At receiver, filters having different pass band frequency range are used to separate the
various information signals. The pass band is chosen so as to extract the information
from one channel. A separation between two modulated signals in frequency band
reduces call interference and also allows for the gradual roll-off gradient of the filters.
Time Division Multiplexing :
Time division multiplexing is the process of combining the samples from different
information signals, in time domain so that they can be transmitted over the same
channel. The fact utilized in TDM technique is that there are large intervals between
the message samples. The samples from the other sources can be placed within these
time intervals. Thus every sample is separated from other in time domain. The time
division multiplexing system can be simulated by two rotating switches, one at
transmitter and the other at receiver. (See fig. 4.) The two wipers rotate and establish
electrical contact with one channel at a time.

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Fig. 4
Each signal is sampled over one sampling interval and transmitted one after the other
along a common channel. Thus part of message 1 is transmitted first followed by part
of message 2, message 3and then again message 1 so on.
It can be anticipated from above process that the receiver switch has to follow two
constraints:
1. It must rotate at the same rate as the transmitter switch.
2. It must start at the same time as the transmitting switch and it must establish
electrical contact with the same channel no. as that of the transmitter. If these
two conditions are met, the receiver is said to be in synchronization with
transmitter. If constraint one is not met, the samples of different sources would
get mixed at the receiver. If constraint two is not met, the information from
source 1 will be received by some other channel which is not intending to
accept the information from that particular channel. To establish
synchronization, the receiver needs to know:
a. Frequency/ rate of operation at transmitter.
b. Sample identification.
This increases the transmitter and receiver complexity and cost.

Fig. 5
Practical Aspects of Time Division Multiplexing :
In time division multiplexing the correct operations of transmitter switch which
creates samples, is a must. The functioning of TDM switch is complex. But its
understanding is easy, provided you are aware of the existence of circuit delays and
setting times. Theoretically large number of samples can be multiplexed in time
domain, but its practical implementation becomes harder and harder as the time
interval between consecutive samples decreases. In ST2102, the operations of
transmitter switch are controlled by the transmitter timing logic. (See fig 6)

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Fig. 6
The opening and closing of particular switch depends upon the decoder output
provided in transmitter timing logic. The decoder's output can be obtained at tp. 7,
8,9,10. Observe that the output at each of these test points is a train of pulses at
frequency 16 kHz and with pulse duration set by the duty cycle selector switch.
The decoder's output depends upon two quantities:
a. Divider output
b. Decoder Enable pulse train which is provided by the duty cycle control signal.
The following table summarizes the switch operation for various inputs to the
decoder.

Divider Output Transmitter Sampling Switches

MSB LSB CH.0 CH.0 CH.2 CH.3

(tp.3) (tp.2) tp.7 tp.8 tp.9 tp.10

0 0 Closed Open Open Open

0 1 Open Closed Open Open

1 0 Open Open Closed Open

1 1 Open Open Open Closed

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The decoder output is decided by the divider output. But the operation takes places
only when the decoder is enabled. The enable signal is active low and it is supplied
from the duty cycle control switch (tp. 4) The switch is closed when a low signal is
applied to it. The duration of a particular switch closing is decided by the duty cycle
control switch whose output drives the enable input of the decoder. For different
setting of the duty cycle switch, the output width driving the decoder's enable input
varies. Hence the duration for which the switch remains closed also varies.
The two control signals to the decoder create a problem. The problem arises when the
decoder enable signal appears while divider output is changing. It causes sampling
error, because the binary code at the divider output may initially correspond to a
different switch. To overcome this problem, the duty cycle output is made to lag by
5% of one channel time slot. This allows the divider output to settle to a constant level
before the enable signal arrives. Figure 7 illustrates the timing of the two signals when
the duty cycle control is set to "9". The period allocated for transmitting one sample is
called as a time slot. On ST2102 four channels are multiplexed. The groups of four
time slots are termed as a frame.

Fig. 7

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Testing Instruments Needed for Experiment

1. Oscilloscope 20 MHz, Dual Trace, ALT Trigger.
2. Oscilloscope probes X1 – X 10 etc.

EXPERIMENT 1
Object :
To understand, synchronization and control signals available on ST2102.
Procedure :
1. Turn ON the power to the trainer. It is indicated by lighting of the power switch.
2. Display the clock signal (tp.5) provided on TRANSMITTER TIMING LOGIC
block. It will be a pulse train. Note that the clock frequency is 64 KHz.
3. Display the clock signal (tp.5) along with channel 0 switch control. Observe the
relation between two signals.
4. Vary the DUTY CYCLE SELECTOR switch and observe the variation in both
signals.
5. Set the DUTY CYCLE SELECTOR Switch to position '5'.
6. Display the waveforms at tp. 8, 9 & 10. Sketch the relative time graph between
the waveforms observed at tp. 5, 7, 8, 9 & 10.
7. With the same links, display the waveform at TX. CH.0 output (tp.6) on channel
1 of the oscilloscope.
8. Observe the waveforms at tp. 7, 8, 9, & 10 on the other channel.
9. Sketch the wave forms in time domain with reference to the TX. CH.0 Signal.

EXPERIMENT 2
Object :
To demonstrate the switching delay and its control on ST2102 with
potentiometer.
As it has been described the switch operation is not delay free. There is always a time
delay between the switch closing and the moment when the control signal was applied
to it.
Procedure :
1. Turn ON the power to the trainer. This is indicated by lighting of power switch.
2. Connect the SYNC LEVER TO TRANSMITTER'S CH.0 input socket with
4mm banana connector. Set voltage level to 5V with the aid of corresponding
potentiometer by observing the signal at tp.11 on oscilloscope.

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3. Set the DUTY CYCLE SELECTOR to position '4'.

4. On the dual channel oscilloscope view the waveforms at tp. 7 & tp. 20. The test
point no. 7 waveform controls the closing of the switch where as waveform at
tp. 20 contain the samples of the input channels.
5. Sketch these waveforms over one complete cycle of waveform at tp.2. Estimate
the delay between the application of control signal (available at tp. 7) and the
sampling (available at tp. 20) to nearest 0.5µs. The delays inherent in operations
are unavoidable but can cause errors if they are too large.
6. To demonstrate the effect of 'DELAY CONTROL' in RECEIVER TIMING
LOGIC, make following links:
a. SYNC LEVEL to CH.0
b. TX. CLOCK to RX. CLOCK
c. TX. CH.0 to RX. CH.0
d. TX. OUTPUT to RX. INPUT.
The variation of DELAY CONTROL Pot varies the time between switch
operations with respect to TDM signal.
7. Turn the DELAY CONTROL potentiometer fully anti-clockwise. Display the
sampled waveform (tp. 20) and the control signal to receiver's channel 0 (tp.35)
on the oscilloscope.
8. Now set the DELAY CONTROL potentiometer fully clockwise. Again display
the sampled waveform (tp.20) and the control signal to receiver channel 0
(tp.35) on the oscilloscope.
9. Note how the waveform at tp. 35 changes with respect to the sample waveform.
Turn the DELAY CONTROL potentiometer fully anti-clockwise to give
minimal delay. Display the waveforms at tp. 35 and tp. 41 on the oscilloscope
simultaneously. These waveforms show the control signal and the extracted
samples in time domain relatively. Measure width of the sample at tp. 41.
10. Turn the DELAY CONTROL Potentiometer fully clockwise. Display the
waveforms at tp. 35 & tp. 41 on oscilloscope simultaneously. Measure the width
of the sample at tp. 41.
11. Sketch the waveform at tp. 20, 35 & 42 relatively in time domain in fully
clockwise and anticlockwise in the case of DELAY CONTROL potentiometer.

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SYNCHRONIZATION

The most vital requirement of a time division multiplexed system is synchronization.

The transmitter and receiver are said to be synchronized when:
1. The rate of operation at transmitter is same as the rate of operation at receiver.
2. Samples can be identified with different channels i.e. timeslot 0 samples must
go to channel 0 output, time slot 1 samples must go to channel 1 output and so
on.
The circuitry that generates the timing signal for the system is called clock. Often the
clock generates periodic rectangular pulses and hence is known as clock pulses. The
question may arise "why is the clock so important?”
As we know, the time division multiplexing and de-multiplexing requires a particular
operation to occur on the precise time interval. Failure to meet this requirement leads
to signal corruption, distortion and even complete system breakdown. The circuit
which ensures precisely timed action is the clock circuit. All the time related
processes derive the timing directly or indirectly from the system clock.
For correct operation of receiver, the switching rate should be same as that for
transmitter. To do this the receiver clock must match with the transmitter
clock.Besides clock signal, the receiver also requires information from the transmitter
to identify one timeslot per frame and so as to pass the time slot to correct output
channel. If it is achieved for one time slot, then other time slots in the frame are
passed to the correct channels. It is ensured by frame synchronization signal.
These two signals namely the clock signal and Frame synchronization signal should
be transmitted by the transmitter along with the information signal. TheTDM PAM
Trainer provides you the flexibility of using three different modes of these
information transfers.
Mode 1 : Three links between transmitter & Receiver (Fig.8)
It gives rise to the most simple receiver circuitry. In this mode a separate transmission
media are used to carry the information signal, the clock signal, and the frame
synchronization signal.
Mode 2 : Two links between transmitter & Receiver (Fig.9)
The number of links between transmitter and receiver can be reduced to two by
embedding the frame synchronization information in the TDM waveform.
However, there is an other way in which the number of links can be reduced to two.
An easy solution to do this is to generate the clock locally at the receiver. This would
remove the need of link for clock signal.
But the above solution is not error-free. The receiver and transmitter clock can at
anytime slip out of synchronization. This may be due to temperature variation,
environmental changes aging of components etc. Hence this solution is not reliable.
The alternate way, which is more reliable, is to extract the clock information from the
frame synchronization signal.

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On TDM PAM trainer, the clock signal is multiple of frame synchronization signal.
The clock frequency is four times that of the frame synchronization frequency. Also
their rising edges occur simultaneously. We may add a circuitry, which can generate
clock signal from the frame synchronization signal on receiver board.
By adding a further circuitry, we can compare the frame synchronization signal to
every fourth receiver clock pulse and generate a control signal. This control signal can
be used to adjust the receiver clock frequency. This will use the correct matching of
transmitter and receiver clock.
Mode 3 : One link between transmitter & Receiver (Fig.10)
The number of links connecting transmitter and receiver can be reduced to one, thus
achieving significant transmission media saving.
Note: The word 'link' refers to one set of dedicated connections and not necessarily
one wire. Though TDM PAM trainer uses one 4mm Banana-Banana connector
because the receiver shares a common ground signal.
The reduction in no. of links is achieved by using one time slot to transmit
synchronization signal along with the information samples. Naturally, this
synchronization signal must be different from the information samples for the receiver
to distinguish it from the other samples. The distinction is achieved by fixing the
amplitude of the synchronization level samples considerably greater than the
maximum information signal amplitude.
Also, because the sync level pulse occurs in the same timeslot in every frame, it
refuses to establish synchronization and to generate the clock at the receiver.
The result is increased complexity. To implement this mode we require the de-
multiplexer to be able to distinguish the synchronization signal from the information
samples. Also, at the transmitter we require a circuitry to ensure that maximum
amplitude of any information signal is limited to less than the synchronization signal
detection level.

Model 1
Three Links Between Transmit Multiplexer and Receiver De-multiplexer
Fig.8

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Model 2
Two Links Between Transmit Multiplexer and Receiver De-multiplexer
Fig.9

Model 3
One Link Between Transmit Multiplexer and Receiver De-multiplexer
Fig.10

EXPERIMENT 3
Object :
To show the importance of frame synchronization signal in receiving the correct
output at correct output channel.
Procedure :
1. Turn 'ON' the Power to the Trainer. It is indicated by lighting ON of the power
switch.
2. Set the DUTY CYCLE SELECTOR Switch to '4'.
3. Make following links.
a. SYNCLEVEL to CH.0
b. TX. OUTPUT to RX. INPUT.
c. TX. CLOCK to RX CLOCK
4. Set the sync levels to 5V with the aid of potentiometer. The sync level can be
observed at tp. 11.

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Also turn the DELAY CONTROL potentiometer fully anticlockwise for

minimum delay.
5. Observe the TX. OUTPUT signal on one channel of the oscilloscope. On other
channel, check the wave from the inputs of all receivers’ low pass filters (tp. 41,
43, 45 & 47).
Find out receiver channel that contains the extracted samples?
6. Remove the TX. CLOCK and RX. CLOCK link momentarily. Replace the link
after a moment.
Now find out receiver channel that contains the extracted samples?
7. Repeat steps 5 & 6 several times. You will probably find the extracted samples
appearing at different output channel after each step.
Why this happened ?

EXPERIMENT 4
Object :
To study the extraction of Sync Pulses from the TDM samples in operating
mode3.
Procedure :
1. Switch 'ON' the power supply. This is indicated by turning 'on' of the power
switch.
2. Ensure that the DUTY CYCLE SELECTOR is in position '5'.
Make following links between FUNCTION GENERATOR block and the
TRANSMITTER block.
a. SYNC LEVEL to CH.0 input
b. ~500Hz to CH.1 input
c. ~1KHz to CH.2 input
d. ~2KHz to CH.3 input
3. Ensure following peak voltage levels at the described test-points by varying the
corresponding potentiometers in the FUNCTION GENERATOR BLOCK.
a. SYNC LEVEL - 7V (at tp. 11)
b. ~500 Hz - 4V (at tp. 13)
c. ~1KHz - 3V (at tp. 15)
d. ~2KHz - 2V (at tp. 17)
This will help you to distinguish, the samples in multiplexed condition.

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4. Observe the TX. OUTPUT (tp.20) on oscilloscope. Use ~500Hz sine wave at
tp.13 for external triggering purpose to obtain the stable display. The sync
pulses are ideally distinct in TDM signal by their highest amplitude.
5. Connect the TX. OUTPUT to RX. INPUT socket. Also turn the
COMPARATOR THRESHOLD LEVEL potentiometer in PHASE LOCKED
LOOP TIMING LOGIC BLOCK fully clockwise. This will ensure the highest
comparator threshold level. The comparator generates a pulse whenever the
voltage level of TDM signal exceeds the comparator's threshold level. Observe
the comparator's output at tp. 22. It will be stream of pulses. Note the frequency
of the output pulse train.
6. By varying the SYNC LEVEL potentiometer in the FUNCTION GENERATOR
block find out the comparator's threshold level to the nearest value.
Keep the fact in mind, that for error free operation of the comparator block, the
SYNC LEVEL amplitude must be well separated from the information signals
amplitude.
7. Set the comparator threshold voltage to 3.5V by varying the COMPARATOR
THRESHOLD LEVEL potentiometer. Set the peak voltage level of the stated
waveforms by verifying the corresponding potentiometers in the FUNCTION
GENERATOR block.
a. SYNCLEVEL - 3.5 V (at tp.11)
b. ~500Hz - 2V (at tp. 13)
c. ~1KHz - 3V (at tp. 15)
d. ~2KHz- 4V (at tp. 17)
8. Observe the output of the comparator block at tp. 22 Explain why the frequency
and wave shape of the output is different in the case?
This exercise demonstrates the importance of the level of sync signals in order
to extract the sync, pulses correctly. Failure to do so causes large amplitude
information signals to generate false pulses for PLL.
If the threshold level is very high the sync pulses or information signals would
generate an output pulse from the comparator and the PLL output would be at
lowest frequency.

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COMPLETE PAM RECEIVER

The receiver circuitry depends upon the choice of the method of Synchronization
employed. Let us review the three modes of connecting the transmitter and receiver.
They are :
Mode 1 : Three links :
Units at receiving End Transmission Link
Receiver TDM samples
Receiver Timing Logic Frame Sync Clock
Features :
1. Simplest receiver
Mode 2 : Two links
Units at receiving End Transmission links
Receiver TDM samples
Receiver timing logic Frame Sync
Phase locked timing Logic
Features :
1. Receiver clock generated by local oscillator.
2. Synchronization obtained from frame synchronization signal.
Mode 3 : One Link
Units at Received End Transmission link
Receiver TDM samples
Receiver Timing Logic
Phase Locked Timing Logic
Features :
1. Synchronization information interlinked with TDM samples.
2. Receiver clock regenerated locally.
Whichever the mode is chosen, the receiver and receiver timing logic are common to
all. These blocks require the following three signals for their operation:
1. TDM samples i.e. Information signal.
2. Timing control signal at RX.CLOCK input SOCKET.
3. Synchronization signal at RX. CH 0 input SOCKET.
Depending upon how we decide to provide these three signals dictates the use of three
correcting modes ?

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Receiver :
The receiver consists of a unity gain buffer, followed by switches and low pass filters.
The input socket viz. RX. INPUT receives the TDM samples. These samples are
passed through the unity gain buffer to prevent its loading. The buffered signals are
passed through the switches, which close at the correct instance of time. The
operation of the switch is controlled by signals from the receiver timing logic
circuitry.
The particular switch closes when the sample corresponding to that particular channel
is chosen. The result is PAM waveform at correct channel.
The PAM signal is demodulated by passing it through the low pass filter. The low
pass filter removes the higher frequency components present with the signal. The
result is the reconstructed waveform at the corresponding channel.
Receiver Timing Logic :
The accurate and error free reproduction of the signals requires pre-use timing
controls of various operations. This function is carried on receiver system by, receiver
timing logic.
The receiver timing logic accepts two input signals viz. RX.CLOCK and RX.CH.0.
These signals may come from the transmitter or receiver itself. The receiver timing
logic operates the receiver switch in a manner similar to the transmitter switch
operation.
The RX.CLOCK signal ticks a two bit binary counter. The outputs of the two bit
binary counter are passed to a decoder which identifies which particular switch is to
be closed e.g. If the binary count is 01, the switch corresponding to channel1 will
close.
To ensure that the count always starts at 0, the binary counter is reset by the frame
synchronization signal at start of every frame. (Provided by RX.CH.0 input)
Thus the operation of switch in receiver system is similar to that of the transmitter
system except for a fact that in receiver the switches are closed for the whole
durations of the particular channel. It is unlike that in the transmitter system where the
closing of switch depends upon the timing as well as the duty cycle selected.
As the switch is closed for its whole duration, the decoder does not require an enable
signal.

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PHASE LOCKED LOOP

The Phase Locked Loop serves as a synchronized clock generator in case when the
transmitter clock is not transmitted. (As in connecting mode 2 & 3).
Simple local oscillator serves the solution for simple defects like oscillator drift,
component aging power fluctuations. All these variations cause the oscillator to step
out of synchronization which is most vital for the TDM systems.
Phase Locked Loop (PLL) has' very wide range of applications e.g. it is used in AM
& FM demodulation, frequency multiplication, pulse regeneration and
synchronization to name a few. The following lines describe the basic blocks and
operations of the Phase Locked Loop (PLL) See fig. 11.
The heart of PLL is the voltage controlled oscillator (VCO). The frequency of the
signal generated by VCO is dependent upon the DC voltage applied to its input.
Higher the applied voltage higher is the frequency with suitable feedback; it is
possible to generate the signal which is in synchronization with phase and frequency
of a received input signal.
The next important block of PLL circuit is the phase comparator / detector circuit.
The function of this block is to compare the phase difference between the two applied
input signals and generate an output proportional to their difference.

Basic Operation of Phase Locked Loop

Fig. 11

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If the phase comparator input signals rising edge does not occur simultaneously with
that of the input signal at other terminal, the phase comparator generates an error
signal. This will be the case when the input signals are unmatched. i.e. either they
have different frequency or have phase difference.
The error signals are either lead or lag phases which are passed to a low pass filter.
This filter is generally referred as loop filter since it forms past of the PLL loop. The
loop filter extracts the mean level information of the input error signals. This mean
level depends upon the Phase/Frequency difference of the two inputs to the applied to
the phase comparator. More the Phase/Frequency difference larger is the mean level.
The loop filter's capacitor holds the mean level information which is applied to the
VCO's control input.
When the mean level is constant, the VCO output at constant frequency between error
pulses. Error pulses either raise or lower this level to correct the VCO output
frequency and therefore align the phase comparator input signals. If the input
frequency is greater than the oscillator output frequency the error pulses generated
increase the VCO output frequency by increasing the mean level.
If the input frequency is lesser than the oscillator output frequency the error pulses
generated decreases the VCO output frequency by decreasing the mean level.
In this manner the PLL generates and synchronized clock signal. There are few
terminologies related to PLL with which you should be familiar:
1. Hold in Range or Locked Range :
When the frequency PLL is synchronized to that of the signal is said to be
locked. Once locked, the PLL output will be synchronized to the input signal
over a limited frequency range. This frequency range is called as hold in range
for locked range.
If the frequency range of the input signal is very different from the natural
frequency of the PLL, it may never be able to lock on to it.
2. Capture Range :
It is defined as the range of frequencies over which the PLL can initially lock. In
general Locked Range is large than the capture range. OnTDM PAM trainer the
locked range and the capture ranges are same.
It is not necessary that the output of VCO can only be square wave. Although
square wave output is generated by VCO onTDM PAM trainer, the output can
be obtained as a sine wave, triangular wave or other wave forms by having a
suitable PLL.
PLL as Frequency Multiplexer :
One of the most important uses which the PLL can be put to is the frequency
multiplier circuit. If on output frequency desired is N times the frequency applied to
the input, it can simply be obtained by placing a module-N counter between the VCO
output and the phase comparator input.

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e.g. if the desired PLL output frequency is four times the applied input frequency,
place a module 4 counter between VCO output and phase comparator input. See
fig.12

Phase Locked Loop

Fig. 12
The module-4 counter can be simulated by using the third bit output of a binary
counter. The third bit output provides one output pulse for every four input pulses.

TDM SYNCHRONIZATION
As we have studied that receiver system requires both the synchronization signal and
the clock signal for its accurate operation. Fortunately, the PLL can provide both
information since onTDM PAM trainer, the channels are sampled once per frame and
the total number of channels is four. The clock frequency is four times the frame
synchronization frequency. Because the frame synchronization signal and the clock
signal are related, these two signals can be obtained from one PLL as shown in
fig. 13.

Use of PLL Circuit for TDM Synchronization

Fig. 13
The timing of switch operation relative to the TDM waveform is also vital. To ensure
the correct operation, one way is to use the leading edge of receiver switch control
signal to operate the required channel switch.
This is perfectly acceptable in ideal conditions. However, in practice many devices
introduce delays between input and output signals and hence the closing of the switch
may not be exactly aligned to the TDM sample. The result of a mismatch is as shown
in fig. 14.

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Fig. 14
Also as the duty cycle decreases the adverse effect of delays become greater. A
solution of this problem is to extract the samples by operating the switches mid way
between the samples. See fig. 15.

Fig. 15
To cause the operation to start midway between the samples, we require advancing
the receiver control pulse cycle relative to TDM samples. This is achieved by
inserting delay element between the VCO an output and the binary counter input. See
fig 13.
The delay element may be a monostable. This causes the clock pulses to slightly
advance in time.
The input to the PLL is the frame synchronization signal. The frame synchronization
signal can be obtained in two ways:
1. From TX.CH.0 output (Mode 2). This requires a separate link.
2. By including the sync information within the sample (Mode 3).

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This reduces the number of links to one. As it has been described, the sync pulses
have amplitude greater than the highest possible amplitude of other channel's samples.
At receiver system a voltage comparator is used to extract the sync information. The
voltage comparator compares the incoming TDM samples with a reference level (or
threshold level). The threshold level is set such that it is greater than the maximum
amplitude of information signals but is lower as compared to the sync pulse
amplitude. The voltage comparator provides an output pulse each time a sample goes
above the threshold level. See fig. 16.

CH 0 CH 2 CH 3 CH 0 CH 1 CH 2 CH 3 CH 0 CH 1 CH 2 CH 3
Fig. 16
The output is a pulse per frame which is an indication of the Time slot 0 in the TDM
signal. This pulse is utilized by the PLL to generate the clock and sync information.

EXPERIMENT 5
Object :
To demonstrate how the PLL locks a particular signal.
As it has been described earlier, the Phase Locked Loop is used in connecting mode 2
& 3 to generate synchronization information and the clock signal.
We will now investigate the control signals and the output of various sub-clocks of
the PLL circuit. This will help to understand the process by which the PLL locks to
the signals and generate the sync pulses and the clock signal.
Procedure :
1. Turn ON the power to the trainer. This is shown by the lighting of the power
switch.
2. Ensure that the DUTY CYCLE SELECTOR switch is in position '5'.
3. Note the PLL's output frequency at tp. 28, without any input applied to it. It is
the lowest frequency generated by the PLL. Explain why this is so?

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4. To see how the PLL output frequency changes when the PLL locks to an input
signal make following changes in the system configuration.
a. Push the level of the toggle switch in PHASE LOCKED LOOP TIMING
LOGIC block in upward position. This connects the PLL blocks input to
the PLL I/P socket.
5. Make the link between TX.CH 0 output socket in TRANSMITTER TIMING
LOGIC block of the PLL I/P socket. This causes the PLL to lock the sync signal
of 16 KHz.
6. Observe the input and output waveforms at tp. 23 and 28 respectively. The PLL
output signal is the SYNC signal used for frame sync by the receiver.
7. Observe the waveforms at tp. 28 (SYNC signal) and tp. 26 (CLOCK signal) on
the oscilloscope. Notice that there is a delay between the two signals.
Measure this delay and observe the relation between SYNC output frequency
and the CLOCK output frequency.

EXPERIMENT 6
Object :
To interconnect the various functional blocks and to observe the overall effect of
the individual parameter/ mode on the communication system. (Complete TDM
PAM System)
Procedure :
1. Set the duty cycle control switch in position '5'.
2. Turn the all potentiometers in FUNCTION GENERATOR block viz SYNC
LEVEL, 250Hz, 1 KHz, 2KHz fully clockwise.
3. Turn the potentiometer marked COMPARATOR THRESHOLD LEVEL in
PHASE LOCKED LOOP TIMING LOGIC block fully clockwise.
4. Ensure that the DELAY CONTROL pot in RECEIVER TIMING LOGIC block
is fully anticlockwise.
5. Make following connections with 4mm banana to banana connectors:
a. 250Hz to CH.0 input socket of TRANSMITTER block.
b. 500Hz to CH1 input socket of TRANSMITTER block.
c. 1 KHz to CH.2 input socket of TRANSMITTER block.
d. 2 KHz to CH.3 input socket of TRANSMITTER block.
6. Turn ON the power to the trainer. It is indicated by the turning ON of the
ON/OFF Switch.

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7. Observe the TX. OUTPUT (tp. 20) along with CH.0 input (tp.11) for reference
with the aid of oscilloscope. Use TRANSMITTER'S CH.0 INPUT for external
triggering of oscilloscope. This will help to achieve a stable waveform.
The TRANSMITTER CIRCUIT samples all channels at different time intervals.
The time division multiplexed samples appear at the TX.OUTPUT (tp.20). Vary
the amplitude of the input sine-waves by varying the potentiometers in the
FUNCTION GENERATOR block. This will help in identifying which sample
belongs to which input channel.
8. Ensure all the potentiometer in the FUNCTION GENERATOR block is turned
fully clockwise before continuing with the exercise.

EXPERIMENT 7
Object :
To Observe output waveforms at receiver channels, ch1/ ch2/ ch3 on oscilloscope
& observe preservation of dc level in output waveform compared to input signal.
Procedure :
1. Make the following connections with banana connectors:
a. TX. OUTPUT to RX. INPUT
b. TX. CLOCK to RX. CLOCK
c. TX. CH.0 to RX. CH.0
This ensures mode1 operation of theTDM PAM trainer (see diagram1) for
interconnections) TX.CLOCK signal is used by the receiver to synchronies its
activity & TX. CH.0 signal is used by the receiver to know which sample
belongs to channel 0.
2. With the help of oscilloscope, observe the TX.OUTPUT signal (tp.20) & the
RECERVER'S CH.0 LOW PASS FILTER'S input (tp. 41)
The oscilloscope displays the extracted sample corresponding to channel 0 from
the time division multiplexed samples.
3. Display the RECEIVER'S LOW PASS FILTER'S input (tp.41) & output (tp.42)
simultaneously on the oscilloscope. The signal at tp. 42 shows the reconstructed
~250Hz sine wave which was transmitted at CH.0.
Similarly view the outputs of all RECEIVER LOW PASS FILTERS at tp. 44,
46, 48. Observe that each of the original sine waves has been correctly
reconstructed.
4. The DUTYCYCLE SELECTOR switch is presently in position 5 i.e. the
duration of each sample is 50% of the timeslot allotted to each channel.

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The DUTY CYCLE SELECTOR Switch can be varied from 0% to 90% in steps
of 10%. Display TX. OUTPUT (tp.20) and receiver CH.0 output (tp.42) on the
oscilloscope.
Now vary the DUTY CYCLE SELECTOR switch. Notice the effect of variation
DUTY CYCLE SELECTOR SWITCH ON TX. OUTPUT & amplitude of the
RECEIVER'S CH.0 OUTPUT.
The RECEIVER'S CH.0 output increased with the increasing sampling duty
cycle. This is due to the fact that the ST2102's Low Pass Filters are not preceded
by the SAMPLE/ HOLD Circuitry.
5. Return the DUTY CYCLE SELECTOR Switch to position '5'.
6. The three links required between transmitter & receiver in Mode 1 of operation
can be reduced to two in Mode 2. To configure the trainer in mode 2 of
operation, disconnect TX.CH.0 & RX.CH.0 link & make following new links.
a. TX.CH.0 to PLL UP
b. SYNC to RX.CH.0
c. PLL O/P to RX. CLOCK
Also ensure that the level of toggle switch in PHASE LOCKED LOOP TIMING
LOGIC is in upward position. The configuration is given in Fig.18.
7. The Phase Locked Loop locks onto the TX.CH.0 signal & produces two outputs.
a. SYNC: This serves the same purpose as TX.CH.0, RX.CH.0 link i.e. it
tells the Receiver which of the transmitted signal belongs to channel 0.
b. CLK : It is used to clock the receiver.
These signals can be examined on tp. 28 & 26 respectively.
8. Observe the receiver's CH.0, CH1, CH.2 & CH.3 output on the oscilloscope (tp.
42, 44, 46 & 48). Notice that the wave shapes are still preserved in mode 2.
9. The number of links can be further reduced to one link in mode 3. In this
operational mode, the sync pulse are transmitted along with the other samples in
channel 0 timeslot i.e. channel 0 is dedicated to carry sync pulses. To configure
the trainer in mode 3 of operation, remove following links.
a. ~250Hz to TRANSMITTER'S CH.0 Input
b. TX.CH.0 to PLLIP SOCKET.
Now establish the following connections,
a. SYNC LEVEL in FUNCTION GENERATOR BLOCK to
TRANSMITTER'S CH.0 Input.
b. Ensure that the toggle level in PHASE LOCKED LOOP TIMING LOGIC
BLOCK is in upward position.
The configuration is as shown in diagram 3.

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10. Display TX.OUTPUT & Transmitter's CH 1 input (tp.13) on the oscilloscope.

Use Transmitters CH.1 INPUT for scope triggering (in EXT TRIG mode). Vary
the SYNC LEVEL preset & observe how the sync pulses change in amplitude.
Return the SYNC LEVEL Pot to fully clockwise position. These sync pulses are
fed to the voltage comparator which extracts the sync pulses. The threshold level
of the comparator has been set such that it can easily distinguish between sync
pulses & the other samples. These sync pulses are fed to the PHASE LOCKED
LOOP circuitry which locks on to the sync pulse, and generates sync clock
signal as in mode 2.
11. Observe the RECEIVER'S CH 1, CH.2 & CH.3 Outputs (tp. 44/46/48) on
oscilloscope. Notice that the wave shapes still preserved in mode 3. RECEIVER
CH.0 output (tp. 42) is having DC level related to the amplitude of the
transmitted sync pulses.

Mode 1
Fig.17

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Mode 2
Fig.18

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Mode 3
Fig.19

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WARRANTY
1) We guarantee the instrument against all manufacturing defects during 24
months from the date of sale by us or through our dealers.
2) The guarantee covers manufacturing defects in respect of indigenous
components and material limited to the warranty extended to us by the original
manufacturer, and defect will be rectified as far as lies within our control.
3) The guarantee will become INVALID.
a) If the instrument is not operated as per instruction given in the instruction
manual.
b) If the agreed payment terms and other conditions of sale are not followed.
c) If the customer resells the instrument to another party.
d) Provided no attempt have been made to service and modify the instrument.
4) The non-working of the instrument is to be communicated to us immediately
giving full details of the complaints and defects noticed specifically
mentioning the type and sr. no. of the instrument, date of purchase etc.
5) The repair work will be carried out, provided the instrument is dispatched
securely packed and insured with the railways. To and fro charges will be to
the account of the customer.

DISPATCH PROCEDURE FOR SERVICE

Should it become necessary to send back the instrument to factory please observe the
following procedure.
1) Before dispatching the instrument please write to us giving full details of the
fault noticed.
2) After receipt of your letter our repairs dept. will advise you whether it is
necessary to send the instrument back to us for repairs or the adjustment is
possible in your premises.
Dispatch the instrument (only on the receipt of our advice) securely packed in original
packing duly insured and freight paid along with accessories and a copy of the details
noticed to us at our factory address.

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LIST OF SERVICE CENTERS

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LIST OF ACCESSORIES
1. Patch cord 8" ................................................................................................5
2. Patch cord 16"...............................................................................................3
3. Patch cord 20"...............................................................................................1
4. Mains cord....................................................................................................1
5. Operating manual & work book ....................................................................1
6. Dust cover ....................................................................................................1
7. CD (Demo VCD) provided with full set only.
8. DCT book provided with full set only.

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