Name of the Course: EEC346-DIGITAL DESIGN WITH VERILOG

Topic for the class: MODULE II -Gate Level modelling

2(Sequential circuits)
Date & Time :3/3/2021

Dr T.Gowri
Assistant Professor
Department of EECE
GITAM Institute of Technology (GIT)
Visakhapatnam – 530045
Email: [email protected]

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Latch
Design of flip-flops with gate primitives

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module srff_gate(q, qbar, s, r, clk);
input s,r,clk;
output q, qbar;
wire nand1_out; // output of nand1
wire nand2_out; // output of nand2
nand (nand1_out,clk,s);
nand (nand2_out,clk,r);
nand (q,nand1_out,qbar);
https://technobyte.org/sr-flip-flop-verilog-gate-
nand (qbar,nand2_out,q); dataflow-behavioral/
endmodule
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//test bench
module SR_test;
reg s,r,clk;
wire q, qbar;
srff_gate(q, qbar, s, r, clk);
Initial $monitor(“$time = %d, clk = %b, s = %b, r = %b, q = %b,
qbar = %b", clk, s, r, q, qbar); // apply test vectors
initial
begin clk=0;
forever #10 clk = ~clk;//Always #10 clk = ~clk;
end
Initial
begin s= 1; r= 0;
#100; s= 0; r= 1;
#100; s= 0; r= 0;
#100; s= 1; r=1;
end
endmodule

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module D_FFgate(q,qbar,d,clk); input
d,clk;
output q, qbar;
Wire dbar, w1, w2;
not not1(dbar,d);
nand nand1(w1,clk,d);
nand nand2(w2,clk,dbar);
nand nand3(q,qbar,w1);
nand nand4(qbar,q,w2);
endmodule

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//test bench for d flip flop
//1. Declare module and ports
module dff_test;
reg D, CLK;
wire Q, QBAR;
//2. Instantiate the module we want to test. We have instantiated the D_FFgate
D_FFgate dut(.q(Q), .qbar(QBAR), .d(D), .clk(CLK));
// instantiation by port name.
//3. Monitor TB ports
$monitor("simtime = %g, CLK = %b, D = %b, Q = %b, QBAR = %b", $time, CLK, D, reset, Q, QBAR);
//4. apply test vectors
initial
Begin
CLK=0;
forever #10 CLK = ~CLK;
end
Initial
begin
reset=1;
D <= 0; #100;D <= 1; #100; D <= 0; #100; D <= 1;
End
endmodule

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module jkff_gate(q,qbar,clk,j,k);
input j,k,clk;
output q,qbar;
wire nand1_out;
// output from nand1
wire nand2_out;
// output from nand2
nand(nand1_out, j,clk,qbar);
nand(nand2_out, k,clk,q);
nand(q,qbar,nand1_out);
nand(qbar,q,nand2_out);
endmodule
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//test bench for JK flip flop
//1. Declare module and ports
module jkff_test;
reg j,k, clk;
wire q, qbar;
//2. Instantiate the module we want to test. We have instantiated the
jkff_gate dec(q,qbar,clk,j,k);
$monitor($time, “clk = %b, j = %b, k = %b, q = %b, qbar = %b“, clk, j, k, q, qbar);
//4. apply test vectors
initial
begin clk=0;
forever #10 clk = ~clk;
end
Initial
begin
j= 1; k= 0;
#100; j= 0; k= 1;
#100; j= 0; k= 0;
#100; j= 1; k=1;
end
endmodule

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 T Clk q
module Tff_gate(q,qbar,clk,T);
input T,clk; 0 1 q
output q,qbar; 1 1 qb
wire nand1_out;
x 0 q
// output from nand1
wire nand2_out;
// output from nand2
nand(nand1_out, T,clk,qbar);
nand(nand2_out, T,clk,q);
nand(q,qbar,nand1_out);
nand(qbar,q,nand2_out);
endmodule
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Edge triggered D-Flip-flop (IC 7474)

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Gate Delays

• Until now, we described circuits without any delays (i.e., zero delay). In real circuits, logic gates
have delays associated with them. Gate delays allow the Verilog user to specify delays through the
logic circuits. Pin-to-pin delays can also be specified in Verilog.
Rise, Fall, and Turn-off Delays

There are three types of delays from the inputs to the output
of a primitive gate.
Rise delay
The rise delay is associated with a gate output transition to a
1 from another value.

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Fall delay
The fall delay is associated with a gate output transition to a 0 from another value.

Turn-off delay
The turn-off delay is associated with a gate output transition to the high impedance value (z) from
another value.
If the value changes to x, the minimum of the three delays is considered.

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Example--Types of Delay Specification

//Delay of delay_time for all transitions and #(delay_time) a1(out, i1, i2);

// Rise and Fall Delay Specification. and #(rise_val, fall_val) a2(out, i1, i2);
// Rise, Fall, and Turn-off Delay Specification

bufif0 #(rise_val, fall_val, turnoff_val) b1 (out, in, control);

Examples of delay specification are shown below.

and #(5) a1(out, i1, i2); //Delay of 5 for all transitions

and #(4,6) a2(out, i1, i2); // Rise= 4, Fall = 6

bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off = 5

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Delays:
• Verilog has the facility to account for different types of propagation delays of circuit elements.
• Any connection can cause a delay due to the distributed nature of its resistance and capacitance.
• Similar delays are present in gates too.
• These manifest as propagation delays in the 0 to 1 transitions and 1 to 0 transitions from input to the output.

1 .Net Delay
One of the simplest delays is that of a direct connection – a net. It can be part of the declaration statement
wire #2 nn; // nn is declared as a net with a propagation delay of 2 time steps
Here nn is declared as a net with an associated propagation delay of 2 time
steps. The delay is the same for the positive as well as the negative transitions.

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 Wire# (2, 1) nm;
Here nm is declared as a net with two distinct propagation delays; the positive
(0 to 1) transition has a delay of 2 time steps associated with it. The negative (1 to 0) transition has
a delay of 1 time step.

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 2 Gate Delay
• Gates too can have delays associated with them. These can be specified as part of the
instantiation itself.
and #3 g ( a, b, c);
• The above represents an AND gate description with a uniform delay of 3 ns for all transitions
from input to output. A more detailed description can be as follows:
and #(2, 1) (a, b, c);
• With the above statement the positive (0 to 1) transition at the output has a delay of 2 time steps while the negative (1 to
0) transition has a delay of 1 time step.

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 3. Delays with Tri-state Gates

For tri-state gates the delays associated with the control signals can be different from those of the input as well as the output.

1. The first number represents the delay associated with the positive (0 to 1) transition of the output.
2. The second number represents the delay associated with the negative (1 to 0) transition of the
output.
3. The third number represents the delay for the output to go to the hi-Z state as
the control signal changes from 1 to 0 (i.e., ON to OFF command).

bufif1 @ (1, 2, 3) b1(ao, ai, c);

Delay for the 0 to 1 transition of ao
Delay for the 1 to 0 transition of ao
Delay for the output to go to the hi-z state as c changes from 1
to 0
Delays for the other tri-state buffers – namely bufif0, notif1 and
notif0 – may be specified in a similar manner.

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 Normally the delay time of any IC varies over a range for ICs from different production
batches (as well as in any one batch). It is customary for manufacturers to specify
delays and their range in the following manner:
Max delay: The maximum value of the delay in a batch; that is, the delay encountered in practice is guaranteed to be
less than this in the worst case.
Min. delay: Minimum value of delay in a batch; that is, the specified signal is guaranteed to be available only
after a minimum of time specified.
Typ. delay: Typical or representative value of the delay. Each of the delays in a gate primitive or for a net can be
specified in terms of these three values. For example
and #(2:3:4) g1(a0, a1, a2); -----for rise and fall same

and #(1:2:3, 2:4:6) g2(b0, b1, b2); -----for rise and fall different
• Here for the 0 to 1 transition of the output (rise time) the gate has a minimum delay value of 1
ns, a typical value of 2 ns, and a maximum value of 3 ns. Similarly, for the 1 to 0 transition
(fall time) the gate has a minimum delay value of 2 ns, a typical delay value of 4 ns, and a
maximum delay value of 6 ns.
• Such delay specifications can be associated with nets as well as tri-state type gates also.
Examples
wire #(1:2:3) a; /* The net a has a propagation delay whose minimum, typical
and maximum values are 1 ns, 2 ns, and 3 ns, respectively*/

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 bufif1 #(1:2:3, 2:4:6, 3:6:9) g3 (a0, b0, c0);
The different delay values for the buffer are as follows:
1. The output rise time (0 to 1 transition) has a minimum value of 1
ns, a typical value of 2 ns and a maximum value of 3 ns.
2. The output fall time (1 to 0 transition) has a minimum value of 2
ns, a typical value of 4 ns and a maximum value of 6 ns.
3. The output turn-off time (1 to 0) has a minimum value of 3 ns, a
typical value of 6 ns, and a maximum value of 9 ns. */

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 STRENGTHS AND CONTENTION RESOLUTION
• In practical situations, outputs of logic gates and signals on nets in a circuit have associated
source impedances.
• When the outputs of two gates are joined together, the signal level is decided by the relative
magnitudes of the source impedances.
• Signal strength declarations are of two types – those associated with outputs of gate primitives
and those with nets.

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 Strength Contention in Gate Primitives
The logic levels taken by the signal o for different combinations of inputs to the two
buffers g1 and g2 are shown in Table

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The output logic values for different input combinations are given in Table. The gate
outputs are decided by following the same logic as in the last case. However, in one
case — when both gates “drag” the output with equal strength in opposite directions
— the output logic level is indeterminate —
that is, x.

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Net Charges
a charge storage capacity is associated with the net. Such nets are declared
with the keyword --trireg.
A trireg net can be in one of two possible states only:
• Driven state: When driven by a source or multiple sources, the net assumes the
strength of the source. It can be any of the strengths specified in Table except the
high impedance value.
• Capacitive state: When the driven source (sources) is (are) tri-stated, the net retains
the last value it was in – by virtue of the capacitance associated with it. The value
can be 0, 1 or x (but not the high impedance value).
• When in the capacitive state, a net can have a storage strength associated with it.
Three such storage strengths are possible – namely large, medium, and small
. Their details are shown in Table

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NET TYPES
wand and wor Types of Nets

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