Registers

A register is a small and temporary storage unit inside a

computer's CPU. It plays a vital role in holding the data
required by the CPU for immediate processing and is made
up of ip- ops it usually holds a limited amount of data
ranging from 8 to 64 bits, depending on the processor
architecture.

Shift Registers

Ship register is a group of ip- ops used to store multiple

bits of data. The bits stored in such registers can be made
to move within the registers and in/out of the registers by
applying clock pulses. An n-bit Shift register can be formed
by connecting n ip- ops where each ip- op stores a
single bit of data. The registers which will ship the beats to
the left are called “Shift left registers”. The registers which
will ship the beats to the right are called “shift right
registers”.

Types of Shift Registers

• Serial in serial out shift register (SISO)

• Serial in parallel out shift register (SIPO)
• Parallel in serial out shift register (PISO)
• Parallel in parallel out shift register (PIPO)
• Bidirectional shift register
• Universal shift register
• Shift register counter
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 Serial-in Serial-out Shift Register (SISO)

The shift register, which allows serial input (one bit after the
other through a single data line) and produces a serial
output is known as serial in serial out shift register. Since
there is only one output, the data leaves the shift register
one bit at the time in a serial pattern, does the name serial-
in serial-out shift register. the circuit consist of four D ip-
ops which are connected in a serial manner. All these ip-
ops are synchronous with each other since the same clock
signal is applied to each ip- op.

The above circuit is an example of a shift right register,

taking the serial data input from the left side of the ip- op.
The main use of a SISO is to act as a delay element.

Serial-in Parallel-out Shift Register (SIPO)

The shift register, which allows serial input (one bit after the
another through a Single data line) and produces a parallel
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 Serial-in Parallel-out Shift Register (SIPO)

output is known as serial-in parallel-out Shift register. The

circuit consist of four D ip- ops which are connected. The
clear (CLR) Signal is connected in addition to the clock
signal to all four ip- ops in order to reset them. The output
of the rst ip- op is connected to the input of the next ip-
op and so on. All these ip- ops are synchronous with
each other since the same clock signal is applied to each
ip- op.
The above circuit is an example of a shift right register,
taking the serial data input from the left side of the ip- op
and producing a parallel output. They are used in
communication lines where Demultiplexing of a data line
into several parallel lines is required because the main use
of the SIPO register is to convert serial data into parallel
data.

Parallel-in Serial-Out Shift Register (PISO)

The shift register, which allows parallel input and produces

a serial output is known as a parallel-in serial-out shift
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 register. the circuit consist of four D ip- op which are
connected. The clock input is directly connected to all the
ip- op for the input data is connected individually to each
ip- op through a multiplexer at the input of every ip- op.
The output of the previous ip- op and parallel data input
are connected to the input of the MUX and the output of
MUX is connected to the next ip- op. All these ip- ops
are synchronous with each other since the same clock
signal is applied to each ip- op.

Parallel-in Serial-out Shift Register (PISO)

Parallel-in Parallel-out Shift Register (PIPO)

The shift register, which allows parallel input and also
produces a parallel output is known as parallel in parallel
out shift register. The circuit consist of four D ip- op which
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 are connected. The clear (CLR) Signal and clock signals are
connected to all four ip- ops. In this type of register, there
are no inter connections between the individual ip- op
since no serial shifting of the data is required. Data is given
as input separately for each ip- op and in the same way,
output is also collected individually from each ip- op.

Parallel-in Parallel-out Shift Register (PIPO)

It is used as a temporary storage device and like SISO shift

register it acts as a delay element.

Bidirectional Shift Register

Bidirectional shift registers are the registers that are

capable of shifting the data either right or left depending on
the mode [Link] the mode selected is 1 (high),the data
will be shifted toward the right direction and if the mode
selected is 0 ( low ) ,the data will be shifted towards the left
direction. The circuit consist of four D ip- ops which are
connected. The input data is connected at two ends of the

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 circuit and depending on the mode selected only one gate
is in the active state.

Bidirectional Shift Register

Universal Shift Register

Universal shift register is a type of register that contains the

both right shift and the left shift. It has also parallel load
capabilities. Generally, these types of registers are taken as
memory elements in computers but the problem with this
type of register is that it shifts only in One Direction. N-bit
universal shift register consist of ip- ops and Multiplexers.
Both are N in size. In this, all the n multiplexers share the
same select lines and this select inputs select the suitable
input for ip- op.
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 Universal Shift Register

Shift Register Counter

Shift register counters are the shift registers in which the

outputs are connected back to the inputs in order to
produce particular sequences. There are basically two
types

• Ring Counter
• Johnson Counter

Ring counter
Ring counter is basically a shift register counter in which
the output of the rst ip- op is connected to the next ip-
op and so on and the output of the last ip- op is again
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 fed back to the input of the rst ip- op, thus the name ring
counter. The data pattern within the shift register Will
circulate as long as clock pulses are applied. The logic
circuit given below shows a ring counter.

Ring Counter Truth Table

It has four D ip- ops which are connected. Ring counter is

generally used because it is self decoding. No extra
decoding circuit is needed to determine what state the
counter is in.

Ring Counter
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 Johnson Counter
A Johnson counter is basically a shift register counter in
which the output of the rst ip- op is connected to the
next ip- op and so on so on and the inverted output of the
last ip- op is again fed back to the input of the rst ip-
op. They are also known as twisted ring counters. The
logic circuit given below shows a Johnson counter and has
four D ip- ops which are connected.

Johnson Counter Truth Table

An n-stage Johnson Counter yields a count sequence of

2n di erent states, thus also known as a mod-2n counter.
Since the circuit consists of four ip ops the data pattern
will repeat every eight clock pulses as shown in the truth
table. The main advantage of the Johnson Counter is that it
only needs n number of ip ops compared to the ring

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 counter to circulate a given data to generate a sequence of
2n states.

Johnson Counter

Applications of Shift Registers

• The shift registers are used for temporary data storage.

• It is also used for data transfer and data manipulation.

• The SISO and PIPO shift registers are used to produce

time delay to digital circuits.

• The SIPO register is used to convert serial data into

parallel data thus they are used in communication lines
where demultiplexing of a data line into several parallel
lines is required.

• A PISO shift register is used to convert parallel data to

serial data.
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 Basic concept of Synchronous and
Asynchronous
counters (detail design of circuits excluded)

There are two types of counters in digital logic circuit that

are used to count the numbers of bits and these types
depends upon the clock pulse applied to the ip- ops.

[Link] Counter

A synchronous counter is a type of digital counter where

the same clock signal dries all the ip- ops that stored the
binary value. This means that all the ip- ops change their
states simultaneously with each clock pulses. These are the
counters in which we use a universal clock that is common
to all ip- ops.

Synchronous Counter
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 It is faster than asynchronous counters because there's no
ripple e ect or Delay from one ip- op to the next. Easier to
design with high-speed applications in mind.

It is used in high-speed counting applications, like in digital

clocks or frequency dividers.

[Link] Counter

In an asynchronous counter, ip- ops are not all clocked

together. Instead, each ip- op’s output triggers the clock
input of the next ip- op. These are the counters in which

Asynchronous Counter

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 we do not use universal clock, main clock is only applied to
the rst ip- op and then for the rest of ip- ops output of
previous ip- op is taken as a clock.

Only the rst ip- op is connected to the clock signal. The

output of each ip- op provides the clock pulses for the
next ip- op in the chain, causing a ripple e ect.

Simple for design since fewer gates are required. Suitable

for low speed applications. It is used in simple applications
where speed is not critical, such as timers or basic counting
circuits.

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 Difference bet ween synchronous and
asynchronous counter

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 Design of Mod N Counter

Notebook……..

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