FSiC 2022 - Matthias Köfferlein

KLayout DRC/LVS FAQ +

Tutorial
Frequently Asked Questions – Explained

1 / 43 Matthias Köfferlein, [Link]

 Prologue and Disclaimer

This is not a beginner’s tutorial

about DRC or LVS with KLayout
FSiC 2022 - Matthias Köfferlein

:(

For a basic introduction see here:

[Link]

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 Structure

Demo files and source code available here:

[Link]
(shown as “...”)
FSiC 2022 - Matthias Köfferlein

Master topics
●
General
●
DRC
●
LVS
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 FSiC 2022 - Matthias Köfferlein

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General
 Raw scripts vs. DRC / LVS
Raw scripts: DRC and LVS scripts:
●
Can be either Python or Ruby ●
Use Ruby always
●
Act directly on the application ●
Act as facade for API (A “domain
API specific language”)
●
Rich capabilities (UI generation, ●
Simple language for verification
PCell coding, Layout creation, and layout manipulation purposes
computational geometry ..) ●
Direct access to API is possible,
FSiC 2022 - Matthias Köfferlein

●
API knowledge required but not encouraged

[Link] [Link]

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 How to run DRC from Python?
Yes, the preferred way is through [Link]

Demonstrates:
●
Calling DRC
from Python
●
Sharing objects
FSiC 2022 - Matthias Köfferlein

between Python
and DRC (Ruby)

executes DRC script

DRC script: [Link] – adds layer 2/0

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.../python/call_drc_from_python/drc_from_python.lym
 How to modularize DRC/LVS?
Method 1: the standard way “instance_eval”

evaluates file in
DRC context

Issue: code inside included file can modify variables

FSiC 2022 - Matthias Köfferlein

in calling scope, but not create new ones

need to define variable here, so the included file can
pass the value back to the calling scope

“include_me.drc”:

7 / 43 .../drc/include/[Link]
 How to modularize DRC/LVS?
Method 2: KLayout preprocessor

Included file “include_me.drc”:

FSiC 2022 - Matthias Köfferlein

●
This is not standard Ruby!
●
KLayout text-substitutes the pseudo-comment by the
included file
●
Paths are resolved relative to calling file
●
The interpreter’s source file and line number information
may not be accurate
8 / 43 .../drc/include/[Link]
 FSiC 2022 - Matthias Köfferlein

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DRC
 How to check every layer?
Example: grid check on all layers
FSiC 2022 - Matthias Köfferlein

gives you every layer that is in the source layout

Direct execution allows for dynamic scripting in

contrast to table- or graph-based DRC tools:
●
Loops
●
Branches
10 / 43 .../drc/all_layers/grid_check.lydrc
 How to improve speed?
1. Mode
Default Mode Tiled Mode Deep Mode
●
Flat polygon handling ●
Need to optimize tile ●
Preserves hierarchy in
●
Single-threaded size many cases
●
No overhead ●
Finite lookup range ●
Very fast / very slow
Use for small layouts Output is flat Typically less memory
FSiC 2022 - Matthias Köfferlein

● ● ●

●
No side effects ●
Multithreading enabled ●
Does not predictably
●
Scales with #CPUs scale with #CPU
●
Scales with layout area ●
Performance not
●
Predictable runtime predictable
and memory footprint ●
Mainly used for LVS
layer preparation
●
Still somewhat
experimental
ment
ve lo p
e r de
d
Un

Note that you can switch modes and tile parameters during execution!
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 How to improve speed?
2. Use low power alternatives
●
Multichannel operations: and_not, split_*
FSiC 2022 - Matthias Köfferlein

●
Use sparse layers for first operands in commutable operations
– The first operand determines the complexity
●
Avoid implicit polygon merging
– avoid huge connected regions with many holes (meshes, inverted
layers)
– raw mode avoids merging
– boolean operations do not merge – prefer those
– DRC functions will often merge inputs
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 How to improve speed?
3. More options
●
Edge-mode operations may be faster than polygon operations
FSiC 2022 - Matthias Köfferlein

renders same result, except

shielding is not available
●
Disable shielding
([Link] )

●
Disable figure breaking in deep mode
([Link] )

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 How to improve speed?
4. Feed me samples
Debugging performance issues is a tedious and time consuming
process
●
Needs full access to a representative test case with layout,
script and other inputs
FSiC 2022 - Matthias Köfferlein

●
Synthetic test cases usually highlight the wrong problem
Sadly, real-world testcases usually cannot be shared
But:
●
It is often possible - with some effort - to break down a testcase
into a reduced one which reproduces the problem while not
disclosing secrets
ur b os s !
Talk to yo
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 How to improve speed?
5. Core code optimization (example)
200x200
array
FSiC 2022 - Matthias Köfferlein

space
violation

touching cells overlapping cells separated cells

Space check touching overlapping separated

tiled (10x10) 6.10 s 6.17 s 1.02 s

1 thread
deep ~1300 s (0.27) ~1300 s (0.27) 0.04 s
131 s 127 s
ry
Prelimina 0.200 s *) 0.210 s *)

*) without pre-merging: error marker duplication happens

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.../drc/slow_and_fast_deep_mode
 How to reduce memory?
1. Release shape memory (“forget”)
Every DRC statement is a function call, every layer is a variable
holding the layer’s shapes (directly or indirectly)
DRC execution is single-pass
A layer may still be used: it cannot be released automatically
FSiC 2022 - Matthias Köfferlein

Use “forget” if you do not need the layer anymore:

releases memory for these layers:

after “forget” you can no longer use them

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 How to reduce memory?
2. Mode
Default Mode Tiled Mode Deep Mode
●
Flat polygon handling ●
Low internal memory ●
Temporary memory
●
Worst option in terms usage required for analysis
of memory ●
Results are still flat ●
Results are often
Use only for small Flat output is not hierarchical, hence
FSiC 2022 - Matthias Köfferlein

● ●

layouts memory efficient memory efficient

●
Good for DRC - result ●
See notes on next
is supposed to be slide ...
empty :)
●
Bad for computing
dense intermediate
layers or manipulating
layouts

Note that you can switch modes and tile parameters during execution!
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 How to reduce memory?
Deep mode pitfalls
Shape propagation / flatten may occur if
●
One of the operands of an operation is flat (specifically “big rectangle NOT
something”)
●
Hierarchical meshes get merged - e.g. as input to “size” and DRC checks
FSiC 2022 - Matthias Köfferlein

●
Cell variant formation in required (e.g. grid check with off-grid instances)

Merging Shape propagation Cell variants

●
Needed for operations ●
Deep mode considers ●
Cells are duplicated and
that need merged shape interactions instances are reassigned
polygons (e.g. size) ●
Computation happens on ●
They are needed for
●
Happens internally the hierarchy level where operations which are not
●
Huge polygons may these interactions happen translation or rotation invariant
appear up in the first ●
E.g. snapping, scaling,
hierarchy ●
Beware of flat inputs – transformations
●
Raw mode disables operations will happen on ●
Magnified instances usually
merging top level in flat mode create variants
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 How to reduce memory?
Deep mode pitfalls: merging
FSiC 2022 - Matthias Köfferlein

Output (white):
hierarchical processing
single polygon inside subcell

Output (white):
huge merged polygon
(160k points) - flat

input (1/0)
19 / 43 200x200 stitched array of non-overlapping cells
 Why doesn’t KLayout read
Calibre decks?
SVRF (Calibre’s verification language) is
protected IP, so it cannot be implemented in
FOSS tools
FSiC 2022 - Matthias Köfferlein

The recommended approach is to read DRC

decks from a common source (e.g. tables,
Python code ..) and to supply generators for
different target tools

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 What is “Universal DRC”?
“Universal DRC” is a feature of KLayout >= 0.27
Feature:
output = [Link](function)
Think of “drc” as a “for each” loop on every cluster of “layer” and other inputs.
“function” is a combined expression delivering shapes which are collected in
“output”.
FSiC 2022 - Matthias Köfferlein

These combined expressions can involve inputs from different sources:

●
“primary”: the shapes from “input”
●
“foreign”: shapes from “input”, outside current cluster
●
“secondary”: shapes from other layers
“function” is a combination of atomic functions, methods and operators.
Application:
●
Extended DRC checks (combined checks, more relations than “less”)
●
Combined filters
●
New applications using “foreign”
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 What is “Universal DRC”?
Example: “critical area”
A
“critical area”
A defect hitting this area with its
center will short wires A and B
CA is a metric for defect sensitivity.
B
FSiC 2022 - Matthias Köfferlein

Defect with given size

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.../drc/universal_drc/[Link]
 How to implement width-
dependent space checks?
0
1
2
FSiC 2022 - Matthias Köfferlein

(0)

(1)+(2)
(2)
“first_edges” will select the counter-
clockwise edges suitable for “space”

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../scripts/drc/.../drc/width_dependent_space
 Where is “connected”?
A: It is not there (yet)
In other systems this feature allows checking
for space only if the shapes are (not) connected
Implementation requirements:
FSiC 2022 - Matthias Köfferlein

●
Needs a net annotation on the shapes
●
Easy in flat, difficult in tiled or deep mode
●
Proposal: employ the hierarchical net
representation which “l2n” database provides
– i.e. introduce space checks between nets
DO
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 How to do a radius check?
No built-in function there, but this idea:
1µ m
s > =
sR adiu
ec k
Ch
FSiC 2022 - Matthias Köfferlein

r=1 r = 1.5 r = 0.5 r=0

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.../drc/radius_check
 How to properly do an
enclosure check?
There is an enclosing/enclosed feature, but it does not
recognize shapes being outside the enclosing area!
Correct implementation: twofold check
FSiC 2022 - Matthias Köfferlein

sees (1)
sees (2)

(1) (2)

2
1
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.../drc/enclosure_check
 FSiC 2022 - Matthias Köfferlein

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LVS
 How to ignore device parameters?

5 □ = 0.5k

.SUBCKT resistor
R1 A B 1k
.ENDS
100 Ω/□
FSiC 2022 - Matthias Köfferlein

To force a match use “tolerance” or “ignore_parameter”

[Link]
100% tolerance =
“match always”

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.../lvs/ignore_parameters/[Link]
 How to enable device parameters?
5 □ = 1k
W=2

.SUBCKT resistor
R1 A B 1k W=1u
.ENDS
200 Ω/□
FSiC 2022 - Matthias Köfferlein

“W” is a secondary parameter and not compared by default.

To force a mismatch use “enable_parameter”
[Link]

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.../lvs/additional_parameters/[Link]
 How to write device subckts?
Spice output can be customized with a “Spice Writer Delegate”
●
Delegate pattern: implement some aspects externally
●
Delegates are used to redirect the flow to custom code
FSiC 2022 - Matthias Köfferlein

Called initially to
write some header

Called to write a
device

●
Full code: [Link]
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 How to read device subckts?
Spice input can be customized with a “Spice Reader
Delegate”
●
Similar to Spice Writer Delegate, but for reading and
somewhat more complex
●
Several levels of integration for tailoring the parser process
FSiC 2022 - Matthias Köfferlein

– Atomic: translate net names

– Spice card: parse card strings into element data
– Devices: build devices from parsed element data
– Subcircuits: filter model subcircuits
●
Full code:
[Link]

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 How to make new devices?
KLayout offers some standard devices, but they may not be sufficient

Example: MOS capacitor in n well

●
Similar to PMOS transistor, but S/D implant is n+
FSiC 2022 - Matthias Köfferlein

●
Specified with W, L instead of area
●
Standard Spice C element may not applicable
●
Multiplier N instead of plain cap value adding for parallel devices

Requirements:
●
Special extractor delivering W, L
●
Spice reader / writer for using subcircuit models
●
Special device combination rules
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 How to make new devices?
P D B
P
Param: W,L,N
poly
n+ D
GOX

n well
FSiC 2022 - Matthias Köfferlein

p substrate B
n-well MOS cap device Model
P

diff

n+ X1 G D B MOSCAPN
D nwell + W=10u L=20u N=2

poly Spice

B
33 / 43 Layout
 How to make new devices?
Full code is here: .../lvs/custom_device

Basic components:
●
“Device Extractor” ([Link])
– A subclass of RBA::GenericDeviceExtractor
– Initializes the “device class”
FSiC 2022 - Matthias Köfferlein

– Defines the geometry collector

– Generates the devices from geometry
●
“Combiner” ([Link])
– A subclass of RBA::GenericDeviceCombiner
– Implements parallel / serial combination of devices
●
Spice reader and writer delegates ([Link])
– Subclasses of RBA::NetlistSpiceReaderDelegate and RBA::NetlistSpiceWriterDelegate
– Specify how devices are read or written from or to Spice files
●
LVS script ([Link])
– The standard LVS script making use of the new devices
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 How to make new devices?
Device Extractor: creating the device class
The “device class” is the device “data sheet” – it specifies terminals,
parameters, model name etc.
You can create one from scratch or use of one of the predefined classes
for a basis (enables standard Spice elements like “R”, “C” or “M”)
FSiC 2022 - Matthias Köfferlein

name, description, default value, is_primary, si_scaling

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 How to make new devices?
Device Extractor: setting up ..
Reimplement “setup” to register the device class and define the extraction
layers
FSiC 2022 - Matthias Köfferlein

input layers
#0
#1
#2
#3
#4
#5

output layers (terminal pins are placed there)

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 How to make new devices?
Device Extractor: geometry collection
The device extractor collects shapes for devices along a cluster definition
based on a “connectivity” scheme. This is not electrical, but logical.
Connected shapes are clustered together.
FSiC 2022 - Matthias Köfferlein

see layer ids mentioned before

include a self-connection to
join shapes into connected
regions

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 How to make new devices?
Device Extractor: turning geometry into device
gets called for each cluster
(potentially multiple devices)
p

d
FSiC 2022 - Matthias Köfferlein

a
a_polygon

places shapes for terminals

NOTE: terminal, layer by index (0, 1, 2 ...)
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 How to make new devices?
Device Combiner
The device combiner checks if devices can be combined, computes the
resulting parameters and rewires the devices so that one is the combined
one and the other becomes disconnected.

here we only combine devices

FSiC 2022 - Matthias Köfferlein

which are geometrically identical

Adds “N” multipliers

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 How to make new devices?
Device Combiner
The device combiner checks if devices can be combined, computes the
resulting parameters and rewires the devices so that one is the combined
one and the other becomes disconnected.

here we only combine devices

FSiC 2022 - Matthias Köfferlein

which are geometrically identical

Adds “N” multipliers

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 How to make new devices?
Demo layout and schematic: .../lvs/custom_device
Layers taken from Sky130

M1 X1 C1 C2
X2
FSiC 2022 - Matthias Köfferlein

X1 X2
W=24 W=14
L=17.2 L=17.2
N=2 N=2

mos_cap.gds

DOWN NPUMP
M1
W=50
L=0.4

VSS
[Link]
41 / 43 [Link]
 Looking for more?

Your community:
[Link]
FSiC 2022 - Matthias Köfferlein

Your documentation source:

[Link]

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 Thank you for listening!
FSiC 2022 - Matthias Köfferlein

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