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Verify Scan Path Setup

The document outlines the setup for a chip verification scan path using STIL format, detailing the signals, timing, and patterns involved in the process. It includes annotations for various test cycles and signal values, specifying input and output conditions for each cycle. The configuration is intended for use with the Tessent Shell software, providing a structured approach to testing integrated circuits.

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shan timo
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32 views6 pages

Verify Scan Path Setup

The document outlines the setup for a chip verification scan path using STIL format, detailing the signals, timing, and patterns involved in the process. It includes annotations for various test cycles and signal values, specifying input and output conditions for each cycle. The configuration is intended for use with the Tessent Shell software, providing a structured approach to testing integrated circuits.

Uploaded by

shan timo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

STIL 1.

0;

Header {
Title "chip_verify_scan_path_setup_stil" ;
Date "Wed Jun 17 17:05:42 2020" ;
Source "Tessent Shell 2020.3-snapshot_2020.06.17_03.00" ;
History {
Ann {* Begin_Verify_Section *}
Ann {* format = STIL *}
Ann {* serial_flag = OFF *}
Ann {* test_set_type = IJTAG_TEST *}
Ann {* pad_value = X *}
Ann {* one_setup = ON *}
Ann {* no_initialization = OFF *}
Ann {* End_Verify_Section *}
}
}

Signals {
"tck" In; "tdi" In; "tms" In; "trst" In;
"tdo" Out;
}

SignalGroups {
_pi_ = '"tck" + "tdi" + "tms" + "trst"';
_po_ = '"tdo"';
input_time_gen_0 = '"tdi" + "tms" + "trst"';
input_time_gen_1 = '"tck"';
}

Timing RETARGET_timing {
WaveformTable tset_gen_tp1 {
Period '100ns' ;
Waveforms {
input_time_gen_0 { 01NZ { '0ns' D/U/N/Z; }}
input_time_gen_1 { 01 { '0ns' D; '25ns' D/U; '75ns' D;}}
_po_ { LHXT { '0ns' X; '24ns' l/h/X/t; '25ns' X;}}
}
}
}
PatternBurst ijtagpats {
PatList { ijtag_test; }
}

PatternExec {
Timing RETARGET_timing;
PatternBurst ijtagpats;
}

Pattern ijtag_test {
//Pattern:0 Vector:0 TesterCycle:0
Ann {* Pattern:0 Vector:0 TesterCycle:0 *}
W tset_gen_tp1;
V {
_pi_=0N01;
_po_=X;
}
//Pattern:0 Vector:1 TesterCycle:1
Ann {* Pattern:0 Vector:1 TesterCycle:1 *}
Ann {* TESSENT_PRAGMA icl_checksum 4f48566a77aaabad499fa6e8812fc6db_1 *}
//Pattern:0 Vector:1 TesterCycle:1
Ann {* Pattern:0 Vector:1 TesterCycle:1 *}
Ann {* TESSENT_PRAGMA pattern_set tmp_ijtag_setup_pat_set *}
Ann {* Pattern_set tmp_ijtag_setup_pat_set *}
"pattern 0":
V {
_pi_=1000;
_po_=X;
}
//Pattern:0 Vector:2 TesterCycle:2
Ann {* Pattern:0 Vector:2 TesterCycle:2 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:3 TesterCycle:3
Ann {* Pattern:0 Vector:3 TesterCycle:3 *}
Ann {* + Justify the scan path *}
V {
_pi_=1011;
_po_=X;
}
//Pattern:0 Vector:4 TesterCycle:4
Ann {* Pattern:0 Vector:4 TesterCycle:4 *}
V {
_pi_=1011;
_po_=X;
}
//Pattern:0 Vector:5 TesterCycle:5
Ann {* Pattern:0 Vector:5 TesterCycle:5 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:6 TesterCycle:6
Ann {* Pattern:0 Vector:6 TesterCycle:6 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:7 TesterCycle:7
Ann {* Pattern:0 Vector:7 TesterCycle:7 *}
Ann {* TESSENT_PRAGMA annotation tap_I1.IR -type read -var_bits {2:0} -var_length
3 -pin tdo -relative_cycles {2:0} *}
V {
_pi_=1101;
_po_=H;
}
//Pattern:0 Vector:8 TesterCycle:8
Ann {* Pattern:0 Vector:8 TesterCycle:8 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = tap_I1.IR[0]
*}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:9 TesterCycle:9
Ann {* Pattern:0 Vector:9 TesterCycle:9 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = tap_I1.IR[1]
*}
V {
_pi_=1011;
_po_=L;
}
//Pattern:0 Vector:10 TesterCycle:10
Ann {* Pattern:0 Vector:10 TesterCycle:10 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = tap_I1.IR[2]
*}
V {
_pi_=1011;
_po_=X;
}
//Pattern:0 Vector:11 TesterCycle:11
Ann {* Pattern:0 Vector:11 TesterCycle:11 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:12 TesterCycle:12
Ann {* Pattern:0 Vector:12 TesterCycle:12 *}
V {
_pi_=1011;
_po_=X;
}
//Pattern:0 Vector:13 TesterCycle:13
Ann {* Pattern:0 Vector:13 TesterCycle:13 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:14 TesterCycle:14
Ann {* Pattern:0 Vector:14 TesterCycle:14 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:15 TesterCycle:15
Ann {* Pattern:0 Vector:15 TesterCycle:15 *}
Ann {* TESSENT_PRAGMA annotation sib_I4.SIB -type read -var_bits {0} -pin tdo -
relative_cycles {0} *}
Ann {* TESSENT_PRAGMA annotation sib_I3.SIB -type read -var_bits {0} -pin tdo -
relative_cycles {1} *}
Ann {* TESSENT_PRAGMA annotation sib_I2.SIB -type read -var_bits {0} -pin tdo -
relative_cycles {2} *}
Ann {* TESSENT_PRAGMA annotation sib_I1.SIB -type read -var_bits {0} -pin tdo -
relative_cycles {3} *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:16 TesterCycle:16
Ann {* Pattern:0 Vector:16 TesterCycle:16 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = sib_I4.SIB *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:17 TesterCycle:17
Ann {* Pattern:0 Vector:17 TesterCycle:17 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = sib_I3.SIB *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:18 TesterCycle:18
Ann {* Pattern:0 Vector:18 TesterCycle:18 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = sib_I2.SIB *}
V {
_pi_=1111;
_po_=L;
}
//Pattern:0 Vector:19 TesterCycle:19
Ann {* Pattern:0 Vector:19 TesterCycle:19 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = sib_I1.SIB *}
V {
_pi_=1011;
_po_=X;
}
//Pattern:0 Vector:20 TesterCycle:20
Ann {* Pattern:0 Vector:20 TesterCycle:20 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:21 TesterCycle:21
Ann {* Pattern:0 Vector:21 TesterCycle:21 *}
V {
_pi_=1011;
_po_=X;
}
//Pattern:0 Vector:22 TesterCycle:22
Ann {* Pattern:0 Vector:22 TesterCycle:22 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:23 TesterCycle:23
Ann {* Pattern:0 Vector:23 TesterCycle:23 *}
V {
_pi_=1001;
_po_=X;
}
//Pattern:0 Vector:24 TesterCycle:24
Ann {* Pattern:0 Vector:24 TesterCycle:24 *}
Ann {* TESSENT_PRAGMA annotation sib_I4.SIB(1) -type read -var_bits {0} -pin tdo
-relative_cycles {0} *}
Ann {* TESSENT_PRAGMA annotation sib_I3.SIB(1) -type read -var_bits {0} -pin tdo
-relative_cycles {1} *}
Ann {* TESSENT_PRAGMA annotation sib_I2.SIB(1) -type read -var_bits {0} -pin tdo
-relative_cycles {2} *}
Ann {* TESSENT_PRAGMA annotation sib_I1.SIB(1) -type read -var_bits {0} -pin tdo
-relative_cycles {3} *}
Ann {* TESSENT_PRAGMA annotation block1_I2.sib2.SIB -type read -var_bits {0} -pin
tdo -relative_cycles {4} *}
Ann {* TESSENT_PRAGMA annotation block1_I2.sib1.SIB -type read -var_bits {0} -pin
tdo -relative_cycles {5} *}
Ann {* TESSENT_PRAGMA annotation block1_I1.sib2.SIB -type read -var_bits {0} -pin
tdo -relative_cycles {6} *}
Ann {* TESSENT_PRAGMA annotation block1_I1.sib1.SIB -type read -var_bits {0} -pin
tdo -relative_cycles {7} *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:25 TesterCycle:25
Ann {* Pattern:0 Vector:25 TesterCycle:25 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = sib_I4.SIB *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:26 TesterCycle:26
Ann {* Pattern:0 Vector:26 TesterCycle:26 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = sib_I3.SIB *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:27 TesterCycle:27
Ann {* Pattern:0 Vector:27 TesterCycle:27 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = sib_I2.SIB *}
V {
_pi_=1101;
_po_=L;
}
//Pattern:0 Vector:28 TesterCycle:28
Ann {* Pattern:0 Vector:28 TesterCycle:28 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register = sib_I1.SIB *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:29 TesterCycle:29
Ann {* Pattern:0 Vector:29 TesterCycle:29 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register =
block1_I2.sib2.SIB *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:30 TesterCycle:30
Ann {* Pattern:0 Vector:30 TesterCycle:30 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register =
block1_I2.sib1.SIB *}
V {
_pi_=1001;
_po_=L;
}
//Pattern:0 Vector:31 TesterCycle:31
Ann {* Pattern:0 Vector:31 TesterCycle:31 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register =
block1_I1.sib2.SIB *}
V {
_pi_=1111;
_po_=L;
}
//Pattern:0 Vector:32 TesterCycle:32
Ann {* Pattern:0 Vector:32 TesterCycle:32 *}
Ann {* TESSENT_MARKER:Previous Compare : pin tdo , ICL register =
block1_I1.sib1.SIB *}
V {
_pi_=1011;
_po_=X;
}
//Pattern:0 Vector:33 TesterCycle:33
Ann {* Pattern:0 Vector:33 TesterCycle:33 *}
V {
_pi_=1001;
_po_=X;
}
}

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