UNIT – 1

INTRODUCTION TO VERILOG:
SYLLABUS:
INTRODUCTION TO VERILOG:

Verilog as HDL, Levels of design Description, Concurrency, Simulation and Synthesis,

Functional Verification, System Tasks, Programming Language Interface (PLI), Module,
Simulation and Synthesis Tools, Test Benches.
LANGUAGE CONSTRUCTS AND CONVENTIONS:
Introduction, Keywords, Identifiers, White Space Characters, Comments, Numbers, Strings,
Logic Values, Strengths, Data Types, Scalars and Vectors, Parameters, Operators.

INTRODUCTION TO VERILOG:

VERILOG AS AN HDL
Verilog aimed at providing a functionally tested and a verified design description for the
target FPGA or ASIC. The language has a dual function – one fulfilling the need for a design
description and the other fulfilling the need for verifying the design for functionality and
timing constraints like propagation delay, critical path delay, slack, setup, and hold times

LEVELS OF DESIGN DESCRIPTION

1. Circuit Level:
At the circuit level, a switch is the basic element with which digital circuits are built.
Switches can be combined to form inverters and other gates at the next higher level of
abstraction. Verilog has the basic MOS switches built into its constructs, which can be used
to build basic circuits like inverters, basic logic gates, simple 1-bit dynamic and static
memories

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2. Gate Level :-
At the next higher level of abstraction, design is carried out in terms of basic gates. All the
basic gates are available as ready modules called ―Primitives.‖ Each such primitive is
defined in terms of its inputs and outputs. Primitives can be incorporated into design
descriptions directly.

3. Data Flow :-
Data flow is the next higher level of abstraction. All possible operations on signals and
variables are represented here in terms of assignments. All logic and algebraic operations are
accommodated. The assignments define the continuous functioning of the concerned block.
At the data flow level, signals are assigned through the data manipulating equations. All such
assignments are concurrent in nature. The design descriptions are more compact than those at
the gate level.

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4. Behavioral Level :-

Behavioral level constitutes the highest level of design description; it is essentially at the
system level itself. With the assignment possibilities, looping constructs and conditional
branching possible, the design description essentially looks like a ―C‖ program.

CONCURRENCY
In an electronic circuit all the units are to be active and functioning concurrently. The
voltages and currents in the different elements in the circuit can change simultaneously. In
turn the logic levels too can change. Simulation of such a circuit in an HDL calls for
concurrency of operation. Verilog simulators are built to simulate concurrency.

SIMULATION AND SYNTHESIS

The design that is specified and entered as described is simulated for functionality and fully
debugged. Translation of the debugged design into the corresponding hardware circuit (using
an FPGA or an ASIC) is called ―synthesis‖. The circuits realized from them are essentially
direct translations of functions into circuit elements.

FUNCTIONAL VERIFICATION
Testing is an essential ingredient of the VLSI design process as with any hardware circuit. It
has two dimensions to it – functional tests and timing tests. Testing or functional verification
is carried out by setting up a ―test bench‖ for the design. The test bench will have the design
instantiated in it; it will generate necessary test signals and apply them to the instantiated
design.

Test Inputs for Test Benches:

Any digital system has to carry out a number of activities in a defined manner. Once a

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proper design is done, it has to be tested for all its functional aspects. Test inputs can be
purely combinational, periodic, numeric sequences, random inputs, conditional inputs, or
combinations of these. As the circuit design proceeds, one develops smaller blocks and
groups them together to form bigger circuit units. The process is repeated until the whole
system is fully built up. Every stage calls for tests to see whether the subsystem at that layer
behaves in the manner expected.
Such testing calls for two types of observations:
Study of signals within a small unit when test inputs are given to the whole unit. Isolation of
a small element and doing local test to facilitate debugging.

Constructs for Modeling Timing Delays:

Any basic gate has propagation delays and transmission delays associated with it. As
the elements in the circuit increase in number, the type and variety of such delays increase
rapidly; often one reaches a stage where the expected function is not realized thanks to an
unduly large time delay.
Verilog has constructs for modeling the following delays:
Gate delay Net delay Path delay
Pin-to-pin delay
A design can be tested for setup time, hold time, clock-width time specifications, etc. Such
constructs or delay models are akin to the finite delay time, rise time, fall time, path or
propagation delays, etc., associated with real digital circuits or systems. The use of such
constructs in the design helps simulate realistic conditions in a digital circuit.

SYSTEM TASKS

A number of system tasks are available in Verilog. Though used in a design

description, they are not part of it. Some tasks facilitate control and flow of the testing
process. Reading data from specified files into a module and writing back into files are also
possible through other tasks. Timescale can be changed prior to simulation with the help of
specific tasks for the purpose.
A set of system functions add to the flexibility of test benches: They are of three categories:
Functions that keep track of the progress of simulation time

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Functions to convert data or values of variables from one format to another Functions to
generate random numbers with specific distributions

PROGRAMMING LANGUAGE INTERFACE (PLI)

PLI provides an active interface to a compiled Verilog module. The interface adds a
new dimension to working with Verilog routines from a C platform.
The key functions of the interface are as follows:
One can read data from a file and pass it to a Verilog module as input. Such data can be test
vectors or other input data to the module. Similarly, variables in Verilog modules can be
accessed and their values written to output devices.
Delay values, logic values, etc., within a module can be accessed and altered. Blocks written
in C language can be linked to Verilog modules.

MODULE

Any Verilog program begins with a keyword – called a ―module.‖ A module is the
name given to any system considering it as a black box with input and output terminals The
terminals of the module are referred to as ‗ports‘.
The ports attached to a module can be of three types:

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input ports through which one gets entry into the module; they signify the input signal
terminals of the module.
output ports through which one exits the module; these signify the output signal terminals of
the module. inout ports: These represent ports through which one gets entry into the module
or exits the module; These are terminals through which signals are input to the module
sometimes; at some other times signals are output from the module through these.

Verilog takes the active statements appearing between the ―module‖ statement and the
―endmodule‖ statement.0

SIMULATION AND SYNTHESIS TOOLS

A variety of Software tools related to VLSI design is available. We discuss here two of
them directly relevant to us – Modelsim and Leonardo Spectrum of Mentor Graphics.
Modelsim has been used to simulate the designs. Simulation results presented for the variety
of examples discussed in the book have been obtained using it. Leonardo Spectrum has been
used to obtain the synthesized circuits presented. We would like to draw the attention of the
readers to the following in this context:

Only the essential aspects of the tools are presented – those essential for the progress of the
book. For more details of the tools and the variety of facilities they offer, one can refer to the
respective user manuals and the Help menus.
Tools from other sources are similar in essentials. Any of them can be used.
Modelsim SE 5.5 Synthesis

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TEST BENCHES

Any digital circuit that has been designed and wired goes through a testing process
before being declared as ready for use. Testing involves studying circuit behavior under
simulated conditions for the following:

Check and ensure that all functions are carried out as desired. It is the test for the static
behavior of the circuit. A set of logic input values are applied at selected points and the logic
values at another set of points observed.
Check and ensure that all the functional sequences are carried out as desired. It is one of the
tests for the dynamic behavior of the circuit. It may call for the generation of specific input
sequences with respect to time, applying them to the circuit and observing selected outputs.
Check for the timing behavior: One tests for the propagation and other types of delays here.
A variety of tests may have to be carried out. It may involve observation of variations in the
signals at selected points, measuring the time delay between specified events, measuring
pulse widths, and so on.

LANGUAGE CONSTRUCTS AND CONVENTIONS:

INTRODUCTION
The constructs and conventions make up a software language. A clear understanding and
familiarity of these is essential for the mastery of the language. Verilog has its own constructs
and conventions [IEEE, Sutherland]. In many respects they resemble those of C language
[Gottfried]. We discuss the constructs and conventions essential to the progress of the book.

Case Sensitivity

Verilog is a case-sensitive language like C. Thus sense, Sense, SENSE, sENse,… etc.,
are all treated as different entities / quantities in Verilog.

KEYWORDS

The keywords define the language constructs. A keyword signifies an activity to be

carried out, initiated, or terminated. As such, a programmer cannot use a keyword for any
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purpose other than that it is intended for. All keywords in Verilog are in small letters and
require to be used as such (since Verilog is a casesensitive language). All keywords appear in
the text in New Courier Bold-type letters.

Examples
module signifies the beginning of a module definition. endmodule signifies the end of a
module definition. begin signifies the beginning of a block of statements.

end signifies the end of a block of statements.

if signifies a conditional activity to be checked
while signifies a conditional activity to be carried out.

IDENTIFIERS

Any program requires blocks of statements, signals, etc., to be identified with an

attached nametag. Such nametags are identifiers. It is good practice for us to use identifiers,
closely related to the significance of variable, signal, block, etc., concerned. This eases
understanding and debugging of any program.

e.g., clock, enable, gate_1, . . .

There are some restrictions in assigning identifier names. All characters of the alphabet or an
underscore can be used as the first character. Subsequent characters can be of alphanumeric
type, or the underscore (_), or the dollar ($) sign – for example

name, _name. Name, name1, name_$, . . . all these are allowed as identifiers
name aa not allowed as an identifier because of the blank ( ―name‖ and ―aa‖ are
interpreted as twodifferent identifiers)
$name not allowed as an identifier because of the presence of ―$‖ as the first character.
1_name not allowed as an identifier, since the numeral ―1‖ is the first character @name not
allowed as an identifier because of the presence of the character ―@‖.
A+b not allowed as an identifier because of the presence of the character ―+‖
.

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WHITE SPACE CHARACTERS

Blanks (\b), tabs (\t), newlines (\n), and form feed form the white space characters in
Verilog. In any design description the white space characters are included to improve
readability. Functionally, they separate legal tokens. They are introduced between keywords,
keyword and an identifier, between two identifiers, between identifiers and operator symbols,
and so on. White space characters have significance only when they appear inside strings.

COMMENTS

It is a healthy practice to comment a design description liberally – as with any other

program. Comments are incorporated in two ways. A single line comment begins with
―//‖ and ends with a new line – for example

module d_ff (Q, dp, clk); //This is the design description of a D flip-flop.
//Here Q is the output.
// dp is the input and clk is the clock.

One can incorporate multiline comments also without resorting to ―//‖ at every line. For such
multiline comments ―/*‖ signifies the beginning of a comment and ―*/‖ its end. All lines
appearing between these two symbol combinations are together treated as a single block
comment – for example
module d_ff (Q, dp, clk);

/* This module forms the design description of a d_flip_flop wherein Q is the output of the
flip-flop ,
dp is the data input and clk the clock input*/

NUMBERS

Frequently numbers need to be specified in a design description. Logic status of signal

lines, buses, delay values, and numbers to be loaded in registers are examples. The numbers
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 can be of integer type or real type.

1. Integer Numbers
2. Real Numbers

STRINGS

A string is a sequence of characters enclosed within double quotes. A string must be

contained on a single line; that is, it cannot be carried over to two lines with a carriage return.
Special characters are specified by preceding them with the ―\‖ character. Verilog treats a
string as a sequence of ASCII characters – for example,

reg [8*18:1] string_value; // Declare a variable that is 18 bytes wide

initial
string_value = "Hello Verilog World"; // String can be stored
// in variable

When a string of ASCII characters as above is an operand in an expression, it is treated as a

binary number. This binary number is formed by replacing each ASCII character by 8 bits – a
0 bit followed by the 7-bit ASCII equivalent – and treating the resulting binary sequence as a
single binary number.

Special characters serve a special purpose in displaying strings, such as newline, tabs, and
displaying argument values. Special characters can be displayed in strings only when they are
preceded by escape characters, as shown in

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Special Characters:

LOGIC VALUES

Signal lines, logic values appearing on signal lines, etc., can normally take two logic
levels:

Value Level Condition in Hardware Circuits

0 Logic zero, false condition

1 Logic one, true condition
x Unknown logic value
z High impedance, floating state

STRENGTHS

The logic levels are also associated with strengths. In many digital circuits, multiple
assignments are often combined to reduce silicon area or to reduce pinouts. To facilitate this,
one can assign strengths to logic levels. Verilog has eight strength levels – four of these are of
the driving type, three are of capacitive type and one of the hi-Z type.
When a signal line is driven simultaneously from two sources of different strength levels, the

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 stronger of the two prevails. A few illustrative examples are considered here.

 If a signal line a is driven by two sources – b at 1 level with strength strong1 and c at level
0 with strength ―pull0‖– a will take the value 1.

 If a signal line a is driven by two sources – b at 1 level with strength ―pull1‖ and c at
level 0 with strength ―strong0,‖ a will take the value 0.

 If a signal line a is driven by two sources – b at 1 level with strength ―strong1‖ and c at
level 0 with strength ―strong0,‖ a will take the value x (indeterminate).

 If a signal line a is driven by two sources – b at 1 level with strength ―weak1‖ and c at
level 0 with strength ―large0,‖ a will take the value 0.

 (Note that large signifies a capacitive drive on a tri-stated line whereas weak signifies a
gate / assigned output drive with a high source impedance; despite this, due to the higher
strength level, the large signal prevails.)

DATA TYPE
The data handled in Verilog fall into two categories:
1. Net data type
2. Variable data type

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The two types differ in the way they are used as well as with regard to their respective
hardware structures. Data type of each variable or signal has to be declared prior to its use.
The same is valid within the concerned block or module.

Nets

A net signifies a connection from one circuit unit to another. Such a net carries the
value of the signal it is connected to and transmits to the circuit blocks connected to it. If the
driving end of a net is left floating, the net goes to the high impedance state. A net can be
specified in different ways.

wire: It represents a simple wire doing an interconnection. Only one output is connected to a
wire and is driven by that.
tri: It represents a simple signal line as a wire. Unlike the wire, a tri can be driven by more
than one signal outputs.
Functionally, wire and tri are identical. Distinct nomenclatures are provided for the
convenience of assigning roles.

Variable Data Type

A variable is an abstraction for a storage device. It can be declared through the

keyword reg and stores the value of a logic level: 0, 1, x, or z. A net or wire connected to a
reg takes on the value stored in the reg and can be used as input to other circuit elements. But
the output of a circuit cannot be connected to a reg. The value stored in a reg is changed
through a fresh assignment in the program. time, integer, real, and realtime are the other
variable types of data; these are dealt with later.

SCALARS AND VECTORS

Entities representing single bits — whether the bit is stored, changed, or transferred —
are called
―scalars.‖ Often multiple lines carry signals in a cluster – like data bus, address bus, and so on.

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Similarly, a group of regs stores a value, which may be assigned, changed, and handled
together. The collection here is treated as a ―vector.‖ Below figure illustrates the difference
between a scalar and a vector. wr and rd are two scalar nets connecting two circuit blocks
circuit1 and circuit2. b is a 4-bit-wide vector net connecting the same two blocks. b[0], b[1],
b[2], and b[3] are the individual bits of vector b. They are ―part vectors.‖ A vector reg or net
is declared at the outset in a Verilog program and hence treated as such. The range of a vector
is specified by a set of 2 digits (or expressions evaluating to a digit) with a colon in between
the two. The combination is enclosed within square brackets.

wire[3:0] a; /* a is a four bit vector of net type; the bits are designated as a[3], a[2], a[1]
and a[0]. */

reg[2:0] b; /* b is a three bit vector of reg type; the bits are designated as b[2], b[1] and
b[0]. */

reg[4:2] c; /* c is a three bit vector of reg type; the bits are designated as c[4], c[3] and
c[2]. */

wire[-2:2] d ; /* d is a 5 bit vector with individual bits designated as d[-2], d[-1], d[0], d[1]
and

d[2]. */

Whenever a range is not specified for a net or a reg, the same is treated as a scalar – a
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single bit quantity. In the range specification of a vector the most significant bit and the least
significant bit can be assigned specific integer values. These can also be expressions
evaluating to integer constants – positive or negative. Normally vectors – nets or regs – are
treated as unsigned quantities. They have to be specifically declared as ―signed‖ if so desired.

wire signed[4:0] num; // num is a vector in the range -16 to +15.

reg signed [3:0] num_1; // num_1 is a vector in the range -8 to +7.

Integer , Real, and Time Register Data Types:

Integer, real, and time register data types are supported in Verilog.

Integer :

An integer is a general purpose register data type used for manipulating quantities.
Integers are declared by the keyword integer. Although it is possible to use reg as a general-
purpose variable, it is more convenient to declare an integer variable for purposes such as
counting. The default width for an integer is the host-machine word size, which is
implementation-specific but is at least 32 bits. Registers declared as data type reg store values
as unsigned quantities, whereas integers store values as signed quantities.

integer counter; // general purpose variable used as a counter.

initial

counter = -1; // A negative one is stored in the counter

Real

Real number constants and real register data types are declared with the keyword real.
They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6,
which is 3 x 106 ). Real numbers cannot have a range declaration, and their default value is 0.

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When a real value is assigned to an integer, the real number is rounded off to the nearest
integer.

real delta; // Define a real variable called delta

initial
begin
delta = 4e10; // delta is assigned in scientific notation
delta = 2.13; // delta is assigned a value 2.13
end
integer i; // Define an integer i
initial
i = delta; // i gets the value 2 (rounded value of 2.13)

Time:

Verilog simulation is done with respect to simulation time. A special time register data
type is used in Verilog to store simulation time. A time variable is declared with the keyword
time. The width for time register data types is implementation-specific but is at least 64
bits.The system function $time is invoked to get the current simulation time.

time save_sim_time; // Define a time variable save_sim_time

initial
save_sim_time = $time; // Save the current simulation time

Memories

In digital simulation, one often needs to model register files, RAMs, and ROMs.
Memories are modeled in Verilog simply as a one-dimensional array of registers. Each
element of the array is known as an element or word and is addressed by a single array index.
Each word can be one or more bits. It is important to differentiate between n 1-bit registers
and one n-bit register. A particular word in memory is obtained by using the address as a
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memory array subscript.

reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit words reg

[7:0] membyte[0:1023]; // Memory membyte with 1K 8-bit
words(bytes) membyte[511] // Fetches 1 byte word whose
address is 511.

PARAMETERS

In some designs, certain parameter values are not committed at the outset.
Proportionality constants, frequency-scaling levels, number of taps in digital filters, etc., are
typical examples. There are also situations where the size of the design is left open and
decided at a later stage. Bus width, LIFO depth, and memory size are such quantities which
may be committed later. All such constants can be declared as parameters at the outset in a
Verilog module, and values can be assigned to them; for example,

parameter port_id = 5; // Defines a constant port_id

parameter cache_line_width = 256; // Constant defines width of cache line

parameter signed [15:0] WIDTH; // Fixed sign and range for parameter WIDTH

Such parameter assignments are made at compiler time. The parameter values cannot be
changed (normally) at runtime. However, a parameter that has been assigned a value in a
module definition can have its value changed at runtime – that is, when the module is used at
runtime in some other design (i.e., instantiated) or when it is tested. Such modifications are
carried out through a “defparameter” statement.
The parameter assignment done as part of parameter declaration can have the appropriate
constant on the right-hand side of the assignment statement, as was the case above. The
assignment can also have algebraic expressions on the right hand side. Such expressions can

17
involve constants and other parameters declared already; for example

Parameter word_size = 16, factor = word_size/2;

Verilog HDL local parameters (defined using keyword localparam -) are identical to
parameters except that they cannot be directly modified with the defparam statement or by
the ordered or named parameter value assignment. The localparam keyword is used to define
parameters when their values should not be changed. For example, the state encoding for a
state machine can be defined using localparam. The state encoding cannot be changed. This
provides protection against inadvertent parameter redefinition.
localparam state1 = 4'b0001,
state2 = 4'b0010,
state3 = 4'b0100,
state4 = 4'b1000;

System Tasks and Compiler Directives :

In this section, we introduce two special concepts used in Verilog:

1. system tasks

2. compiler directives.

System Tasks :

Verilog provides standard system tasks for certain routine operations. All system tasks
appear in the form $. Operations such as displaying on the screen, monitoring values of nets,
stopping, and finishing are done by system tasks. We will discuss only the most useful
system tasks. Other tasks are listed in Verilog manuals provided by your simulator vendor or
in the IEEE Standard Verilog Hardware Description Language specificaion.

Displaying information:
“$display” is the main system task for displaying values of variables or strings or

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expressions. This
Is one of the most useful tasks in Verilog.

Usage: $display(p1, p2, p3,....., pn); //p1, p2, p3,..., pn can be quoted strings or
//variables or expressions.
The format of $display is very similar to printf in C. A $display inserts a newline at
the end of the string by default. A $display without any arguments produces a
newline.

Strings can be formatted using the specifications listed in Table

String Format Specifications

Display
%d or %D Display variable in decimal
%b or %B Display variable in binary
%s or %S Display string
%h or %H Display variable in hex

%c or %C Display ASCII character

Display hierarchical name (no argument required
%m or %M
%v or %V Display strength
%o or %O Display variable in octal
%t or %T Display in current time format
%e or %E Display real number in scientific format (e.g., 3e10)
%f or %F Display real number in decimal format (e.g., 2.13)
%g or %G Display real number in scientific or decimal, whichever is
shorter

//Display the string in quotes

$display("Hello Verilog World");
-- Hello Verilog World

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 //Display value of current simulation time 230
$display($time);
-- 230

//Display value of 41-bit virtual address 1fe0000001c at time 200

reg [0:40] virtual_addr;
$display("At time %d virtual address is %h", $time, virtual_addr);
-- At time 200 virtual address is 1fe0000001c

//Display value of port_id 5 in binary

reg [4:0] port_id;
$display("ID of the port is %b", port_id);
-- ID of the port is 00101

//Display x characters
//Display value of 4-bit bus 10xx (signal contention) in binary
reg [3:0] bus;
$display("Bus value is %b", bus);
-- Bus value is 10xx

//Display the hierarchical name of instance p1 instantiated under the highest-level module
called top. No argument is required. This is a useful feature)
$display("This string is displayed from %m level of hierarchy");
-- This string is displayed from top.p1 level of hierarchy

//Display special characters, newline and %

$display("This is a \n multiline string with a %% sign");
-- This is a
-- multiline string with a % sign //Display other special characters

Monitoring information:
Verilog provides a mechanism to monitor a signal when its value changes. This facility is

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provided by the “$monitor” task.
Usage: $monitor(p1,p2,p3,....,pn);
The parameters p1, p2, ... , pn can be variables, signal names, or quoted strings.

A format similar to the $display task is used in the $monitor task. $monitor continuously
monitors the values of the variables or signals specified in the parameter list and displays all
parameters in the list whenever the value of any one variable or signal changes.Unlike
$display, $monitor needs to be invoked only once.
Only one monitoring list can be active at a time. If there is more than one $monitor statement
in your simulation, the last $monitor statement will be the active statement. The earlier
$monitor statements will be overridden.

//Monitor time and value of the signals clock and reset ,Clock toggles every 5 time units
and reset
//goes down at 10 time units
initial
begin
$monitor($time, " Value of signals clock = %b reset = %b", clock,reset);
end
Partial output of the monitor statement:
-- 0 Value of signals clock = 0 reset = 1
-- 5 Value of signals clock = 1 reset = 1
-- 10 Value of signals clock = 0 reset = 0

Stopping and finishing in a simulation :

The task $stop is provided to stop during a simulation.

Usage: $stop;

The $stop task puts the simulation in an interactive mode. The designer can then debug the
design from the interactive mode. The $stop task is used whenever the designer wants to
suspend the simulation and examine the values of signals in the design.

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 The $finish task terminates the simulation.
Usage: $finish;

Examples of $stop and $finish

// Stop at time 100 in the simulation and examine the results

// Finish the simulation at time 1000.
initial
begin
clock = 0;
reset = 1;
#100 $stop; // This will suspend the simulation at time = 100
#900 $finish; // This will terminate the simulation at time =
1000 end

Opening a file :

A file can be opened with the system task $fopen.

Usage: $fopen(" ");

Writing to files:

The system tasks $fdisplay, $fmonitor, $fwrite, and $fstrobe are used to write to
files.p Note that these tasks are similar in syntax to regular system tasks $display,
$monitor, etc., but they provide the additional capability of writing to files.

Reading files:
Systems tasks for reading files are also provided by the IEEE Standard Verilog Hardware
Description Language. These system tasks include $fgetc, $ungetc, $fgetc, $fscanf, $sscanf,
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$fread, $ftell, $fseek, $rewind, and $fflush.

Closing files:
Files can be closed with the system task $fclose.
Usage: $fclose(<file_name>);
//Closing Files
$fclose(handle1);

Strobing :
Strobing is done with the system task keyword $strobe. This task is very similar to the
$display task except for a slight difference. If many other statements are executed in the same
time unit as the $display task, the order in which the statements and the $display task are
executed is nondeterministic. If $strobe is used, it is always executed after all other
assignment statements in the same time unit have executed. Thus, $strobe provides a
synchronization mechanism to ensure that data is displayed only after all other assignment
statements, which change the data in that time step, have executed

//Strobing
always @(posedge clock)
begin
a = b;
c = d;
end
always @(posedge clock)
$strobe("Displaying a = %b, c = %b", a, c);

The values at positive edge of clock will be displayed only after statements a = b and c =
d execute. If $display was used, $display might execute before statements a = b and c =
d, thus displaying different values.

Random Number Generation:

Random number generation capabilities are required for generating a random set of
test vectors. The system task “$random” is used for generating a random number.

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Usage: $random; $random();

module Tb();
integer address;

initial
begin
repeat(5)
#1 address = $random;
end

initial
$monitor("address = %d;",address);

endmodule

RESULT:
address = 303379748;
address = -1064739199;
address = -2071669239;
address = -1309649309;
address = 112818957;

Compiler Directives :

Compiler directives are provided in Verilog. All compiler directives are defined by
using the `<keyword> construct. We deal with the two most useful compiler directives.

`define :
The `define directive is used to define text macros in Verilog . The Verilog compiler
substitutes the text of the macro wherever it encounters a `. This is similar to the #define
construct in C. The defined constants or text macros are used in the Verilog code by
preceding them with a ` (back tick).

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 //define a text macro that defines default word size Used as 'WORD_SIZE in the code
'define WORD_SIZE 32

//define an alias. A $stop will be substituted wherever 'S appears

'define S $stop;

//define a frequently used text string

'define WORD_REG reg [31:0] // you can then define a 32-bit register as
'WORD_REG reg32;

`include :
The `include directive allows you to include entire contents of a Verilog source file in
another Verilog file during compilation. This works similarly to the #include in the C
programming language. This directive is typically used to include header files, which
typically contain global or commonly used definitions
// Include the file header.v, which contains declarations in the main verilog file design.v.
'include header.v ... ... ... ...

`timescale:
Verilog HDL allows the reference time unit for modules to be specified with the
`timescale
compiler directive.

Usage: `timescale <reference_time_unit> /<time_precision>

The <reference_time_unit> specifies the unit of measurement for times and delays. The
<time_precision>specifies the precision to which the delays are rounded off during
simulation. Only 1, 10, and 100 are valid integers for specifying time unit and time precision

//Define a time scale for the module dummy1,Reference time unit is 100
//nanoseconds and precision is 1 ns

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`timescale 100 ns / 1 ns

module dummy();
st1;
st2;
st3;

OPERATORS

Verilog has a number of operators akin to the C language. These are of three types:
 Unary: the unary operator is associated with a single operand. The operator
precedes the
operand – for example, ~a.
 Binary: the binary operator is associated with two operands. The operator appears
between the two operands – for example, a&b.
 Ternary: the ternary operator is associated with three operands. The two operators
together constitute a ternary operation. The two operators separate the three
operands – for example a?b:c
// Here the operato
“ ? ” and “ : ” together define an operation.

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