4/5/2017 PLC Program to Implement 3 to 8 Line Decoder - Sanfoundry
PLC Program to Implement 3 to 8 Line Decoder
This is a PLC Program to Implement 3 to 8 Line Decoder.
Problem Description
Implement 3 to 8 line decoder in PLC using Ladder Diagram programming language.
Problem Solution
It has three inputs I0, I1 and I2 and 8 outputs Q0 to Q7.
These three inputs I0, I1 and I2 determines which output should be active.
If I0 and I1 are true and I2 is false, then Q6 will be activated and all others are not.
It does not need K-map and simplification so one step is eliminated to create Ladder Logic Diagram.
Realize the 3 to 8 line decoder using Logic Gates.
Truth Table can be written as given below.
Inputs Outputs
I2 I1 I0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Realization of 3 to 8 line decoder using Logic Gates
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4/5/2017 PLC Program to Implement 3 to 8 Line Decoder - Sanfoundry
PLC Program
Here is PLC program to Implement 3 to 8 Line Decoder, along with program explanation and run time
test cases.
List of Inputs and Outputs
I0= I:1/0 (Input)
I1= I:1/1 (Input)
I2= I:1/2 (Input)
Q0= O:2/0 (Output)
Q1= O:2/1 (Output)
Q2= O:2/2 (Output)
Q3= O:2/3 (Output)
Q4= O:2/4 (Output)
Q5= O:2/5 (Output)
Q6= O:2/6 (Output)
Q7= O:2/7 (Output)
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4/5/2017 PLC Program to Implement 3 to 8 Line Decoder - Sanfoundry
Ladder Diagram for 3 to 8 line decoder
Program Description
In all the rungs, I0 (I:1/0), I1 (I:1/1) and I2 (I:1/2) are used to determine which output from Q0 to Q7
should go ON..
Q0 to Q7 are outputs.
When I0 (I:1/0), I1 (I:1/1) and I2 (I:1/2) are low, output 0 O:2/0 will get activated.
When I:1/0 and I:1/1 are low and I:1/1 is high that is when I0 and I1 are low and I2 is high, output 1
O:2/1 will get activated.
Similarly remaining six different outputs are obtained.
In other words, according to bit pattern of I0 I:1/0, I1 I:1/1 and I2 I:1/2, outputs from Q0 to Q7 are
activated.
Runtime Test Cases
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Inputs Outputs
4/5/2017 PLC Program to Implement 3 to 8 Line Decoder - Sanfoundry
I2 I1 I0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
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