Code No: 5857AA R22
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech I Semester Examinations, March - 2023
CMOS ANALOG IC DESIGN
(VLSI System Design)
Time: 3 Hours Max. Marks: 60
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Note: This question paper contains two parts A and B. i) Part- A for 10 marks, ii) Part - B for 50
marks.
Part-A is a compulsory question which consists of ten sub-questions from all units carrying
equal marks.
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Part-B consists of ten questions (numbered from 2 to 11) carrying 10 marks each. From
each unit, there are two questions and the student should answer one of them. Hence, the
student should answer five questions from Part-B.
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PART - A
(10 Marks)
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1.a) How p-channel device is formed? [1]
b) Draw the structure of interleaved finger capacitor. [1]
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c) How to cancel feedthrough effects? [1]
d) What will happen when the gate and drain of an MOS transistor are tied together? [1]
e) Which inverter gives highest gain? [1]
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f) What is mean by single ended voltages in Differential amplifiers? [1]
g) How op amps are classified? [1]
h) Why simulating the op amp in open loop configuration is difficult? [1]
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i) Draw the symbol of op amp comparator. [1]
j) How the gain is reduced in clamped push pull comparator? [1]
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PART - B
(50 Marks)
2.a) Draw the physical structure of an p-channel transistor and define all the parameters.
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b) Explain the formation of MiM capacitor which is used for VLSI applications. [5+5]
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3.a) How n-channel MOSFET is modeled for velocity saturation? Explain with neat circuit
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diagram.
b) Draw the circuit diagram of small signal model for the MOS transistor and explain how to
derive the parameters of this model from large signal variables? [5+5]
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4.a) Explain the I-V characteristics of current sink and current source.
b) Use the cascode current-sink configuration shown in figure below, to design a current sink of
100µA and VMIN of 1V. Model parameters are VT0 = -0.7V, K = 50µA/V2, γ = 0.57,
λ = 0.05(L=1µm) V-1, 2|ϕF| = 0.8V. Assume any parameter values are required. [5+5]
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OR
5.a) What is the principle of current mirror and explain its working with neat circuit diagram.
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b) What is bandgap curvature problem? How to reduce it? [6+4]
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6.a) What are the various types of inverting CMOS amplifiers? Explain their working with neat
circuit diagrams.
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b) Derive the equation for -3dB frequency of the CMOS inverter with a current source load.
[5+5]
OR
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7.a) Explain the working of CMOS differential amplifier using a current mirror load.
b) What are the advantages of cascode amplifier over the inverting amplifiers? [6+4]
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8.a) How classical two-stage CMOS op amp broken into voltage to current and current to voltage
stages? Explain.
b) Explain the Miller compensation technique for two stage op amp. [5+5]
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9.a) Explain the method of measurement of CMRR of op amp.
b) Show that if the voltage gain of an op amp approaches infinity, the differential input becomes
a null port. Assume that the output is returned to the input by means of negative feedback.
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[5+5]
10.a) Find the propagation delay time of an open-loop comparator that has a dominant pole at
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103 rad/s, a dc gain of 104, a slew rate of 1V/µs, and a binary output voltage swing of 1V?
Assume the applied input voltage is 10mV.
b) Explain the performance of two stage open loop comparator with necessary equations.
[4+6]
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11.a) What are the various methods that are capable of driving large values capacitive load? Explain
any one method in detail.
b) How the autozeroing technique is used to improve the performance of open loop comparator?
[5+5]
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