TMP1827

SBOSA15B – SEPTEMBER 2022 – REVISED JANUARY 2025

TMP1827 2-Kbit EEPROM, With Integrated ±0.2°C Temperature Sensor, Compatible

With 1-Wire® Protocol
1 Features 3 Description
• 1-Wire® interface with multi-drop shared bus and The TMP1827 is a high-accuracy, 1-Wire® compatible
cyclic redundancy check (CRC) digital output temperature sensor with integrated 2Kb
• Bus powered with operating voltage: 1.7V to 5.5V EEPROM, SHA-256-HMAC authentication scheme
• IEC 61000-4-2 ESD for 8-kV contact discharge and a wide operating temperature range from –55°C
• Functional Safety-Capable to +150°C. The TMP1827 provides a high accuracy
– Documentation available to aid functional safety of ±0.1°C (typical)/±0.2°C (maximum) across the
system design temperature range of +10°C to +45°C. Each device
• High-accuracy digital temperature sensor comes with a factory programmed 64-bit unique
– TMP1827 identification number for addressing and NIST
• ±0.2°C (maximum) from +10°C to +45°C traceability. The TMP1827 supports both standard
• ±0.3°C (maximum) from –40°C to +105°C speed for legacy application and overdrive mode
• ±0.4°C (maximum) from –55°C to +150°C with 90-kbps data rate for low latency communication
– TMP1827N across a wide voltage range of 1.7V to 5.5V.
• ±0.9°C (maximum) from –55°C to +150°C In the simplest mode of operation, the TMP1827
• Temperature measurement current: 94µA 1-Wire® interface, with an integrated 8kV
• Shutdown current: 1.3µA IEC-61000-4-2 ESD protection on the data pin,
• 16-bit temperature resolution: 7.8125 m°C (1 LSB) requires only a single connection and a ground return
• Fast data rates of 90kbps in overdrive speed in bus powered mode, which simplifies and reduces
• Flexible user programmable short address modes cost by reducing the number of wires and external
for faster device address protection components. Additionally, there is the VDD
• SHA-256-HMAC authentication scheme power pin also available for applications that need to
– FIPS 180-4 compliant Secure Hash have a dedicated power supply.
Implementation 1-Wire® is a registered trademark of Maxim
– FIPS 198-1 compliant HMAC Implementation Integrated Products, Inc.
• 2Kb EEPROM features:
– Write operation in 64-bit block size Package Information
– Continuous read mode (1) (2) PACKAGE SIZE
PART NUMBER PACKAGE
(NOM)
– Read with write protection with 256-bit page
size TMP1827 WSON (8) 2.50mm × 2.50mm
– Authenticated write protection mode with 256- (1) For all available packages, see the orderable addendum at
bit page size the end of the data sheet.
– Programming current: 178µA (2) These package options are compatible with 1-Wire® devices.
• NIST traceable factory-programmed non erasable 1-Wire® is a registered trademark of Maxim Integrated
Products Inc.
64-bit identification number for device addressing VDD = 1.7V to 5.5V
• Four configurable open-drain digital input-output
and temperature alert RPU

2 Applications GPIO

• Factory automation and control VDD

SDQ VDD SDQ VDD
• Appliances MCU
TMP1827 TMP1827
• Medical accessories GND GND
• CPAP machines
• Battery charger ICs GND

• EV charging infrastructure VDD Powered Bus Powered

• LED lighting
• Temperature transmitters Simplified Schematic
• Cold chain

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................12
2 Applications..................................................................... 1 8.4 Device Functional Modes..........................................22
3 Description.......................................................................1 8.5 Programming............................................................ 37
4 Description (cont.)...........................................................2 8.6 Register Map.............................................................43
5 Device Comparison......................................................... 2 9 Application and Implementation.................................. 54
6 Pin Configuration and Functions...................................3 9.1 Application Information............................................. 54
7 Specifications.................................................................. 3 9.2 Typical Applications.................................................. 54
7.1 Absolute Maximum Ratings........................................ 3 9.3 Power Supply Recommendations.............................57
7.2 ESD Ratings............................................................... 3 9.4 Layout....................................................................... 57
7.3 Recommended Operating Conditions.........................4 10 Device and Documentation Support..........................59
7.4 Thermal Information....................................................4 10.1 Documentation Support.......................................... 59
7.5 Electrical Characteristics.............................................4 10.2 Receiving Notification of Documentation Updates..59
7.6 1-Wire® Interface Timing............................................ 5 10.3 Support Resources................................................. 59
7.7 Security Engine Characteristics.................................. 6 10.4 Trademarks............................................................. 59
7.8 EEPROM Characteristics............................................6 10.5 Electrostatic Discharge Caution..............................59
7.9 Timing Diagrams......................................................... 7 10.6 Glossary..................................................................59
7.10 Typical Characteristics.............................................. 9 11 Revision History.......................................................... 59
8 Detailed Description......................................................12 12 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 12 Information.................................................................... 60
8.2 Functional Block Diagram......................................... 12

4 Description (cont.)
The TMP1827 implements the SHA-256-HMAC authentication engine along with key storage, for system
authentication requirements of an end equipment. The 2Kb EEPROM on the device allows the host application
to store application specific content in block sizes of 64-bit. The memory can be write protected in page size
of 256-bits to avoid accidental data overwrite. The memory architecture enables application to optimize the bus
bandwidth when updating variables which are only few bytes while providing an optimal memory size for write
protection. The device also features mechanism for host authentication by means of authenticated memory write
operations.

5 Device Comparison
Table 5-1. Device Comparison
FEATURE TMP1826 TMP1827 TMP1827N(1)
Best Accuracy 0.2°C 0.2°C 0.9°C
Temperature Range –55°C to +150°C –55°C to +150°C –55°C to +150°C
Memory Size 2Kb 2Kb 2Kb
Memory Write protection Yes Yes Yes
Authenticated Memory Write - Yes Yes
Authentication type - SHA-256-HMAC SHA-256-HMAC
Bus speeds Standard and Overdrive Standard and Overdrive Standard and Overdrive
Drop in replacement package NGR (2.5 mm × 2.5 mm, WSON) NGR (2.5 mm × 2.5 mm, WSON) NGR (2.5 mm × 2.5 mm, WSON)
Alternate package DGK (3.0 mm × 4.9 mm, VSSOP) - -

(1) TMP1827N is an orderable option for the TMP1827. See the orderable addendum at the end of the data sheet.

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6 Pin Configuration and Functions

VDD 1 8 IO2/ALERT

SDQ 2 7 IO1
Thermal
Pad
ADDR 3 6 IO0

GND 4 5 IO3

Figure 6-1. NGR 8-Pin WSON Top View

Table 6-1. Pin Functions

PIN
Type(1) DESCRIPTION
NAME WSON
ADDR 3 I Resistor address select. If unused, TI recommends to connect pin to ground
GND 4 — Ground
IO0 6 I/O General-purpose digital open-drain IO. If unused, TI recommends to connect pin to ground
IO1 7 I/O General-purpose digital open-drain IO. If unused, TI recommends to connect pin to ground
General-purpose digital open-drain IO or configurable as temperature alert. If unused, TI
IO2/ALERT 8 I/O
recommends to connect pin to ground
IO3 5 I/O General-purpose digital open-drain IO. If unused, TI recommends to connect pin to ground
SDQ 2 I/O Serial bidirectional data. In bus power mode, the pin is used to power the internal capacitor
VDD 1 I Supply voltage in VDD powered mode. In bus powered mode, must be connected to ground

(1) I = Input; I/O = Input or Output

7 Specifications
7.1 Absolute Maximum Ratings
Over free-air temperature range unless otherwise noted(1)
MIN MAX UNIT
Supply voltage VDD 6.5 V
SDQ, Bus powered mode –0.3 6.5
I/O voltage V
SDQ, Supply powered mode –0.3 VDD + 0.3
I/O voltage IO0, IO1, IO2, IO3 –0.3 6.5 V
Input voltage ADDR –0.3 1.65 V
Operating junction temperature, TJ –55 155 °C
Storage temperature, Tstg –65 155 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins ±2000 V
Electrostatic
V(ESD) Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) All pins ±500 V
discharge
IEC 61000-4-2 Contact Discharge SDQ pin ±8000 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage VDD powered mode 1.7 5.5 V
VPUR Supply voltage on SDQ in bus powered mode (VDD = GND) 1.7 5.5 V
All IO pins in VDD powered mode (except SDQ and ADDR(1)) 0 5.5 V
VI/O
SDQ pin in VDD powered mode 0 VDD + 0.3 V
TA Operating ambient temperature(2) -55 150 °C

(1) If ADDR pin is not used, connecting to GND is recommended

(2) In bus powered mode, overdrive speed supports the maximum operating temperature up to 150°C, while standard speed supports up
to 105°C for full VPUR range and up to 125°C for VPUR > 2.5V (See Figure 7-17)

7.4 Thermal Information

TMP1827
THERMAL METRIC(1) NGR (WSON) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 66.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 55.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 20.2 °C/W
RθJB Junction-to-board thermal resistance 26.3 °C/W
ψJT Junction-to-top characterization parameter 1.0 °C/W
ψJB Junction-to-board characterization parameter 26.1 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Over free-air temperature range and VDD = 1.7 V to 5.5 V (unless otherwise noted); Typical specifications are at TA = 25°C
and VDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE SENSOR
10°C to 45°C ±0.1 ±0.2 °C
Temperature accuracy
-40°C to 105°C ±0.3 °C
(TMP1827)
TERR -55°C to 150°C ±0.4 °C
Temperature accuracy
-55°C to 150°C ±0.1 ±0.9 °C
(TMP1827N)
PSR DC power supply sensitivity ±0.03 °C/V

Temperature resolution (High Including sign bit 16 Bits

TRES
Precision Format) LSB 7.8125 m°C
Averaging enabled, Conversion Time = 5.5 ms,
TREPEAT Repeatability(1) 16-bit mode, ±2 LSB
1-Hz conversion rate, 300 acquisition
TLTD Long-term stability and drift 1000 hours at 150°C(2) 0.0625 °C
TSTART = –40°C
Temperature cycling and TFINISH = 150°C
THYST 4 LSB
hysteresis TTEST = 25°C
3 cycles

Response time (Stirred Single layer Flex PCB 0.77 s

τ = 63 %
tRESP_L Liquid) 2-layer 62-mil Rigid 25°C to 75°C 1.91 s
NGR Package PCB

Active Conversion time (No CONV_TIME_SEL = 0 2.54 3 3.37 ms

tACT (Figure 8-12)
Averaging) CONV_TIME_SEL = 1 4.69 5.5 6.12 ms
Start-up delay for temperature
tDELAY 100 300 µs
conversion
SDQ DIGITAL INPUT/OUTPUT

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Over free-air temperature range and VDD = 1.7 V to 5.5 V (unless otherwise noted); Typical specifications are at TA = 25°C
and VDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CIN SDQ pin capacitance 40 pF
VIL Input logic low level(3) –0.3 0.2 × VS V
VIH Input logic high level(3) 0.8 × VS VS + 0.3 V
VHYST Hysteresis 0.3 V
VOL Output low level IOL = –4 mA 0.4 V
IO CHARACTERISTICS
CIN Input capacitance 10 pF
VIL Input logic low level(3) –0.3 0.3 × VS V
VIH Input logic high level(3) 0.7 × VS VS + 0.3 V
IIN Input leakage current 0 ±0.12 µA
VOL Output low level IOL = –3 mA 0.4 V
RESISTOR ADDRESS DECODER CHARACTERISTICS
Load capacitance as seen
CLOAD on ADDR pin (includes PCB 100 pF
parasitics)
RADDR resistor range 6.49 54.9 kΩ
RADDR resistor tolerance TA = 25°C –1.0 1.0 %
RADDR resistor temperature
–100 100 ppm/°C
coefficient
RADDR resistor lifetime drift –0.2 0.2 %
tRESDET Resistor decoding time 2.8 ms
POWER SUPPLY
IPU Pullup current(5) Bus powered mode, serial bus idle 400 μA
Supply current during
IDD_ACTIVE Temperature Conversion, serial bus idle 94 154 μA
temperature conversion
VDD powered, serial TA = -55°C to 85°C 1.6 4.2
IDD_SB Standby current(4) bus inactive, continuous μA
conversion mode TA = -55°C to 150°C 24

Serial bus inactive, one TA = -55°C to 85°C 1.3 3.3

IDD_SD Shutdown current μA
shot conversion mode TA = -55°C to 150°C 23.2
Power-on reset threshold
Supply rising (Figure 7-4, Figure 7-5) 1.5 V
VPOR voltage
Brownout detect Supply falling 1.3 V
Time required by device to reset after power up
tINIT POR Initialization Time 2.0 ms
(Figure 7-4, Figure 7-5)

(1) Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.
See Figure 7-11
(2) Long term stability is determined using accelerated operational life testing at a junction temperature of 150°C.
(3) In bus powered mode VS = VPUR. In supply powered mode VS = VDD.
(4) Quiescent current between conversions.
(5) The pullup current parameter is required to size the bus pullup resistor (See Section 8.3.3) for active temperature conversion or
EEPROM read and program or authentication operations.

7.6 1-Wire® Interface Timing

Over free-air temperature range and VDD = 1.70 V to 5.5 V (unless otherwise noted)
STANDARD MODE OVERDRIVE MODE
UNIT
MIN MAX MIN MAX
BUS RESET AND BIT SLOT TIMING

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Over free-air temperature range and VDD = 1.70 V to 5.5 V (unless otherwise noted)
STANDARD MODE OVERDRIVE MODE
UNIT
MIN MAX MIN MAX
Host to device bus reset pulse width (Figure 7-1)
tRSTL (1) 480 560 48 80 µs

tRSTH Device to host response time (Figure 7-1)(2) 480 48 µs

Device turnaround time for bus reset
tPDH 15 60 2 8 µs
response (Figure 7-1)
tPDL Device to host response pulse width (Figure 7-1) 60 240 8 24 µs
tSLOT Bit slot time (Figure 7-2, Figure 7-3)(5) tWR0L + tRC tWR0L + tRC µs
tREC Recovery time (Figure 7-2, Figure 7-3) 2 2 µs
tGF Glitch filter width (Figure 7-6)(3) 0.48 0.025 µs
tF Fall time 100 100 ns
BIT WRITE TIMING
tWR0L Host write 0 width (Figure 7-2) 60 120 9 10 µs
tWR1L Host write 1 width (Figure 7-2) 2 15 1 2 µs
tRDV Device read data valid time (Figure 7-2) 15 2 µs
tDSW Device read data window (Figure 7-2) 15 45 2 7 µs
BIT READ TIMING
tRL Host drive read bit slot time (Figure 7-3)(4) 2.5 5 2 3 µs
Host wait time before read data sampling
tRWAIT tRL+tRC tRL+tRC µs
window (Figure 7-3)(5)
tMSW Host read data sampling window (Figure 7-3)(5) tRL+tRC 30 tRL+tRC 3 µs

(1) In bus powered mode, extending the tRSTL above 600 µs can cause the device to power on reset
(2) The tRSTH is the maximum time the host must wait to receive a response from the furthest device, taking into account the propagation
delay and recovery time for all the devices.
(3) The glitch filter timing applies only on the rising edge of the SDQ signal
(4) tRL minimum time includes the glitch filter timing
(5) The tRC time is defined as the time taken for the bus voltage to rise from 0V to minimum VIH of the device. This is a function of the bus
pullup resistor, devices and parasitic capacitance of the trace or cable. The parameters must be characterized for the application.

7.7 Security Engine Characteristics

Over free-air temperature range and VDD = 1.7 V to 5.5 V (unless otherwise noted)
MIN TYP MAX UNIT
tHASH_DATA Computation time for SHA-256 hash calculation for data size of 8 bytes 380 µs
tDECOMMISSION Time for decommission of the device 78 130 ms
IDD_HASH Hash computation current 360 µA

7.8 EEPROM Characteristics

Over free-air temperature range and VDD = 1.7 V to 5.5 V (unless otherwise noted); Typical specifications are at TA = 25°C
and VDD = 3.3 V (unless otherwise noted)
MIN TYP MAX UNIT
Programming time for 8-byte data word in user EEPROM 13.2 21 ms
tPROG
Programming time for register copy to EEPROM 26.4 42 ms
tREADIDLE Idle bus time for EEPROM 8-byte data read 560 µs
IDD_PROG Programming current 178 230 µA
at TA = 125°C 25 years
Data Retention
at TA = 150°C 10 years
at TA = 125°C 20000 200000 cycles
Program Endurance
at TA = 150°C 1000 10000 cycles

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7.9 Timing Diagrams

Host drives SDQ
Device drives SDQ
High Impedance, external pullup

tPDL
VDD/VPUR

VIH
tPDH
tRSTL tRSTH
VIL

Figure 7-1. Bus Reset Timing Diagram

Host drives SDQ
High Impedance, external pullup
tSLOT tREC tSLOT tREC
VDD/VPUR VDD/VPUR

VIH VIH

VIL VIL

tRDV tDSW tRDV tDSW

tWR1L
tWR0L
Host Write-1 Host Write-0

Figure 7-2. Write Timing Diagram

Host drives SDQ
Device drives SDQ
High Impedance, external pullup

tSLOT tREC tSLOT tREC

VDD/VPUR VDD/VPUR

VIH VIH

tRWAIT tRWAIT

VIL VIL

tRL tMSW tRL tMSW

Host Read-1 Host Read-0

Figure 7-3. Read Timing Diagram

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VDD
VPOR

0V
VSDQ Bus Idle Bus Ac
ve

SDQ Pin

tINIT

Figure 7-4. VDD Powered Initialization Timing Diagram

VPUR Bus Idle Bus Active

VPOR

0V
tINIT

Figure 7-5. Bus Powered Initialization Timing Diagram

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Host drives SDQ

High Impedance, external pullup

VPUR

VIH

VIL

tGF

Logic H
Input of
Logic L Glitch Filter

Logic H
Output of
Logic L Glitch Filter
Figure 7-6. Glitch Filter Timing Diagram

7.10 Typical Characteristics

0.6 140
1.7 V
0.5 3.3 V
130 5.5 V
0.4
DS Max
0.3
Te mperature Error (C)

120
0.2
A)

0.1 110
Current (

0
-0.1 100

-0.2
90
-0.3
DS Min
-0.4
80
-0.5
-0.6 70
-55 -25 5 35 65 95 125 150 -60 -40 -20 0 20 40 60 80 100 120 140
Te mperature (C) Temperature (C)

. .

Figure 7-7. Temperature Error vs Temperature (NGR Package) Figure 7-8. Temperature Conversion Current vs Temperature

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7.10 Typical Characteristics (continued)

10 10
1.7 V 1.7 V
9 3.3 V 9 3.3 V
5.5 V 5.5 V
8 8

7 7
A)

A)
6 6
Current (

Current (
5 5

4 4

3 3

2 2

1 1

0 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C) Temperature (C)

. .
Figure 7-9. Shutdown Current vs Temperature Figure 7-10. Standby Current vs Temperature
80% 80%

70% 70%

60% 60%

Population (%)
Population (%)

50% 50%

40% 40%

30% 30%

20% 20%

10% 10%

0 0
-5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Normalized Data Distribution (LSB) Normalized Data Distribution (LSB)

TA = 25°C TA = 25°C

Figure 7-11. Data Distribution With 5.5-ms Conversion Time and Figure 7-12. Data Distribution With 3-ms Conversion Time and
Averaging On in 16-Bit Format Averaging On in 16-Bit Format
50% 50%

40% 40%
Population (%)

Population (%)

30% 30%

20% 20%

10% 10%

0 0
-5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Normalized Data Distribution (LSB) Normalized Data Distribution (LSB)
TA = 25°C TA = 25°C
Figure 7-13. Data Distribution With 5.5-ms Conversion Time and Figure 7-14. Data Distribution With 3-ms Conversion Time and
Averaging Off in 16-Bit Format Averaging Off in 16-Bit Format

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7.10 Typical Characteristics (continued)

80% 90
Bus Powered-Overdrive Mode 2-layer FR4 PCB
Bus Powered-Standard Mode 85 Single Layer Flex PCB .
70% VDD Powered 63% Response
80
75
60%
70

Temperature ( C)
Population (%)

50% 65
60
40% 55
50
30% 45
40
20%
35

10% 30
25
0 20
-5 -4 -3 -2 -1 0 1 2 3 4 5 -1 0 1 2 3 4 5 6 7
Normalized Data Distribution (LSB) Time (sec)
TA = 25°C, 5.5-ms conversion time, Averaging On, 16-bit .
format .
Figure 7-15. Data Distribution for Power Mode and Bus Speed Figure 7-16. Thermal Response Time (NGR)
2.6

2.5

2.4

2.3
VPUR Supply (V)

2.2

2.1

1.9

1.8

1.7

1.6
90 95 100 105 110 115 120 125 130 135 140 145 150
Temperature (C)
.
Figure 7-17. VPUR Typical Standard Speed Mode Supply Voltage vs Temperature

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8 Detailed Description
8.1 Overview
The TMP1827 is a digital output temperature sensor designed for thermal-management and thermal-protection
applications. The TMP1827 is a 1-Wire® device which can operate in either supply powered or bus powered
(parasitic powered) mode. The device features a 2Kb EEPROM, SHA-256-HMAC based authentication engine.
Figure 8-1 shows the TMP1827 block diagram.
8.2 Functional Block Diagram

ADDR Internal IO3

thermal
BJT
Oscillator
Con
guraon Temperature IO2/ALERT
1-Wire Interface EEPROM sensor circuit
VDD Power Control & Controller
Device Capacitor

ScratchPad-1 ADC IO1

SDQ
ScratchPad-2 2Kb User EEPROM
IO0

Security
Key and
Controller
Memory
and SHA-256-
Protec on
HMAC

GND

Figure 8-1. Functional Block Diagram

8.3 Feature Description

8.3.1 Power Up
The device operates in both supply powered and bus powered mode. In both modes, when the supply voltage
reaches within the operating range, the device requires tINIT to initialize. After tINIT, the host MCU can begin
accessing the device.
During initialization, the device can not respond to any bus activity. When initialization is complete, the device
shall wait for the bus reset from the host. During the initialization for the device, the following events take place:
• The EEPROM content for short address, temperature alert low, temperature alert high and temperature offset
registers are restored.
• The EEPROM for the IO configuration register is read and contents of the IO configuration register is
restored.
• The EEPROM content for device configuration-1 and device configuration-2 registers are restored to the
respective registers.
– If the ARB_MODE bits is restored as '10b' or '11b', then the device responds to the SEARCHADDR in
arbitration mode.
– If OD_EN bit is set to '1b', then the device shall communicate in overdrive speed, unless the first bus reset
pulse from the host is sent in standard speed.
• The user memory protection bits are restored and appropriate protection to the user EEPROM block applied.
• The authentication key and secret bytes are read from the EEPROM to internal flops for the authentication
operation.

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8.3.2 Power Mode Switch

The device is designed to operate in supply powered or bus powered mode. The dual mode implementation
provides a unique method of redundancy that, even in cases where the power supply pin VDD becomes 0V, the
device can draw power from data pin, as long as the pullup resistor value used is as per the specification limit.
When the device switches from supply powered to bus powered mode, the device shall operate with the same
settings until the internal capacitor is able to provide the current draw required by the device for communication
and the external pullup resistor can keep SDQ voltage above 1.7V during ADC and EEPROM programming.
If the internal voltage on the capacitor drops below the brown-out threshold, the device shall switch off and
enter bus powered mode of communication on subsequent power up. When the device completes the power-up
initialization sequence, as described earlier, the device shall respond to first bus communication starting with the
bus reset sequence.
8.3.3 Bus Pullup Resistor
The bus pullup resistance value selected is important for communication as per the speed mode and verifying
that the minimal possible energy is consumed in the application. If the resistor value is too small, the design can
violate the VOL limits on the SDQ pin.
Consider the total SDQ pins and bus capacitance along with the bus leakage current when selecting the pullup
resistor. The pullup resistance value selected must also verify that the signal level reaches VIH as per the timing
requirements for standard and overdrive mode.
In bus powered mode of operation, the device charges the internal capacitor through the SDQ pin and the pullup
resistor. This charge on the capacitor is used during bus communication, when the SDQ pin low. For other high
current functions like thermal conversion and EEPROM access, the bus is held idle to verify that the device
can draw current through the pullup resistor. The SDQ pin voltage during the high current operation must be
maintained to provide sufficient operating margins. For VPUR ≤ 2.0 V, use Equation 1 along with a low impedance
current path. For VPUR > 2.0 V, use Equation 2 to calculate the pullup resistor value.

VPUR – VOL MAX VPUR – 1.6

< RPUR < (1)
4 × 10–3 300 × 10–6

VPUR – VOL MAX VPUR – VIH MIN

< RPUR < IPU MIN (2)
4 × 10–3

When the device is used in VDD or supply powered mode, a larger pullup resistor value can be used, as the SDQ
pin is used only for communication. The user must verify that the pullup resistor value selected must be able to
support the timing for the required bus speed of operation.
For low current consumption devices like the TMP1827, selecting the correct pullup resistor value allows
the application to avoid low impedance current path components for bus powered mode of operation while
maintaining communication speeds and device parameters as per the electrical specification. For multiple
devices on the bus, a low impedance current path is recommended.
8.3.4 Temperature Results
The conversion is initiated by the host MCU by sending the temperature conversion command if the automatic
conversion is disabled, immediately after the presence detect is completed when the automatic conversion is
enabled, or in continuous conversion mode if the device is VDD powered. At the end of every conversion, the
device updates the temperature registers temperature result and the status register bits. Figure 8-2 shows that
the device supports a high precision and legacy format, which can be configured through the TEMP_FMT bit in
the device configuration-1 register. The default setting for the temperature result is legacy format for software
compatibility.

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Temperature Result MSB Register Temperature Result LSB Register

High Precision Format

S 27 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7

Legacy Format
S S S S S 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4

Figure 8-2. Temperature Format

If the format selected is the high precision 16-bit format, the data in the result registers is stored in two's
complement form and has a resolution of 7.8125m°C and a range of ±256°C. If the format selected is the legacy
12-bit format, the data in the result register is stored in sign extended form and has a resolution of 62.5m°C
and a range of ±128°C. The temperature register reads as 0°C before the first conversion. Table 8-1 and Table
8-2 show examples of possible binary data that can be read from the temperature result registers and the
corresponding hexadecimal and temperature equivalents for both formats.
Table 8-1. Precision (16-Bit) Temperature Data Format
TEMPERATURE DIGITAL OUTPUT (PRECISION FORMAT)
(°C) BINARY HEXADECIMAL
150 0100 1011 0000 0000 4B00
127 0011 1111 1000 0000 3F80
100 0011 0010 0000 0000 3200
25 0000 1100 1000 0000 0C80
1 0000 0000 1000 0000 0080
0.125 0000 0000 0001 0000 0010
0.03125 0000 0000 0000 0100 0004
0.0078125 0000 0000 0000 0001 0001
0 0000 0000 0000 0000 0000
–0.0078125 1111 1111 1111 1111 FFFF
–0.03125 1111 1111 1111 1100 FFFC
–0.125 1111 1111 1111 0000 FFF0
–1 1111 1111 1000 0000 FF80
–25 1111 0011 1000 0000 F380
–40 1110 1100 0000 0000 FC00
–55 1110 0100 1000 0000 F480

Table 8-2. Legacy (12-Bit) Temperature Data Format

TEMPERATURE DIGITAL OUTPUT
(°C) BINARY HEXADECIMAL
140 0000 0111 1111 1111 07FF
128 0000 0111 1111 1111 07FF
127.9375 0000 0111 1111 1111 07FF
100 0000 0110 0100 0000 0640
25 0000 0001 1001 0000 0190
1 0000 0000 0001 0000 0010
0.125 0000 0000 0000 0010 0002
0 0000 0000 0000 0000 0000
–0.125 1111 1111 1111 1110 FFFE
–1 1111 1111 1111 0000 FFF0
–25 1111 1110 0111 0000 FE70

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Table 8-2. Legacy (12-Bit) Temperature Data Format (continued)

TEMPERATURE DIGITAL OUTPUT
(°C) BINARY HEXADECIMAL
–40 1111 1101 1000 0000 FD80
–55 1111 1100 1001 0000 FC90

8.3.5 Temperature Offset

The temperature offset has the same format as the temperature result and is stored in the temperature offset
registers.
The device, after every temperature conversion, applies the offset value before the temperature is stored in the
temperature result register. The host write to the offset register can be stored in the configuration EEPROM of
the device, which removes the overhead for the host to reprogram the value or reapply in software at every
power up. The offset features allow the device to achieve better accuracy at the temperature range for the
application by performing a single point calibration.
8.3.6 Temperature Alert
The temperature alert feature uses the temperature alert low registers for low threshold comparison and
temperature alert high registers for high threshold comparison. The format of the register is the same as the
temperature results.
The device shall compare the result of the last conversion with the alert thresholds. If the temperature result
is less than the low limit, or more than the high limits, then the device shall set the appropriate alert status
flag, in the status register. The alert status flags are cleared based on the ALERT_MODE setting in the device
configuration-1 register.
Additionally, if the IO2/ALERT pin is configured as an alert pin, the alert status is reflected on the pin in supply
powered mode.
8.3.7 Standard Device Address
Every device comes with a unique 64-bit address that is factory programmed. Additionally the device provides
flexible addressing modes that the host controller can use to improve bus throughput. This is described below.
8.3.7.1 Unique 64-Bit Device Address and ID
The device has a hard-coded, 64-bit address which is factory programmed and cannot be altered by the
customer application. The unique 64-bit device address is used for device addressing in the end application and
for NIST traceability. Figure 8-3 shows the format of the 64-bit address. When the host accesses the device or
when the device sends the address, the 64-bit unique address is sent least significant bit first. The unique 64-bit
address consists of 3 fields. The lower 8 bits consists of the device family code, followed by a 48-bit unique
number and 8-bit CRC checksum on the preceding 56 bits.
The device family code for TMP1827 shall read as 27h.
MSb LSb MSb LSb MSb LSb
8-bit CRC 48-bit Unique Address 8-bit Device Family
Bit-63 Bit-0
Figure 8-3. 64-Bit Device Address

8.3.8 Flexible Device Address

Depending on the user application case, the TMP1827 provides for some user and application configurable
address modes, called flexible address mode. These modes exist alongside the standard device address, and is
extremely useful for applications that require a combination of faster access and device position identification.
When the flexible device address is used, the short address register is updated. The short address register shall
be updated by the host write when the FLEX_ADDR_MODE bits are '00b'. When these bits are changed from

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the value '00b', the device decodes the address resistor connected on ADDR pin or IOs or both of them and
overlay on the short address register. This is helpful as the same set of 16 resistors or 16 IO combinations can
be used for up to 256 unique flexible address.
The FLEX_ADDR_MODE is not stored in the configuration EEPROM, therefore the host must copy the short
address register content into EEPROM configuration memory to make the short address values permanent
without the need to decode at every power up.
8.3.8.1 Non-Volatile Short Address
Figure 8-4 shows the user-programmable, 8-bit short address mode of the device. The host must copy the 8-bit
short address to the configuration EEPROM, so that at subsequent power up, the device loads the updated short
address and respond to the host.
MSb LSb
NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0
Bit-7 Bit-0
Figure 8-4. Non-Volatile Short Address

8.3.8.2 IO Hardware Address

Figure 8-5 shows the 8-bit IO hardware address mode of the device. This feature is available on packages
which have general-purpose pins (IO0-IO3) available. The 8-bit value consists of the lower 4 bits as read values
of the pins (IO3 to IO0) that is overlaid on the contents of the short address register to form a 8-bit address.
The application can connect the general-purpose pins to either VDD/SDQ for logic '1' or GND for logic '0'. TI
recommends to use a 20 KΩ resistor to be placed between the IO and VDD/SDQ to prevent a supply shot in case
the IO pin is accidentally set to zero in output mode.
After having FLEX_ADDR_MODE as '00b', the host must set the bits as '01b' in the device configuration-2
register for the device to latch the state of the general-purpose pins.
MSb LSb
NV7 NV6 NV5 NV4 IO3 IO2 IO1 IO0
Bit-7 Bit-0
Figure 8-5. IO Hardware Address

Note
IO pins must be configured as input before using IO hardware address mode. If any of the IO0 to IO3
pins are used in output mode, then the respective value shall be latched as '0'.

8.3.8.3 Resistor Address

The resistor address modes uses E96-series (1% tolerance) standard resistor connected between the ADDR pin
and ground. Figure 8-6 shows the 8-bit address with the lower 4 bits decoded from the resistor connected, which
is overlaid on the contents of the short address register.
MSb LSb
NV7 NV6 NV5 NV4 RA3 RA2 RA1 RA0
Bit-7 Bit-0
Figure 8-6. Resistor Address

After having FLEX_ADDR_MODE as '00b', the host controller must set the bits as '10b' in the device
configuration-2 register which enables the device to decode the resistor connected. After writing the device
configuration-2 register, the host must place the device in shut down mode and idle the bus for tRESDET, for

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the device to decode the resistor address. Table 8-3 shows the set value of the device address based on the
decoded resistor value. If the ADDR pin connected to GND or lower than 6.49 kΩ, then the address decoder
shall always decode as '0000b'. Similarly, if the ADDR pin is connected to a resistor higher than 54.9 kΩ, the
address decoder shall always decode as '1111b'.
Table 8-3. Resistor Address Decode
RESISTOR VALUE (kΩ) ADDRESS DECODE
< 6.49 0h
7.87 1h
9.31 2h
11.0 3h
13.3 4h
15.4 5h
17.8 6h
20.5 7h
23.7 8h
26.7 9h
30.1 Ah
33.2 Bh
37.4 Ch
42.2 Dh
47.5 Eh
> 54.9 or floating Fh

This mode is useful when the application requires placing the TMP1827 on multiple printed circuit boards
(PCBs). The Bill of Materials (BOM) component can be changed easily instead of having multiple PCBs
fabricated for individual pin connections, thereby reducing the cost of the system.

Note
If unused, the ADDR pin is recommended be connected to GND. The CLOAD for ADDR pin is due to
parasitic capacitance depending on the board layout.

8.3.8.4 Combined IO and Resistor Address

In the combined IO and resistor address mode, the IO0 and IO1 pins are used along with the resistor connected
between ADDR pin and ground. Figure 8-7 shows the 8-bit address with the lower 4 bits decoded from the
resistor connected, followed by 2 bits decoded from the IO0 and IO1 pins which can be connected to either
VDD/SDQ for logic '1' or GND for logic '0', which is overlaid on the contents of the short address register. TI
recommends to use a 20 KΩ resistor to be placed between the IO and VDD/SDQ to prevent a supply shot in case
the IO pin is accidentally set to zero in output mode.
After having FLEX_ADDR_MODE as '00b', the host must set the bits as '11b' in the device configuration-2
register which enables the device to sample the ADDR pin to identify the resistor connected, followed by
sampling of the IO0 and IO1 to configure the short address. If the bit field value has already been updated in the
non-volatile storage, then the device shall automatically latch the pins, run the resistor decoder, and update the
value in the short address register on power up.
The host controller must place the device in shut down mode and idle the bus for tRESDET, for the device to
decode the resistor address.

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MSb LSb
NV7 NV6 IO1 IO0 RA3 RA2 RA1 RA0
Bit-7 Bit-0
Figure 8-7. Combined IO and Resistor Address

This mode is useful when the application requires placing up to 64 devices on a single PCB, as the mode
allows for easy expansion using a combined approach of IO and resistor decoding while enabling IO2 and IO3 to
function as general-purpose input and output pins. This mode can also be used for position identification as no
two devices can have the same short address.

Note
IO pins must be configured as input before using IO hardware address mode. If the IO0 or IO1 pins
are used in output mode, then the respective value shall be latched as '0'.

8.3.9 CRC Generation

The TMP1827 implements a cyclic redundancy check (CRC) mechanism for data integrity check and
communication robustness. Table 8-4 lists the properties of a 8-bit CRC.
Table 8-4. CRC-8 Rule
CRC-8 RULE ATTRIBUTES

CRC width 8 bits

CRC polynomial x8 + x5 + x4 + 1 (0x31)

Initial seed value 00h

Input data reflected Yes

Output data reflected Yes

XOR value 00h

When a new transaction is done, the shift register is initialized with the seed value of 00h and the data is shifted
in LSB first. The CRC result is always part of the 64-bit unique address and is computed on the preceding
56-bits. Additionally, when the host writes to the scratchpad-1 for the registers and scratchpad-2 for the memory,
the device sends the CRC computed on the data bytes to provide a data integrity check for the host on the
transaction. When the host reads the scratchpad-1 for reading the temperature register, the device shall append
the CRC after the 8 bytes of scratchpad are sent.
The host must recalculate the CRC and compares the recalculation against the received CRC from the device.
This is done by shifting the read data from the device along with CRC bits. If there is no bus error, then the shift
register at the end of the bit shift results in 00h. When writing the data to the device, the host must check the
CRC received by processing the write data to verify that there are no transmission errors and take appropriate
corrective action before performing the next function.
8.3.10 Functional Register Map
The scratchpad-1 region and the IO register region together are referred to as the functional register map
(see Figure 8-8). The scratchpad-1 region is 16 bytes deep, and has temperature result, device status, device
configuration, short address, temperature alert limits and temperature offset registers. The IO register region
has the IO read and IO configuration registers. Some of the registers can be committed to the configuration
EEPROM to verify that the device settings are restored on power up without the host rewriting the configuration.

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Scratchpad-1
Byte-0 Temperature Register LSB

Byte-1 Temperature Register MSB Back up EEPROM

Byte-2 Status Register

Byte-3 Reserved = FFh

Byte-4 Device Con
guraon-1 Register Device Conguraon-1 Register

Byte-5 Device Con guraon-2 Register Device Con gura on-2 Register
Byte-6 Short Address Register Short Address Register
Byte-7 Reserved = FFh

Byte-8 Temperature Alert Low LSB Temperature Alert Low LSB

Byte-9 Temperature Alert Low MSB Temperature Alert Low MSB
Byte-10 Temperature Alert High LSB Temperature Alert High LSB
Byte-11 Temperature Alert High MSB Temperature Alert High MSB
Byte-12 Temperature Oset LSB Temperature Oset LSB
Byte-13 Temperature O set MSB Temperature Oset MSB
Byte-14 Reserved = FFh

Byte-15 Reserved = FFh

IO Registers
IO Read Register

IO Con gura on Register IO Conguraon Register

Figure 8-8. Functional Register Map (Scratchpad-1)

8.3.11 User Memory Map

The EEPROM memory is organized as 8 pages of 4 blocks each. Figure 8-9 shows that each block is 8 bytes or
64 bits. This results in a total user memory of 2048 bits. All memory access to the device shall be increments of
a block size of 8 bytes. Access to the memory for programming is done through the scratchpad-2 register. The
host writes to the scratchpad-2 register, which allows the device to perform a read before committing the content
to the memory.

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00FFh Block 3 00F8h – 00FFh

Block 2 00F0h – 00F7h
Page 7
Block 1 00E8h – 00EFh
00E0h Block 0 00E0h – 00E7h
00DFh Block 3 00D8h – 00DFh
Block 2 00D0h – 00D7h
Page 6
Block 1 00C8h – 00CFh
00C0h Block 0 00C0h – 00C7h
00BFh Block 3 00B8h – 00CFh
Block 2 00B0h – 00B7h
Page 5
Block 1 00A8h – 00AFh
00A0h Block 0 00A0h – 00A7h
009Fh Block 3 0098h – 009Fh
Block 2 0090h – 0097h
Page 4
Block 1 0088h – 008Fh
256 bytes

0080h Block 0 0080h – 0087h

007Fh Block 3 0078h – 007Fh
Block 2 0070h – 0077h
Page 3
Block 1 0068h – 006Fh
0060h Block 0 0060h – 0067h
005Fh Block 3 0058h – 005Fh
Block 2 0050h – 0057h
Page 2
Block 1 0048h – 004Fh
0040h Block 0 0040h – 0047h
003Fh Block 3 0038h – 003Fh
Block 2 0030h – 0037h
Page 1
Block 1 0028h – 002Fh
0020h Block 0 0020h – 0027h
001Fh Block 3 0018h – 001Fh
32 bytes

Block 2 0010h – 0017h

Page 0
Block 1 0008h – 000Fh
0000h Block 0 0000h – 0007h

Figure 8-9. Address to EEPROM Page and Block Map

Note
The device shall return "1" for any device read if the address is outside the user memory map.

8.3.12 SHA-256-HMAC Authentication Block

The authentication block on the TMP1827 device uses a keyed-hash message authentication code (HMAC)
which is FIPS PUB-198-1 compliant SHA-256 hash implementation. The SHA-256 implementation is FIPS
PUB-180-4 compliant. The HMAC engine does not encrypt the data, but generates a 256-bit hash based on the
user programmed keys.
For details on SHA-256-HMAC authentication block, refer to the TMP1827 Security Programming Guide.

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8.3.13 Bit Communication

The 1-Wire® interface communication does not have a reference clock, therefore all communication is
performed asynchronously with fixed time slot (tSLOT) and variable pulse width to indicate logic '0' and '1'. In
idle state, the external pullup resistor holds the line high. All bit communication, whether the communication is a
write or a read, are initiated by the host by driving the data line low to generate a falling edge and the bit value is
decoded as the time for which the data line is held low or high after the falling edge.
Even though the communication is one bit at a time, the data exchanged between the host and device is
performed at byte boundary. Every byte is sent least significant bit first. The device behavior is not ensured when
incomplete bytes are sent.
8.3.13.1 Host Write, Device Read
A host write is the means by which the host sends the command, function, and data to the devices. A host write
starts by the host driving the data line low as shown in Figure 8-10. If the host intends to transmit a logic '1', the
line is released after tWR1L time. If the host intends to transmit a logic '0', the line is released after tWR0L. After
releasing the data, the pullup resistor causes the line to become high till the beginning of the next time slot. The
device samples the line after tRDV has elapsed from the falling edge, for a time frame indicated by tDSW. The host
must factor the rise time due to the pullup resistor and bus capacitance to determine the release of the data line
before the line is sampled by the device and the host drives the next write bit time slot.
Host drives SDQ
High Impedance, external pullup
tSLOT tREC tSLOT tREC
VDD/VPUR VDD/VPUR

VIH VIH

VIL VIL

tRDV tDSW tRDV tDSW

tWR1L
tWR0L
Host Write-1 Host Write-0

Figure 8-10. Host Write, Device Read

8.3.13.2 Host Read, Device Write

A host read is the means by which the hosts gets the data from the device or the CRC for data integrity check. A
host read starts by the host driving the data line low as shown in Figure 8-11. When the device detects the falling
edge, the device can drive the line low before the time tRL. The host can release the bus from the side after the
time tRL(MIN) elapses. If the device intends to transmit a logic '1', then the bus is released before tRL(MAX) elapses.
If the device intends to transmit a logic '0', then the bus is released after tSLOT(MIN). The host must sample the
line after the time tRWAIT, for a time frame indicated by tMSW. The host must factor the rise time due to the pullup
resistor and bus capacitance to determine the sampling window for the host to sample the bit level sent by the
device or to drive the next read bit time slot.

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Host drives SDQ
Device drives SDQ
High Impedance, external pullup

tSLOT tREC tSLOT tREC

VDD/VPUR VDD/VPUR

VIH VIH

tRWAIT tRWAIT

VIL VIL

tRL tMSW tRL tMSW

Host Read-1 Host Read-0

Figure 8-11. Host Read, Device Write

8.3.14 Bus Speed

The device supports both standard speed (8.33 kbps) and overdrive speed (90 kbps) data rates. All devices
are factory programmed to start in overdrive speed to enable higher data throughput. If the host requires the
device to operate at standard speed, then the host can easily switch the device by issuing a standard speed bus
reset. The seamless switchover allows the host to leverage better data rates on new designs, while maintaining
backward compatibility for older design.
Additionally, the device also provides the flexibility to switch from standard to overdrive speed mode using
address phase commands of OVD SKIPADDR and OVD MATCHADDR.
• When host issues OVD SKIPADDR, then all devices capable to support the overdrive mode on the bus
switch, from standard speed to overdrive speed.
• When host issues OVD MATCHADDR, then the device whose 64-bit device address matches the address
that host sends switches from standard to overdrive speed.
8.3.15 NIST Traceability
The accuracy of temperature testing is verified with equipment that is calibrated by an accredited lab that
complies with ISO/IEC 17025 policies and procedures. Each device is tested and trimmed to conform to the
respective data sheet specification limits.
8.4 Device Functional Modes
The TMP1827 device features flexible one-shot temperature conversion modes along with robust user EEPROM
architecture, which is described in the sections below.
8.4.1 Conversion Modes
The TMP1827 supports both one-shot and continuous conversion modes. There are different methods for
one-shot conversion modes, that can be used based on single device or multiple device bus network. The
continuous conversion mode is only supported in VDD powered mode. Each of the conversion modes are with
single temperature sample, but the host can enable eight samples averages in the device for improved accuracy.
The conversion always results in a single temperature sample, but the host can enable eight samples averages
in the device to reduce conversion noise and improve accuracy.
8.4.1.1 Basic One-Shot Conversion Mode
The basic one-shot conversion mode is the default conversion mode. The device goes through a bus reset,
address and function phase to initiate the temperature conversion. During the communication, the device is in
shutdown mode. When the conversion request is registered by the device, the device starts active conversion
and then goes back to low power shutdown mode (see Figure 8-12). If the device is in continuous conversion
mode, then the one-shot conversion mode request is ignored.

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Bus Answer to SKIPADDR CONVERT

Reset
Communicaon Reset (CCh) TEMP (44h)
8 Samples
Start of Conversion
Averaging Enabled
Command startup delay (tDELAY)
Ac
ve conversion me (tACT)
Shutdown Shutdown
Temperature
Conversion

Figure 8-12. One-Shot Conversion Mode

As shown in Figure 8-13, there is no change in how one-shot conversion is performed when there are multiple
devices on the bus. However, as there are multiple devices, the combined current drain in bus powered mode
of operation can cause the bus voltage to drop. In such use cases,the host is required to implement a low
impedance current path using a FET/transistor switch activated before tDELAY. This path is switched on to meet
the current requirement of the bus during an active conversion and after the active conversion duration is
complete, the path is switched off for bus communication.
Answer to
Bus Communicaon
SKIPADDR CONVERT TEMP
Reset (CCh) (44h)
Reset
Start of Conversion

Temperature
Conversion Sequence
Command startup delay (tDELAY) Ac
ve conversion me (tACT)

Shutdown Shutdown
TMP18xx
Device 0

TMP18xx
Device 1

TMP18xx
Device 2

Figure 8-13. Multiple Device One-Shot Conversion Mode

8.4.1.2 Auto Conversion Mode

The auto conversion mode is a programmable feature in bus powered mode that can be enabled by setting the
CONV_MODE_SEL as '10b' in the device configuration-1 register. As shown in Figure 8-14, the host can skip
the issue of the temperature conversion request and directly read the temperature data from the device when
the auto conversion mode is enabled. This enables the application to speed up the temperature conversion
and read, because the request command is no longer required. As in the case for multiple device bus, a low
impedance current path is required to meet the current requirement of the bus during the active conversions.
Bus Answer to MATCHADDR 64-bit Device READ SCRATCHPAD-1
Reset
Communicaon Reset (55h) Address (BEh)
Start of Conversion

Command startup delay (tDELAY)

Ac
ve conversion me (tACT)
Shutdown Shutdown
Temperature
Conversion

Figure 8-14. Auto Conversion Mode

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8.4.1.3 Stacked Conversion Mode

The stacked conversion mode is a programmable feature in bus powered mode that can be enabled by setting
CONV_MODE_SEL as '01b' in the device configuration-1 register. As shown in Figure 8-15, the devices can
use the address programmed in the short address register to delay the temperature conversion for the devices
when the stacked conversion mode is enabled. No more than two devices are actively converting at any given
time, therefore the current drain in bus powered configuration is limited. This allows the application to avoid
simultaneous temperature conversion by multiple parts and reducing the user system maximal supply current.
Answer to SKIPADDR CONVERT
Bus Communica
on Reset
Reset (CCh) TEMP (44h)
Start of Conversion

Temperature Command startup delay (tDELAY)

Conversion Sequence

Shutdown
TMP18xx
STACKMODE ADDRESS = 0

TMP18xx
STACKMODE ADDRESS = 1

TMP18xx
STACKMODE ADDRESS = 2

Note
The host controller must program all the device with the same setting for CONV_TIME_SEL and
AVG_SEL to verify that no more than two devices are actively converting to use the feature as the
feature is intended.

Figure 8-15. Stacked Conversion Mode

8.4.1.4 Continuous Conversion Mode

The continuous conversion mode is applicable only in VDD powered mode of operation for the device. This mode
can be enabled by writing a value other than '000b' to CONV_MODE_SEL bits in the device configuration-1
register. As shown in Figure 8-16, the device can perform periodic conversions at the interval programmed
by the host and updates the temperature result register when continuous conversion mode is enabled. The
device also performs the alert threshold check and sets the flags and alert pin, if configured accordingly. When
in continuous conversion mode, the CONVERTTEMP function has no effect on the temperature conversion
request. The application can at any time change the rate of conversion or put the device back into one-shot
conversion mode, and this takes effect only after the current conversion is complete.
Start of conversion
Averaging

Active conversion time

(tACT)

Conversion interval Conversion interval

(tCONV)
Figure 8-16. Continuous Conversion Mode

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If due to any reason, the VDD supply fails without the device going through a brownout and causes the device
to move to bus powered mode of operation, the conversion mode automatically reverts to the setting in the
configuration EEPROM.
8.4.2 Alert Function
As described earlier, the built-in alert function can be used by the host to check if the temperature has crossed a
certain threshold. The alert status bits are available in both bus powered and VDD powered mode. The alert pin
is available only in VDD powered mode.
If the device is in VDD powered mode and IO2/ALERT is configured to function as an IO2/ALERT pin, then the
pin shall be driven active low when the threshold crossing occurs. The pin is open-drain, and therefore requires
a pullup resistor. The IO2/ALERT pin deassertion is based on the setting of the ALERT_MODE setting in the
device configuration-1 register.
8.4.2.1 Alert Mode
The device operates in alert mode, when the ALERT_MODE is set as '0b'. In the alert mode of operation, the
alert status flag and IO2/ALERT pin are asserted when the last temperature conversion is either higher than the
temperature alert high limit or when temperature is lower than the temperature alert low limit register.
The alert status flag and IO2/ALERT pin are deasserted only when the host reads the status register or performs
a successful ALERTSEARCH command as shown in Figure 8-17.

ALERT_HIGH

Temperature

ALERT_LOW

Temperature conversions

ALERT_HIGH

ALERT_LOW

ALERT pin

Alert Status Read

Figure 8-17. Alert Mode Timing Diagram

8.4.2.2 Comparator Mode

The device operates in comparator mode, when the ALERT_MODE is set as '1b'. In the alert mode of operation,
the alert status flag and IO2/ALERT pin are asserted when the last temperature conversion is either higher than
the temperature alert high limit or when the temperature is lower than the temperature alert low limit register.
The alert status flag and IO2/ALERT pin are deasserted only when the result of the last temperature conversion
is less than the temperature alert high limit minus the hysteresis or above the temperature low limit plus the
hysteresis as shown in Figure 8-18. The hysteresis is selectable using the HYSTERESIS bit field in the device
configuration-2 register.

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ALERT_HIGH

ALERT_HIGH-HYSTERESIS

Temperature
ALERT_LOW+HYSTERESIS

ALERT_LOW

Temperature conversions

ALERT_HIGH

ALERT_LOW

ALERT pin

Alert Status Read

Figure 8-18. Comparator Mode Timing Diagram

8.4.3 1-Wire® Interface Communication

To leverage the features effectively, the device access consists of three distinct phases. As shown in Figure
8-19, any bus communication starts with a bus reset condition to which every device on the bus must respond.
This is followed by a highly configurable address phase, where the host selects the device the host wants to
access. Finally, there is a function phase where the host provides the selected devices the action the host wants
to take.
Bus Reset Phase Address Phase Func on Phase

Write Data

Answer to
Reset Command Device Address Func
on CRC
Reset

Read Data

Figure 8-19. 1-Wire® Bus Communication

In a 1-Wire® bus, all write and reads are initiated by the host except for the answer to reset which is initiated by
the devices on the bus.
8.4.3.1 Bus Reset Phase
The bus reset phase is the beginning of the communication. The phase is initiated by the host by holding the
1-Wire® data line low for a period tRSTL. All devices on the bus, irrespective of the current state shall respond
to the bus reset, by reinitializing the internal state and responding to the host initiated bus reset. The devices
respond after a minimum of tPDH, by holding the 1-Wire® low for a time period of tRSTH as shown in Figure 7-1.
All devices when powered up are configured with the OD_EN bit set as '1' in the device configuration-2 and OD
flag set as '1' in status register. If the host sends a bus reset pulse of 48 µs to 80 µs, then only devices operating
in overdrive speed shall respond to the bus reset pulse, while devices operating in standard mode shall continue
to wait for a standard mode bus reset.
If the host sends a bus reset pulse of minimum tRSTL for standard mode, the device shall reset the OD_EN bit
to '0' and respond to the bus reset in standard mode. If the bus consists of mixed standard and overdrive speed

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devices, then sending a bus reset pulse in standard mode shall reset all devices to standard mode speed of
operation.
Sending the bus reset for a particular speed of operation and then communicating at the other speed mode is
illegal for the host. Also, if a bus reset pulse is sent which is greater than 80 µs (but less than 480 µs), then the
device communication is reset, though the device operation is not ensured.
8.4.3.2 Address Phase
Figure 8-20 shows the address phase that follows the bus reset phase. During this phase, the host presents
8-bit commands which can be followed by either host sending a 64-bit device address, a 8-bit flexible address, or
skipping the address. Some of the commands are used to discover the device address, while others are used to
select the device.
Host Sends Reset
Pulse

Yes Is Reset pulse No

width for Standard
Speed?
Yes
Is device in
Standard Speed?

No

TMP18xx switches
TMP18xx Responds
to Standard Speed.
in Overdrive Speed
OD Flag = 0

Host Sends Address

Command

No No No No No No No No
69h 3Ch
33h (READADDR)? 55h (MATCHADDR)? F0h (SEARCHADDR)? ECh (ALERTSEARCH)? CCh (SKIPADDR)? 0Fh (FLEXADDR)?
(OVD_MATCHADDR)? (OVD_SKIPADDR)?

Yes Yes Yes Yes Yes Yes Yes

TMP18xx Sends FLAG
TMP18xx Sends FLAG
Host Sends 8 Bytes of Host Sends 8 Bytes of Host Sends 1 Byte of
Address, LSb to MSb Host Sends FLAG Address, LSb to MSb Short Address, LSb to MSb

TMP18xx Sends 8 Bytes of

Address, LSb to MSb OD Flag = 0
Yes TMP18xx with
No Address Search Algorithm No
Does TMP18xx Alert Flag Set? Does TMP18xx No
Address Match? Address Match? Does TMP18xx Short
Address Match?

OD Flag = 0
Yes Yes
Yes
OD Flag = 1

Host Sends Func
on

Figure 8-20. Address Phase Flowchart

8.4.3.2.1 READADDR (33h)

The command can be used by the host to read the 64-bit address of the device. This command must only be
used when there is one device on the bus, as this command causes a collision if multiple devices are present on
the bus.
8.4.3.2.2 MATCHADDR (55h)
The command is used by the host and is followed by a 64-bit address that is used to select a single device on
the bus. The address for each device is unique, therefore only one device can be selected by the command
while all other devices continue to wait for a bus reset.
8.4.3.2.3 SEARCHADDR (F0h)
The command is used by the host to identify the 64-bit address of each of the devices on the bus after the
system is powered up (see Figure 8-21). Additionally, this command can be run by the host to discover any

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new devices that can be added to the system later. When there is a single device bus, the host can skip the
command and instead use the SKIPADDR or OVD_SKIPADDR commands to access the device.
As shown in right side flow of Figure 8-21, when the fast arbitration mode is enabled by setting ARB_MODE
bits as '11b' in the device configuration-2 register, the devices check the bus for the transmitted bit. If the device
reads a bit value other than what was transmitted, the device no longer responds to the command until the next
bus reset. A device that wins the bus continues until the 64th bit, sets the ARB_DONE bit in the status register
to '1b' and stops responding to the next SEARCHADDR command. The arbitration function allows the host a fast
discovery of the devices without having to go through the complicated, memory intensive and longer discovery
method using traditional SEARCHADDR command. At the same time, if the host has an issue on the bus, then
the host can simply perform a broadcast write to disable and enable the arbitration mode to restart the fast
arbitration mode.
The device also features an optimized arbitration mode which is enabled by setting ARB_MODE bits as '10b'.
The devices check the transmitted bit, and if the devices detect a logic '0' when the devices send a logic '1',
the devices do not participate in the SEARCHADDR command until the next SEARCHADDR command is sent.
The device that is able to send all 64 bits successfully, wins the bus and sets the ARB_DONE bit in the status
register to '1b' and stops responding to next SEARCHADDR command. As a result of the optimized arbitration
mode, the host does not have to manage the complex memory structure to identify devices on the bus and can
still use the legacy software search algorithm.
The host must top searching for devices when the host receives "FFFFFFFFh". The host must disable the
arbitration mode bits to clear the ARB_DONE status and enable only when the host wants to search for new
devices added to the existing bus.

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No No No
Address Command = Address Command =
ECh (ALERTSEARCH)? F0h (SEARCHADDR)?

Yes Yes

No No
Is ARB_MODE = 10? Is ARB_MODE = 11?

Yes Yes

TMP18xx Sends Bit 0 TMP18xx Sends Bit 0 TMP18xx Sends Bit 0

TMP18xx Sends Bit 0

Host Sends Bit 0

No No TMP18xx TMP18xx No
Bit-0 Match? Tx Bit-0 = Rx Bit-0 Tx Bit-0 = Rx Bit-0
Match? Match?
Yes
Yes Yes

TMP18xx Sends Bit 1 TMP18xx Sends Bit 0

TMP18xx Sends Bit 1 Host Sends Bit 0

Host Sends Bit 1

TMP18xx Sends Bit 1 TMP18xx Sends Bit 1

LEGACY ADDRESS SEARCH

OPTIMIZED ARBITRATION

FAST ARBITRATION
No No TMP18xx TMP18xx No
Bit-1 Match? Tx Bit-1 = Rx Bit-1 Tx Bit-1 = Rx Bit-1
Match? Match?

Yes Yes

TMP18xx Sends Bit 1

TMP18xx Sends Bit 63
Host Sends Bit 1
TMP18xx Sends Bit 63 Yes
Host Sends Bit 63
TMP18xx Sends Bit 63 TMP18xx Sends Bit 63

No No TMP18xx TMP18xx No
Bit-63 Match? Tx Bit-63 = Rx Bit-63 Tx Bit-63 = Rx Bit-63
Match? Match?

Yes Yes
Yes

TMP18xx Sends Bit 63

Host Sends Bit 63

Winning TMP18xx Drops out of Next SEARCH

Host Sends a Reset Pulse to restart the

1-Wire Bus communica
on

Figure 8-21. Address Search Algorithm Flowchart

8.4.3.2.4 ALERTSEARCH (ECh)

The command is used by the host to identify if any of the devices have an alarm condition that must be serviced
in alert mode. An alarm condition is set by the device when the temperature conversion is performed and the
temperature result is higher than alert high temperature register or lower than alert low temperature register.

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The command uses the same method as the SEARCHADDR command, except that only devices with an alarm
condition shall respond. If none of the devices have an alarm condition, then the host shall get '1' followed by '1'
on the bus. If the device sends a '1' followed by '0', the host shall interpret the data as either one or more devices
have an alert condition, or all devices have an alert condition. If there is a bus noise, that causes the line to be
sample erroneously, but if no device has an alert condition, then the host shall get all '1' on the bus during the
address search phase. The ARB_MODE bit does not have an impact on how the subsequent address search
algorithm works.
Only devices that have an alert set shall participate when the devices receive an ALERTSEARCH address
command and responds by sending the 64-bit address. A device shall no longer participate in the send address
phase if the device successfully transmits the device address, which automatically clears the internal alert flags,
releases the ALERT pin, until another temperature conversion results in the alert condition getting set. The host
controller must verify that all parts on the bus are configured in alert mode to use the command.
8.4.3.2.5 SKIPADDR (CCh)
The host can issue this command to select all the devices on the bus. This is useful when the host wants to write
to the scratchpad-1 or trigger the temperature conversion for all the devices on the bus. Additionally, the host
can use the command to increase the overall bus data throughput when there is a single device on the bus.
The host must take care to not issue the command when there are multiple devices on the bus. A collision on the
bus is caused if the host attempts to read the devices with this command.
8.4.3.2.6 OVD SKIPADDR (3Ch)
The host can issue this command to select all devices which support overdrive speed in a mixed speed bus.
This is useful when the host wants to write to the scratchpad-1 or trigger the temperature conversion for all
the devices on the bus that support overdrive speeds. Additionally, the host can use the command to increase
the overall bus data throughput when there is a single device on the bus. When the command is issued, only
devices that support overdrive mode shall set the internal OD flag as '1'.
The host must take care to not issue the command when there are multiple devices on the bus which support
overdrive mode. A collision on the bus is caused if the host attempts to read the devices with this command.
If the host issues a standard mode bus reset at any time, all devices which have OD flag set as '1' shall clear the
same and revert back to standard mode speed.
8.4.3.2.7 OVD MATCHADDR (69h)
The command is used by the host and is followed by a 64-bit address that is used to select a single device on
the bus in overdrive speed. The address for each device is unique, therefore only one device can be selected by
the command while all other devices have to wait for a bus reset. The selected device shall set the internal OD
flag as '1', and start all further communication in overdrive speed.
If the host issues a standard mode bus reset at any time, or selects another device using the OVD
MATCHADDR, then all other devices which have OD flag set as '1' shall clear the same and revert back to
standard mode speed.
8.4.3.2.8 FLEXADDR (0Fh)
The host issues the command to access a device by the short address that is configured in the short
address register. Using the command does not affect the 64-bit unique address of the device. The FLEXADDR
command is followed by one byte, which is the short address of the device, the host wants to select for further
communication.
8.4.3.3 Function Phase
Figure 8-22, Figure 8-23 and Figure 8-24 show the function phase that follows the address phase. The host can
present different functions during this phase, which is followed by either the host sending data to the device,
reading device data, or starting a temperature conversion. Some of the functions can be broadcast to all the
devices on the bus using SKIPADDR or OVD SKIPADDR. Read functions must always be unicast with a device

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selected during the address phase using MATCHADDR, FLEXADDR or OVD MATCHADDR. For cases, where
there is a single device on the bus, the device address selection can be skipped.

No No No No
Function = 44h Function = 4Eh (WRITE Function = 48h (COPY Function = BEh (READ
Host Sends Function (CONVERT TEMP)? SCRATCHPAD-1)? SCRATCHPAD-1)? SCRATCHPAD-1)?

Yes Yes Yes Yes

TMP18xx Sends
Host Sends Host waits for EEPROM
Host waits for conversion Scratchpad Byte starting
DEVICE_CONFIG1 Byte programming time. Line
time. Line held IDLE at Byte-0 (LSB First)
held IDLE

Host Sends
DEVICE_CONFIG2 Byte Yes
Host Sent Reset?

Host Sends SHORT_ADDR No

Byte

No Have first 8 bytes

Host Sends been read?
TEMP_ALERT_LOW LSB
Byte
Yes
Host Sends
TEMP_ALERT_LOW MSB TMP18xx Sends CRC Byte
Byte

Host Sends
TMP18xx Sends
TEMP_ALERT_HIGH LSB
Scratchpad Byte starting
Byte
at Byte-8 (LSB First)

Host Sends
TEMP_ALERT_HIGH MSB
Yes
Byte
Host Sent Reset?

Host Sends
TEMP_OFFSET_LSB Byte No

No Have last 8 bytes

Host Sends been read?
TEMP_OFFSET_MSB Byte

Yes

TMP18xx Sends CRC Byte TMP18xx Sends CRC Byte

Back to Start

Figure 8-22. Function Phase Flowchart for Register Space

8.4.3.3.1 CONVERTTEMP (44h)

The function is issued by the host when the host wants the temperature sensors on the bus to perform a
one-shot temperature conversion.
When the device is bus powered, the host must keep the bus idle for the duration of the active temperature
conversion. The active temperature conversion time is dependent on the conversion mode. After temperature
conversion has completed, the result is updated in temperature result LSB and temperature result MSB and
status registers.
When automatic temperature conversion mode is enabled in the device configuration-1 register, the command is
ignored.

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8.4.3.3.2 WRITE SCRATCHPAD-1 (4Eh)

The function is issued by the host to write the functional registers for the temperature sensor. Following the
function byte, the host transmits the device configuration registers, short address register, temperature alert
low limit registers, temperature alert high limit registers and temperature offset registers. After sending the 9
bytes, the device shall transmit the CRC computed on the 9 bytes and send the CRC back to the host for quick
verification of data integrity.
Additionally, the host can issue a bus reset at any time during the transfer, though the same can be done only at
byte boundary to verify that there is no register corrupted due to incomplete transfer.
When the FLEX_ADDR_MODE bits are updated as a non-zero value, the host must hold off on any
communication to keep the bus in idle state for either tRESDET or tDELAY, as per the requested flex mode, to allow
the device to decode and update the short address. Also when the FLEX_ADDR_MODE bits have a non-zero
value, the byte for short address register shall not be updated in the register scratchpad, for any subsequent
write scratchpad-1 operations, to avoid the overwrite of the decoded short address.

Note
When updating the OD_EN and/or LOCK_EN bit in the device configuration-2 register, the host
controller must send the 9 bytes and wait for the CRC transmission before the change of device speed
or write protection of the register scratchpad can take effect. If the host terminates the transfer before
the complete CRC transmission, then any update to OD_EN and/or LOCK_EN shall not take effect.

8.4.3.3.3 READ SCRATCHPAD-1 (BEh)

The function is issued by the host to read the temperature result, status bits, and functional registers from the
register scratchpad. The selected device transmits the first 8 bytes of the register scratchpad followed by CRC of
the 8 bytes. If the host wants to continue the read operation, the host receives the next 8 bytes along with CRC
for the last 8 bytes. The host can terminate the function at any point by issuing a bus reset.
8.4.3.3.4 COPY SCRATCHPAD-1 (48h)
The function is issued by the host to copy the scratchpad-1 registers to the EEPROM configuration memory. As
shown in Figure 8-22, the temperature alert registers, configuration register, short address register, temperature
offset and IO pin configuration registers are stored in the configuration EEPROM. There are 9 bytes being

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copied from the register space to the NVM, therefore the host must hold the bus in idle state for twice the
EEPROM programming time before the host performs the next access.

No No No No
Func
on = 0Fh (WRITE Func on = 55h (COPY Funcon = AAh (READ Funcon = F0h (READ
SCRATCHPAD-2)? SCRATCHPAD-2)? SCRATCHPAD-2)? EEPROM)?

Yes Yes Yes Yes

Host Sends EEPROM Host sends A5h to commit Host Sends EEPROM Host Sends EEPROM
Address High Byte Scratchpad-2 to EEPROM Address High Byte Address High Byte

Host Sends EEPROM Host Sends EEPROM Host Sends EEPROM

Host waits for tPROG
Address Low Byte Address Low Byte Address Low Byte

Host Sends 8 Data Bytes TMP18xx Sends Data

Host waits for tREADIDLE
(LSB First) Bytes (LSB First)

Yes TMP18xx Sends Data

Host Sent Reset?
Bytes (LSB First)

No
Yes
No Host Sent Reset?
Has 8 bytes been
read?
No
Yes
No
Have 8 bytes
TMP18xx Sends CRC Byte TMP18xx Sends CRC Byte been read?

Yes

Back to Start

Figure 8-23. Function Phase Flowchart for Memory Access

8.4.3.3.5 WRITE SCRATCHPAD-2 (0Fh)

The function is issued by the host to prepare data write to the EEPROM using memory scratchpad.
Figure 8-23 shows that the host first sends 2 bytes for the EEPROM address, followed by 8 data bytes. On
receiving the 8 data bytes, the device computes the CRC for total of 10 bytes of address and data received
from the host for data integrity check. The function only copies the data to the memory scratchpad, to enable the
host to change data, before the final EEPROM erase and program. Additionally, the host can use the memory
scratchpad as a 8-byte volatile buffer.
The device does not support byte wise access for EEPROM. All access to the scratchpad are done in
increments of 8 bytes. Hence the host must send the address at the 8-byte block boundary. Figure 8-9 shows
that any attempt to write data at a non-block boundary results in data corruption for the corresponding EEPROM
page and block.
8.4.3.3.6 READ SCRATCHPAD-2 (AAh)
The function is issued by the host to read the content of the memory scratchpad.
The host first sends the 2 bytes for the EEPROM address (see Figure 8-23). If the 2 bytes of address matches
the address sent during the last WRITE SCRATCHPAD-2, the device responds by sending the 8 bytes of data
that is written to the scratchpad-2 buffer earlier. The host can send a bus reset any time during the transfer. If the
device sends all 8 bytes and no bus reset is received,the device transmits the CRC computed on the 2 byte of
address sent by the host and 8 bytes of data sent by the device to the host for data integrity check.
If there is a mismatch in the EEPROM address, the device shall go back to the start and wait for a bus reset
to restart communication, and the host shall receive '1' on the bus for any subsequent read. This mechanism

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verifies that the host can detect an address byte corruption during both WRITE SCRATCHPAD-2 and READ
SCRATCHPAD-2, as both the data bytes and CRC byte reads back as FFh.
8.4.3.3.7 COPY SCRATCHPAD-2 (55h)
The function is issued by the host to copy the contents of scratchpad-2 to the EEPROM. The EEPROM current
is higher during the erase and program, therefore the application must size the external pullup resistor to verify
that there is sufficient current drawn by the one or more devices or implement a low impedance current path
using an external FET/transistor switch parallel to the bus pullup resistor.
The host application must verify that only WRITE SCRATCHPAD-2 or READ SCRATCHPAD-2, with address of
the intended location in the user EEPROM, are issued before COPY SCRATCHPAD-2 is sent. The device stores
and uses the address sent during WRITE SCRATCHPAD-2 to identify the location in the user EEPROM where
the copy operation shall be performed. The host only needs to send one byte with A5h to initiate the copy of
the memory content from scratchpad-2 to the user EEPROM, at the address location already specified, when
performing the commit operation. The host must hold the bus in idle state for the EEPROM programming time
before starting any new access on the bus.
8.4.3.3.8 READ EEPROM (F0h)
The function is issued by the host to read the EEPROM memory directly.
The host sends 2 bytes for the address of the EEPROM location, that the host wants to read. The device then
sends the data bytes starting from that location until the internal address pointer does not reach the end of
the EEPROM or host does not issue a bus reset. If the internal address pointer reaches end of the EEPROM
location, the device shall send 1s on the bus. After sending the 2 bytes for the address of the EEPROM location
to access, and when moving between block boundary, the host must idle the bus for tIDLE as specified in the
EEPROM characteristics. Additionally, there is no CRC provided in the response from the device during the
READ EEPROM function.
The device does not support byte wise access for EEPROM. All access to the memory is done in increments
of 8 bytes. Hence the host must send the address at the 8-byte block boundary. If the address is sent for a
non-block boundary, the device shall send data from the start of the corresponding block as shown in Figure 8-9.

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No No
Func
on = F5h (GPIO Func on = A5h (GPIO
READ)? WRITE)?

Yes Yes

Host Sends GPIO

Conguraon Byte

TMP18xx Sends GPIO Host Sends Inverted GPIO

Read Register Conguraon Byte

No
Is GPIO Conguraon
TMP18xx Sends CRC Byte Byte transmission OK?

Yes

TMP18xx Sends OK Code TMP18xx Sends Fail Code

No AAh FFh
Host Sent Reset

Yes

Back to Start

Figure 8-24. Function Phase Flowchart for IO Access

8.4.3.3.9 GPIO WRITE (A5h)

The function is issued by the host to configure and read the GPIO.
The host sends the IO configuration byte, followed by the inverted IO configuration byte value. This action
enables the device to check for bit error due to bus noise. If errors are detected, then the device transmits a fail
code of FFh to the host for the host to retry. If no errors are detected, then the device transmits the success code
of AAh.
8.4.3.3.10 GPIO READ (F5h)
The function is issued by the host to read the GPIO.
After issuing the function, the device sends a byte which has the corresponding IO status, followed by the CRC
for the IO status byte. The host can repeat the sequence to implement a polling loop.
8.4.4 NVM Operations
The TMP1827 device follows a common procedure for programming of keys, programming user data and
enabling the memory protection for user data and keys.
8.4.4.1 Programming User Data
Programming of user data to the memory use the functions WRITE SCRATCHPAD-2, READ SCRATCHPAD-2
and COPY SCRATCHPAD-2 as described earlier. The application must use the address in the provided
functional memory map to write user data to the device.

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1. Host issues a bus reset, then waits for the response and sends the address command for the specific
device.
2. Host issues a WRITE SCRATCHPAD-2 with the address as per the functional memory map and the 8 bytes
of data and 1 byte of CRC to verify the transfer.
3. Host issues a bus reset, then waits for the response and sends the address command for the specific
device.
4. Host issues a READ SCARTCHPAD-2 with the address as per the functional memory map, then reads the 8
bytes of data and 1 byte of CRC to verify that the data are the same as what is written in the earlier step.
5. Host issues a bus reset, then waits for the response and sends the address command for the specific
device.
6. Host issues a COPY SCRATCHPAD-2 with the data bytes as A5h to commit the data to user EEPROM.
8.4.4.2 Register and Memory Protection
The TMP1827 provides user configurable protection for both the scratchpad-1 registers and the memory region
as described below.
8.4.4.2.1 Scratchpad-1 Register Protection
The device provides for a one-time write protection for the entire register map. All the writable registers, except
for IO configuration, can be write-protected. To enable the write protection permanently, the host controller must
set LOCK_EN bit in the device configuration-2 register, then copy the register to the configuration EEPROM.
When the configuration EEPROM is programmed, the change is permanent and irreversible.
Additionally, the device provides temporary write protection mechanism. If the LOCK_EN bit is not committed
to configuration EEPROM, the device shall prevent any write to the register scratchpad-1 region, except the IO
configuration register as long as power is applied. If the device goes through a POR, then the LOCK_EN bit shall
be cleared to allow the host to update the register scratchpad-1.
8.4.4.2.2 User Memory Protection
For additional details on user memory protection, refer to the TMP1827 Security Programming Guide.

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8.5 Programming
The TMP1827 has multiple methods in which an application can access the device functions for temperature
conversion and EEPROM programming. When accessing multiple device the MATCHADDR command along
with the 64-bit device address must be used. If the short address has been programmed uniquely, then the host
can use the FLEXADDR command along with the 8-bit short address.
The sections below describe the sequences that must be followed to access the device functions properly.
8.5.1 Single Device Temperature Conversion and Read
Table 8-5 shows the program flow that the host MCU must execute for temperature conversion and subsequent
read of the temperature result. As the temperature results are the first two bytes of the register scratchpad-1, the
host can optionally stop the read after the device transmits the first two bytes by performing a bus reset.
Table 8-5. Single Device Temperature Conversion and Read Scratchpad-1 Sequence
HOST TO DEVICE DEVICE TO HOST COMMENTS
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices
CONVERTTEMP (44h) Host sends function command to start temperature conversion
Bus idle for tDELAY + tCONV Bus is held in idle state (high) during temperature conversion
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices
READ SCRATCHPAD-1 Host sends function command to read register scratchpad-1
(BEh)
TEMP_RESULT_L Device sends temperature result LSB register
TEMP_RESULT_H Device sends temperature result MSB register
STATUS_REG (Optional read for host) Device sends status register
FFh (Optional read for host) Device sends reserved byte
CONFIG_REG1 (Optional read for host) Device sends configuration-1 register
CONFIG_REG2 (Optional read for host) Device sends configuration-2 register
SHORT_ADDR (Optional read for host) Device sends short address register
FFh (Optional read for host) Device sends reserved byte
CRC (Optional read for host) Device sends CRC on first 8 bytes
TEMP_ALERT_LOW_L (Optional read for host) Device sends temperature alert low LSB register
TEMP_ALERT_LOW_H (Optional read for host) Device sends temperature alert low MSB register
TEMP_ALERT_HIGH_L (Optional read for host) Device sends temperature alert high LSB register
TEMP_ALERT_HIGH_H (Optional read for host) Device sends temperature alert high MSB register
TEMP_OFFSET_L (Optional read for host) Device sends temperature offset LSB register
TEMP_OFFSET_H (Optional read for host) Device sends temperature offset MSB register
FFh (Optional read for host) Device sends reserved byte
FFh (Optional read for host) Device sends reserved byte
CRC (Optional read for host) Device sends CRC on last 8 bytes

8.5.2 Multiple Device Temperature Conversion and Read

Table 8-6 shows the program flow that the host MCU must execute for temperature conversion and subsequent
read of the temperature result for multiple devices. The host must use the MATCHADDR command or the
FLEXADDR command to address each device on the bus, because the devices do not arbitrate on a read
function.

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Table 8-6. Multiple Device Temperature Conversion and Read Scratchpad-1 Sequence
HOST TO DEVICE DEVICE TO HOST COMMENTS
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all device(s)
CONVERTTEMP (44h) Host sends function command to start temperature conversion
Bus idle for tDELAY + tCONV Bus is held in idle state (high) during temperature conversion
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-1 ADDRESS Host sends 8-byte device address for selecting device-1
READ SCRATCHPAD-1 Host sends function command to read register scratchpad-1
(BEh)
TEMP_RESULT_L Device-1 sends temperature result LSB register
TEMP_RESULT_H Device-1 sends temperature result MSB register
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-1 ADDRESS Host sends 8 byte device address for selecting device-2
READ SCRATCHPAD-1 Host sends function command to read register scratchpad-1
(BEh)
TEMP_RESULT_L Device-2 sends temperature result LSB register
TEMP_RESULT_H Device-2 sends temperature result LSB register

8.5.3 Register Scratchpad-1 Update and Commit

Table 8-7 shows the sequence the host must execute to update the register scratchpad and commit to the
configuration EEPROM. The host must read the scratchpad to verify that the scratchpad can perform the correct
read modify write to the registers, before the scratchpad copies the same information to the configuration
EEPROM.
If the host has only one device, or if the application can guarantee no bus corruption, then the host can use
SKIPADDR command to globally update and commit the register scratchpad region with the same settings.
However once committed and locked, the host cannot update the locations anymore, and hence TI strongly
advises that the host still read the locations before running the commit operation.
Table 8-7. Register Scratchpad-1 Update and Program Configuration EEPROM
HOST TO DEVICE DEVICE TO HOST COMMENTS
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-1 ADDRESS Host sends 8 byte for selecting device-1
READ SCRATCHPAD-1 Host sends function command to read register scratchpad-1
(BEh)
16 register bytes + 2 CRC Device sends first 8 register scratchpad-1 bytes followed by CRC byte and then
bytes last 8 register scratchpad-1 bytes followed by CRC byte
Reset
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-1 ADDRESS Host sends 8 byte for selecting device-1
WRITE SCRATCHPAD-1 Host sends function command to write register scratchpad-1
(4Eh)

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Table 8-7. Register Scratchpad-1 Update and Program Configuration EEPROM (continued)
HOST TO DEVICE DEVICE TO HOST COMMENTS
9 register bytes Host sends the updated 9 register scratchpad-1 bytes
CRC Device sends CRC for the register bytes
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-1 ADDRESS Host sends 8 byte for selecting device-1
COPY SCRATCHPAD-1 Host sends function command to write copy scratchpad-1 to configuration
(48h) EEPROM
Bus idle for tPROG for Bus is held in idle state (high) during configuration EEPROM erase-program
register

8.5.4 Single Device EEPROM Programming and Verify

Table 8-8 shows the correct procedure the host must execute to update the EEPROM. When communicating
with a single device, the host can use the SKIPADDR command. However when communicating with multiple
devices, the host must use the MATCHADDR command or the FLEXADDR command to address the correct
device. The host writes to the EEPROM scratchpad first, reads the scratchpad back to verify the content before
the host copies the same information to the user EEPROM. The copy command is issued with the qualifier byte
A5h and the bus is held idle for the duration of erase and program of the EEPROM. The host shall repeat the
sequence for every 8 byte page. After the locations are programmed, the host can issue an READ EEPROM
function with the start address to read all the bytes. The device shall read back the bytes in page size and put
a CRC byte after every page to verify that the host shall be able to identify bit corruption using the CRC over a
smaller data packet.
As long as the host continues the read operation, the device shall read back 8 bytes of data followed by a CRC
byte. When the device reaches the end of the EEPROM block, the device shall return all 1's to the host.
Table 8-8. Single Device EEPROM Program and Verify Sequence
HOST TO DEVICE DEVICE TO HOST COMMENTS
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices
WRITE SCRATCHPAD-2 Host sends function command to write to scratchpad-2
(0Fh)
2-byte EEPROM Address Host sends 2-byte EEPROM address where data has to be written with MSB first
and LSB last
8-bytes data Host sends 8-byte data for the EEPROM address
CRC Device sends CRC for the address and data
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices
READ SCRATCHPAD-2 Host sends function command to read from scratchpad-2
(AAh)
2-byte EEPROM Address Host sends 2-byte EEPROM address for which data has been written with MSB
first and LSB last
8-bytes data Device sends 8 bytes from scratchpad-2
CRC Device sends CRC for the 8 bytes
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices

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Table 8-8. Single Device EEPROM Program and Verify Sequence (continued)
HOST TO DEVICE DEVICE TO HOST COMMENTS
COPY SCRATCHPAD-2 Host sends function command to copy scratchpad-2 to EEPROM
(55h)
A5h Host sends qualifier byte for EEPROM program
Bus idle for tPROG Bus is held in idle state (high) during EEPROM programming
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices
READ EEPROM (F0h) Host sends function command to read EEPROM
2-byte EEPROM Address Host sends 2-byte address to the EEPROM to read data
Bus idle for tREADIDLE Bus is held in idle state (high) during read to prefetch the data
8-bytes data Device sends 8 bytes from EEPROM address
CRC Device sends CRC for the 8 bytes
Bus idle for tREADIDLE Bus is held in idle state (high) during read to prefetch the data

8.5.5 Single Device EEPROM Page Lock Operation

When the device EEPROM is successfully programmed as shown in Table 8-8, the host shall execute the
sequence, as shown in Table 8-9, to write-protect the EEPROM page.
Table 8-9. Single Device EEPROM Page Lock Sequence
HOST TO DEVICE DEVICE TO HOST COMMENTS
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices
WRITE SCRATCHPAD-2 Host sends function command to write to scratchpad-2
(0Fh)
80h Host sends page protection byte
0Nh Host sends page number to lock
55h Host sends lock code byte
CRC Device sends CRC
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices
READ SCRATCHPAD-2 Host sends function command to read from scratchpad-2
(AAh)
80h Host sends page protection byte
0Nh Host sends page number to lock
55h Device sends lock code byte
CRC Device sends CRC
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all devices
COPY SCRATCHPAD-2 Host sends function command to lock the page
(55h)
A5h Host sends qualifier byte for EEPROM program
Bus idle for tPROG Bus is held in idle state (high) during EEPROM programming

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8.5.6 Multiple Device IO Read

Table 8-10 shows the program flow that the host MCU must execute for reading the IO from a device. The host
selects the device the host wants to communicate with and issues the GPIO READ function and the device
returns the IO read register value along with the CRC for the byte. The device at this point shall again sample
the IOs. If the host issues a bus reset during the sampling time, the device shall terminate the update process
and the device holds the last sampled value. If the host continues, then the new sampled values shall be sent
back by the device.
Table 8-10. Multiple Device GPIO Read Sequence
HOST TO DEVICE DEVICE TO HOST COMMENTS
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-1 ADDRESS Host sends 8 byte device address for selecting device-1
GPIO READ (F5h) Host sends function command for GPIO read
IO Read Register Device samples the GPIO and sends the IO read register data
CRC Device sends CRC
IO Read Register Device samples the GPIO and sends the IO read register data
CRC Device sends CRC
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-2 ADDRESS Host sends 8 byte device address for selecting device-2
GPIO READ (F5h) Host sends function command for GPIO read
IO Read Register Device samples the GPIO and sends the IO read register data
CRC Device sends CRC

8.5.7 Multiple Device IO Write

Table 8-11 shows the program flow that the host MCU must execute for configuring the IO for a device. The
host selects the device it wants to communicate with and issues the GPIO WRITE function. The host shall then
send the IO configuration register followed by an inverted value, that allows the device to check for any bus
transmission error. If the host receives a return code other than AAh, the host must terminate the transaction
by sending a bus reset and again write to the IO configuration register. If the host plans to read the device
continuously, then the host must send a bus reset and initiate a GPIO READ function.
Table 8-11. Multiple Device GPIO Write Sequence
HOST TO DEVICE DEVICE TO HOST COMMENTS
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-1 ADDRESS Host sends 8 byte device address for selecting device-1
GPIO WRITE (A5h) Host sends function command for GPIO write
IO configuration data Host sends IO configuration data
IO configuration data Host sends inverted IO configuration data
Return Code Device returns AAh for successful write and FFh for error
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-2 ADDRESS Host sends 8 byte device address for selecting device-2

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Table 8-11. Multiple Device GPIO Write Sequence (continued)

HOST TO DEVICE DEVICE TO HOST COMMENTS
GPIO WRITE (A5h) Host sends function command for GPIO write
IO configuration data Host sends IO configuration data
IO configuration data Host sends inverted IO configuration data
Return Code Device returns AAh for successful write and FFh for error

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8.6 Register Map

Table 8-12. Register Map
SCRATCHPAD-1
TYPE RESET REGISTER NAME REGISTER DESCRIPTION SECTION
BYTE
00h RO 00h TEMP_RESULT_L Temperature result LSB register Go
01h RO 00h TEMP_RESULT_H Temperature result MSB register Go
02h RO 3xh STATUS_REG Status register Go
03h RO FFh Reserved Reserved
04h R/W 70h CONFIG_REG1 Device Configuration-1 register Go
05h R/W 80h CONFIG_REG2 Device Configuration-2 register Go
06h R/W 00h SHORT_ADDR Short address register Go
07h RO FFh Reserved Reserved
08h R/W 00h TEMP_ALERT_LOW_L Temperature alert low limit LSB Go
09h R/W 00h TEMP_ALERT_LOW_H Temperature alert low limit MSB Go
0Ah R/W F0h TEMP_ALERT_HIGH_L Temperature alert high limit LSB Go
0Bh R/W 07h TEMP_ALERT_HIGH_H Temperature alert high limit MSB Go
0Ch R/W 00h TEMP_OFFSET_L Temperature offset LSB register Go
0Dh R/W 00h TEMP_OFFSET_H Temperature offset MSB register Go
0Eh RO FFh Reserved Reserved
0Fh RO FFh Reserved Reserved
— RO F0h IO_READ IO read register Go
— WO 00h IO_CONFIG IO configuration register Go

Table 8-13. Access Type Codes

Access Type Code Description
Read Type
R R Read
RC R Read
C to Clear
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W0CP W W
0C 0 to clear
P Requires privileged access
Reset or Default Value
-n Value after reset or the default
value

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8.6.1 Temperature Result LSB Register (Scratchpad-1 offset = 00h) [reset = 00h]
The register is part of the 16-bit temperature result readout that stores the least significant byte of the output
of the most recent conversion. Following a power up, the register has the value 00h until the first conversion is
complete.
Return to Register Map.
Figure 8-25. Temperature Result LSB Register
7 6 5 4 3 2 1 0
TEMP_RESULT[7:0]
R-00h

Table 8-14. Temperature Result LSB Register Field Descriptions

Bit Field Type Reset Description
7:0 TEMP_RESULT[7:0] R 00h Stores the LSB of the most recent temperature conversion
results.

8.6.2 Temperature Result MSB Register (Scratchpad-1 offset = 01h) [reset = 00h]
The register is part of the 16-bit temperature result readout that stores the most significant byte of the output
of the most recent conversion. Following a power up, the register has the value 00h until the first conversion is
complete.
Return to Register Map.
Figure 8-26. Temperature Result MSB Register
7 6 5 4 3 2 1 0
TEMP_RESULT[15:8]
R-00h

Table 8-15. Temperature Result MSB Register Field Descriptions

Bit Field Type Reset Description
7:0 TEMP_RESULT[15:8] R 00h Stores the MSB of the most recent temperature conversion
results.

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8.6.3 Status Register (Scratchpad-1 offset = 02h) [reset = 3Ch]

This register provides status of the alert flags, data ready, power mode, arbitration completion, and device lock.
The lock flag is set after the device configuration EEPROM is locked by the application. The arbitration done
flag is set after the device successfully sends the device address and is cleared only when the ARB_MODE bits
in the configuration register are cleared. The power mode status flag value is decided based on the powering
technique used for the device detected at power up and updated during every bus reset.
The alert flags are set after the most recent conversion results are available and cleared when the status register
is read by the host application. In alert mode, the alert flag when set, cannot be cleared by the device even if the
result of the last conversion is between the alert limits.
The data ready flag is set after a conversion is completed. The flag is automatically cleared when the host
controller reads the status register.
Return to Register Map.
Figure 8-27. Status Register
7 6 5 4 3 2 1 0
ALERT_HIGH ALERT_LOW Reserved DATA_READY POWER_MOD ARB_DONE LOCK_STATUS
E
RC-0b RC-0b R-11b RC-0b R-xb R-0b R-0b

Table 8-16. Status Register Field Description

Bit Field Type Reset Description
7 ALERT_HIGH R/RC 0b Alert high status flag
0b = Last temperature conversion result is less than alert high
limit
1b = Last temperature conversion result is more than or equal to
alert high limit
Alert high status flag is available on the IO2 pin when the pin is
configured for alert function

6 ALERT_LOW R/RC 0b Alert low status flag

0b = Last temperature conversion result is more than alert low
limit
1b = Last temperature conversion result is less than or equal to
alert low limit
Alert low status flag is available on the IO2 pin when the pin is
configured for alert function
5:4 Reserved R 11b Reserved
3 DATA_VALD RC 0b Data valid status flag
0b = No update in temperature result register
1b = Temperature result register updated after conversion
The data valid flag is automatically cleared when the host
controller reads the status register
2 POWER_MODE R xb Device power mode flag.
0b = VDD powered mode
1b = Bus powered mode
1 ARB_DONE R 0b Arbitration complete flag
0b = Arbitration is not complete or not enabled
1b = Arbitration is complete
0 LOCK_STATUS R 0b Lock status flag.
0b = Device configuration registers can be updated
1b = Device configuration registers cannot be updated

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8.6.4 Device Configuration-1 Register (Scratchpad-1 offset = 04h) [reset = 70h]

Use this register to configure the device functions like temperature data format, alert mode, and averaging
averaging, and conversion type (one-shot, auto and stacked conversion in bus powered mode and one-shot
or continuous conversion in VDD powered mode). The host can store the updated setting to the configuration
EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register setting is
automatically restored from the configuration EEPROM.
Return to Register Map.
Figure 8-28. Device Configuration-1 Register
7 6 5 4 3 2 1 0
TEMP_FMT Reserved CONV_TIME_S ALERT_MODE AVG_SEL CONV_MODE_SEL[2:0]
EL
RW-0b RW-1b RW-1b RW-1b RW-0b RW-000b

Table 8-17. Device Configuration-1 Register Field Descriptions

Bit Field Type Reset Description
7 TEMP_FMT RW 0b Selects the temperature format.
0b = 12-bit legacy format
1b = 16-bit high precision format
6 Reserved RW 1b Reserved. Host must always write this bit as 1b.
5 CONV_TIME_SEL RW 1b Selects the ADC conversion time
0b = 3 ms /
1b = 5.5 ms
4 ALERT_MODE RW 1b Alert pin function only available in VDD powered mode
0b = Alert pin works in Alert Mode
1b = Alert pin works in Comparator Mode
3 AVG_SEL RW 0b Conversion averaging selection
0b = No averaging
1b = Averaging of 8 back-to-back conversions
2:0 CONV_MODE_SEL[2:0] RW 000b Conversion mode selection bits.
When device is in bus powered mode:
000b = Default one shot conversion mode using CONVERT
TEMP function
001b = Stacked conversion mode is enabled. When enabled,
the short address is used to stagger the actual conversion start
with respect to the conversion request.
010b = Auto temperature conversion mode is enabled
011b - 111b = Reserved. Device behavior is unspecified.
When device is in VDD powered mode:
000b = Default one shot conversion mode using CONVERT
TEMP function
001b = One conversion every 8 seconds
010b = One conversion every 4 seconds
011b = One conversion every 2 seconds
100b = One conversion every 1 second
101b = One conversion every 0.5 second
110b = One conversion every 0.25 second
111b = One conversion every 0.125 second

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8.6.5 Device Configuration-2 Register (Scratchpad-1 offset = 05h) [reset = 80h]

This register is used to configure the overdrive enable, flexible address mode, arbitration mode during address
discovery, and the hysteresis for alert status. The register can be used to lock the writable registers for the
device. All register bits except FLEX_ADDR_MODE can be stored in the configuration EEPROM using the
COPY SCRATCHPAD-1 function command and restored at power-on reset.

Note
1. When setting the lock enable bits, the application must send all the scratchpad-1 data bytes and
read the CRC from the device before the change of overdrive bit takes effect.
2. When FLEX_ADDR_MODE is selected to decode resistor or IO pins, the bus must be placed in
the idle state after the device configuration-2 register byte is transmitted for tRESDET.

Return to Register Map.

Figure 8-29. Device Configuration-2 Register
7 6 5 4 3 2 1 0
OD_EN FLEX_ADDR_MODE[1:0] ARB_MODE[1:0] HYSTERESIS[1:0] LOCK_EN
RO-1b RW-00b RW-00b RW-00b RW-0b

Table 8-18. Device Configuration-2 Register Field Description

Bit Field Type Reset Description
7 OD_EN RO 1b Overdrive mode enable
0b = Overdrive speed is disabled
1b = Overdrive speed is enabled
The bit when set cannot be cleared by host write and
automatically is cleared only by a standard speed reset signal.
6:5 FLEX_ADDR_MODE[1:0] RW 00b Flexible address mode selection.
00b = Short address register is updated by host
01b = Short address register is updated by IO pin decode
10b = Short address register is updated by Resistor decode
11b = Short address register is updated by combined IO and
resistor address decode
Flexible address mode selection takes effect only when there is
a change detected in the bit setting.
4:3 ARB_MODE[1:0] RW 00b Arbitration mode
00b = Arbitration by device is disabled
01b = Reserved
10bh = Arbitration by device is enabled in software compatible
mode
11b = Fast Arbitration mode is enabled
The arbitration feature is applicable only when address
command is SEARCHADDR. Other commands and functions
are not affected by the ARB_MODE bit.
2:1 HYSTERESIS[1:0] RW 00b Alert hysteresis selection
00b = 5 °C hysteresis
01b = 10°C hysteresis
10b = 15°C hysteresis
11b = 20°C hysteresis
0 LOCK_EN RW 0b Register protection enable bit
0b = The register protection is disabled
1b = The register protection is enabled.
When set, the bit cannot be cleared by writing to the
scratchpad-1 to unlock the register protection. The feature when
enabled, prevents application write to the temperature offset,
temperature alert low, temperature alert high, short address and
device configuration registers.
See Note-1 above.

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8.6.6 Short Address Register (Scratchpad-1 offset = 06h) [reset = 00h]

The register is used to program the short address for the device. The host can store the updated setting to the
configuration EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register
setting is automatically restored from the configuration EEPROM. As described in Flexible Device Address,
the specific short address decoded value is overlaid on the non-volatile memory content restored to the short
address register after decoding.
The short address register can be updated by the host when the FLEX_ADDR_MODE bits have the value '00b'.
Any write to register when the FLEX_ADDR_MODE bits are not '00b' shall be ignored by the device.
Return to Register Map.
Figure 8-30. Short Address Register
7 6 5 4 3 2 1 0
SHORT_ADDRESS[7:0]
RW-00h

Table 8-19. Short Address Register Field Descriptions

Bit Field Type Reset Description
7:0 SHORT_ADDRESS[7:0] RW 00h Stores the short address for the device which can be used to
access the device without sending the 64-bit Unique Device
Address. The short address is also used during stacked
conversion mode to stagger the active conversion.

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8.6.7 Temperature Alert Low LSB Register (Scratchpad-1 offset = 08h) [reset = 00h]
This register provides the LSB for the low temperature alert threshold to compare with the latest temperature
conversion result. The register on the first power up has the alert threshold set in legacy format. If there is
a change of format, then the application must update the register in the new format. If the latest temperature
conversion result is less than the threshold set, then the device shall update the alert low status flag in the status
register, respond with the status bit flagged for an alert during the ALERTSEARCH command, and set the alert
pin low if the device is in VDD powered mode.
The factory state format for the register is legacy mode. The host can store the updated setting to the
configuration EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register
setting is automatically restored from the configuration EEPROM.
Return to Register Map.
Figure 8-31. Temperature Alert Low LSB Register
7 6 5 4 3 2 1 0
ALERT_LOW[7:0]
RW-00h

Table 8-20. Temperature Alert Low LSB Register Field Descriptions

Bit Field Type Reset Description
7:0 ALERT_LOW[7:0] RW 00h Stores the LSB of the alert low limit for comparison with the last
temperature conversion result

8.6.8 Temperature Alert Low MSB Register (Scratchpad-1 offset = 09h) [reset = 00h]
This register provides the MSB for the low temperature alert threshold to compare with the latest temperature
conversion result. The register on the first power up has the alert threshold set in legacy format. If there is
a change of format, then the application must update the register in the new format. If the latest temperature
conversion result is less than the threshold set, then the device shall update the alert low status flag in the status
register, respond with the status bit flagged for an alert during the ALERTSEARCH command, and set the alert
pin low if the device is in VDD powered mode.
The factory state format for the register is legacy mode. The host can store the updated setting to the
configuration EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register
setting is automatically restored from the configuration EEPROM.
Return to Register Map.
Table 8-21. Temperature Alert Low MSB Register
7 6 5 4 3 2 1 0
ALERT_LOW[15:8]
RW-00h

Table 8-22. Temperature Alert Low MSB Register Field Description

Bit Field Type Reset Description
7:0 ALERT_LOW[15:8] RW 00h Stores the MSB of the alert low limit for comparison with the last
temperature conversion result

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8.6.9 Temperature Alert High LSB Register (Scratchpad-1 offset = 0Ah) [reset = F0h]
This register provides the LSB for the high temperature alert threshold to compare with the latest temperature
conversion result. The register on the first power up has the alert threshold set in legacy format. If there is
a change of format, then the application must update the register in the new format. If the latest temperature
conversion result is more than the threshold set, then the device shall update the alert high status flag in the
status register, respond with the status bit flagged for an alert during the ALERTSEARCH command, and set the
alert pin low if the device is in VDD powered mode.
The factory state format for the register is legacy mode. The host can store the updated setting to the
configuration EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register
setting is automatically restored from the configuration EEPROM.
Return to Register Map.
Figure 8-32. Temperature Alert High LSB Register
7 6 5 4 3 2 1 0
ALERT_HIGH[7:0]
RW-F0h

Table 8-23. Temperature Alert High LSB Register Field Descriptions

Bit Field Type Reset Description
7:0 ALERT_HIGH[7:0] RW F0h Stores the LSB of the alert high limit for comparison with the last
temperature conversion result

8.6.10 Temperature Alert High MSB Register (Scratchpad-1 offset = 0Bh) [reset = 07h]
This register provides the MSB for the high temperature alert threshold to compare with the latest temperature
conversion result. The register on the first power up has the alert threshold set in legacy format. If there is
a change of format, then the application must update the register in the new format. If the latest temperature
conversion result is more than the threshold set, then the device shall update the alert high status flag in the
status register, respond with the status bit flagged for an alert during the ALERTSEARCH command, and set the
alert pin low if the device is in VDD powered mode.
The factory state format for the register is legacy mode. The host can store the updated setting to the
configuration EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register
setting is automatically restored from the configuration EEPROM.
Return to Register Map.

Figure 8-33. Temperature Alert High MSB Register

7 6 5 4 3 2 1 0
ALERT_HIGH[15:8]
RW-07h

Table 8-24. Temperature Alert High MSB Register Field Description

Bit Field Type Reset Description
7:0 ALERT_HIGH[15:8] RW 07h Stores the MSB of the alert high limit for comparison with the
last temperature conversion result

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8.6.11 Temperature Offset LSB Register (Scratchpad-1 offset = 0Ch) [reset = 00h]
The register is used to store the LSB of the offset calibration for the temperature sensor. The register on
the first power up has the temperature offset set in legacy format. If there is a change of format, then
the application must update the register in the new format. After every temperature conversion, the offset
calibration is automatically applied to the temperature result, before being stored in the TEMP_RESULT_L and
TEMP_RESULT_H registers.
The factory state format for the register is legacy mode. The host can store the updated setting to the
configuration EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register
setting is automatically restored from the configuration EEPROM.
Return to Register Map.
Figure 8-34. Temperature Offset LSB Register
7 6 5 4 3 2 1 0
TEMP_OFFSET_L[7:0]
RW-00h

Table 8-25. Temperature Offset LSB Register Field Descriptions

Bit Field Type Reset Description
7:0 TEMP_OFFSET_L[7:0] RW 00h Stores the offset correction LSB for the temperature result

8.6.12 Temperature Offset MSB Register (Scratchpad-1 offset = 0Dh) [reset = 00h]
The register is used to store the MSB of the offset calibration for the temperature sensor. The register on
the first power up has the temperature offset set in legacy format. If there is a change of format, then
the application must update the register in the new format. After every temperature conversion, the offset
calibration is automatically applied to the temperature result, before being stored in the TEMP_RESULT_L and
TEMP_RESULT_H registers and compared with limits registers.
The factory state format for the register is legacy mode. The host can store the updated setting to the
configuration EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register
setting is automatically restored from the configuration EEPROM.
Return to Register Map.
Figure 8-35. Temperature Offset MSB Register
7 6 5 4 3 2 1 0
TEMP_OFFSET_H[15:8]
RW-00h

Table 8-26. Temperature Offset MSB Register Field Descriptions

Bit Field Type Reset Description
7:0 TEMP_OFFSET_H[15:8] RW 00h Stores the offset correction MSB for the temperature result

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8.6.13 IO Read Register [reset = F0h]

The register is used to read the state of the IO0 to IO3 pin. The register values are updated when the GPIO
READ function is issued by the host. When IO2 is configured to function as an alert pin, the pin provides a status
of the alert pin.
Return to Register Map.
Figure 8-36. IO Read Register
7 6 5 4 3 2 1 0
nIO3_STATE nIO2_STATE nIO1_STATE nIO0_STATE IO3_STATE IO2_STATE IO1_STATE IO0_STATE
R-1b R-1b R-1b R-1b R-0b R-0b R-0b R-0b

Table 8-27. IO Read Register Field Descriptions

Bit Field Type Reset Description
7 nIO3_STATE R 1b Read inverted value of the IO3 pin when configured as a digital
input or output
6 nIO2_STATE R 1b Read inverted value of the IO2 pin when configured as a digital
input or output
5 nIO1_STATE R 1b Read inverted value of the IO1 pin when configured as a digital
input or output
4 nIO0_STATE R 1b Read inverted value of the IO0 pin when configured as a digital
input or output
3 IO3_STATE R 0b Read value of the IO3 pin when configured as a digital input or
output
2 IO2_STATE R 0b Read value of the IO2 pin when configured as a digital input or
output
1 IO1_STATE R 0b Read value of the IO1 pin when configured as a digital input or
output
0 IO0_STATE R 0b Read value of the IO0 pin when configured as a digital input or
output

8.6.14 IO Configuration Register [reset = 00h]

The register is used to select the IO function for the pins marked IO0-IO3 on the device. When selected to
function as a digital open-drain output, the pin shall be able to drive a 0 or 1 externally for controlling open
drain output on IO0 to IO3 pin. In bus powered mode, IOs tied to SDQ and used for short address must not be
configured as output as this can cause the SDQ line to be driven low. TI strongly recommends to use a 20 KΩ
resistor between IO pins and SDQ.
Return to Register Map.
Figure 8-37. IO Configuration Register
7 6 5 4 3 2 1 0
IO3_SEL[1:0] IO2_SEL[1:0] IO1_SEL[1:0] IO0_SEL[1:0]
WO-00b WO-00b WO-00b WO-00b

Table 8-28. IO Configuration Register Field Descriptions

Bit Field Type Reset Description
7:6 IO3_SEL[1:0] WO 00b Selects the function of the IO
00b = IO3 is configured as input buffer and can be read
01b = Reserved
10b = IO3 is configured as an output in open drain mode and
the IO is driven as '0'
11b = IO3 is configured as an output in open drain mode and the
IO is driven as Hi-Z

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Table 8-28. IO Configuration Register Field Descriptions (continued)

Bit Field Type Reset Description
5:4 IO2_SEL[1:0] WO 00b Selects the function of the IO
00b = IO2 is configured as input buffer and can be read
01b = IO2 is configured as an open drain active low alert
10b = IO2 is configured as an output in open drain mode and
the IO is driven as '0'
11b = IO2 is configured as an output in open drain mode and the
IO is driven as Hi-Z
3:2 IO1_SEL[1:0] WO 00b Selects the function of the IO
00b = IO1 is configured as input buffer and can be read
01b = Reserved
10b = IO1 is configured as an output in open drain mode and
the IO is driven as '0'
11b = IO1 is configured as an output in open drain mode and the
IO is driven as Hi-Z
1:0 IO0_SEL[1:0] WO 00b Selects the function of the IO
00b = IO0 is configured as input buffer and can be read
01b = Reserved
10b = IO0 is configured as an output in open drain mode and
the IO is driven as '0'
11b = IO0 is configured as an output in open drain mode and the
IO is driven as Hi-Z

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The TMP1827 can operate as a 1-Wire® half duplex bus, either in supply or bus powered mode. The TMP1827
features a thermal sensor with an integrated 2Kb user EEPROM and SHA-256-HMAC authentication for
applications requiring identification with lesser number of components due to space constraints. The device
also features an integrated CRC that can be used for verifying data integrity during communication.
The bus powered mode is designed for applications working without a dedicated power supply pin and can
reduce cabling costs. As the device current consumption during thermal conversion and EEPROM operations
is low, the device can not require a low impedance current path, thereby reducing the need for additional FET
or load switch and current limiting resistor to bypass the bus pullup resistor. The pullup resistor used during
bus powered mode must be correctly sized to verify that the sufficient current can be supplied during a thermal
conversion and EEPROM operation, and input pin voltage does not fall below the VIH(MIN).
Additionally, if the host must reset the device when operating in bus powered mode, the host must pull the
communication line low for at least 50 ms. This allows the internal capacitor of the device to discharge and
prepare the device for power-on reset.
9.2 Typical Applications

9.2.1 Bus Powered Application

5.0 V

3.0 kΩ VDD

MCU GPIO SDQ TMP1827 Temperature

Source
GND GND

Figure 9-1. Bus Powered Application

9.2.1.1 Design Requirements

For this design example, use the parameters listed below:
Table 9-1. Design Parameters
PARAMETER VALUE
Power mode Bus Powered (VDD pin is connected to GND)
Supply (VDD) 5.0 V
Pullup resistor range (RPUR) 1.2 kΩ to 3.33 kΩ

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9.2.1.2 Detailed Design Procedure

To reduce the wire count, the bus powered mode for the TMP1827 is the primary mode of operation. The VDD
pin of the device must be connected to GND and the SDQ pin of the device must be connected to the host GPIO
with a pullup resistor.
To calculate the pullup resistor range, substitute the value for VPUR, VOL(MAX), VIH(MIN) and IPU(MIN) in Equation 2
as the VPUR > 2.0 V.

5.0 – 0.4 5.0 – 4.0

< RPUR < (3)
4 × 10–3 300 × 10–6

1.15 kΩ < RPUR < 3.33 kΩ (4)

The actual value of the pullup resistor can then be adjusted based on the speed of communication and bus or
cable parasitic capacitance.
When the VDD is activated, the TMP1827 draws current through the pullup resistor to charge internal capacitors.
When the internal capacitor is charged to the pullup voltage, the host can start communication. The bus idle
state is high, which is maintained by the pullup resistor, when the host puts the GPIO in high impedance state.
The TMP1827 uses the stored charge to operate when the SDQ pin is low and measures the low period to
decode bus reset, logic high and logic low sent by the host. Similarly, when the host reads data from the
TMP1827, the device changes the state of the bus from high to low and releases the bus. Depending on whether
the device has to send a logic low or logic high, the device shall either hold the bus low or release the bus
immediately.
9.2.2 Supply Powered Application
1.8 V

0.1 µF

5.1 kΩ VDD

MCU GPIO SDQ TMP1827 Temperature

Source
GND GND

Figure 9-2. Supply Powered Application

9.2.2.1 Design Requirements

For this design example, use the parameters listed below:
Table 9-2. Design Parameters
PARAMETER VALUE
Power mode VDD Powered
Supply (VDD) 1.8 V
Pullup resistor (RPUR) 5.1 kΩ

9.2.2.2 Detailed Design Procedure

The supply powered mode uses the VDD pin connected to the same supply rail as the host and pullup resistor. TI
recommends to place a 0.1-µF bypass capacitor close to the VDD pin of the TMP1827.

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The pullup resistor value of 5.1 kΩ is large enough to provide proper communication with standard speed and
avoid VOL violation when the device is sending data to the host. The user can change the value based on the
total bus load and application operating requirements.
The communication protocol for supply powered mode is same as that for bus powered mode, which allows the
entire software stack to be reused. This mode of operation is useful for onboard thermal sensing applications as
this mode provides for continuous conversion and alert function.
9.2.3 UART Interface for Communication
3.3 V

2.2 kΩ VDD
SN74LVC1G07
MCU UART.TX SDQ TMP1827 Temperature
Source
GND UART.RX GND
Op
onal series
resistor
Figure 9-3. Using UART to Interface TMP1827

9.2.3.1 Design Requirements

For this design example, use the parameters listed below:
Table 9-3. Design Parameters
PARAMETER VALUE
Power Mode Bus powered
Supply (VDD) 3.3 V
Pullup resistor range (RPUR) 750 Ω to 2.2 kΩ

9.2.3.2 Detailed Design Procedure

If using GPIO for communication is not possible due to any reason, using the UART peripheral that is available
on most host controllers to interface with the TMP1827 is also possible. UART is a push-pull full duplex bus and
to interface with TMP1827, the devcie requires a buffer with open-drain driver like the SN74LVC1G07.
The input of the buffer is connected to the UART transmit pin and the output of the buffer is connected to the
SDQ pin on the TMP1827. The output of the buffer is also connected to the UART receive pin on the host. As
the output is open-drain, the output requires a pullup resistor which can be calculated in Equation 2 as VPUR >
2.0 V. Substituting the value for VPUR = 3.3 V, V OL(MAX) = 0.4 V, V IH(MIN) = 2.64 V and IPU(MIN) = 300 µA, the RPUR
value selected must be greater than 725 Ω and less than 2.2 kΩ.
In software, the application must adjust the baud rate so that the application can send bus reset to the device by
sending 00h. The start bit of the UART frame which is always 0, provides the required falling edge for data sent
to the TMP1827. When sending a logic high to the device, the UART shall send FFh to the TMP1827 and, when
sending a logic low to the device, the UART shall send C0h. As UART is a full duplex bus, the host must flush
the receive buffers during a transmit operation.
When receiving data from the TMP1827, the host shall send FFh and the device when transmitting a logic high
detects and release the bus, while when transmitting a logic low detects and hold the bus low. As a result, the
host shall receive a FFh for a logic high and F0h for a logic low depending on the baud rate configured.

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9.3 Power Supply Recommendations

The TMP1827 operates with a power supply in the range of 1.7 V to 5.5 V in both VDD powered and bus
powered modes. When operating in VDD powered mode, a power-supply bypass capacitor is required for
precision and stability. Place this power-supply bypass capacitor as close to the supply and ground pins of
the device as possible. A typical value for this supply bypass capacitor is 0.1 µF. Applications with noisy or
high-impedance power supplies can require a bigger bypass capacitor to reject power-supply noise.
In bus powered mode, the VDD pin must be connected to ground. The internal capacitor in the device is sufficient
to provide power during bus communication. The internal capacitor is recharged through the external pullup
resistor during the recovery period. In cases where there is a long bus length or at higher temperatures, the host
can need to provide additional time for bus recovery or to use the overdrive speed in which the part uses the
internal capacitor charge less.
When using IO pins to control external circuits, take care that currents to these pins do not heat the part and
offset temperature measurements.
9.4 Layout
9.4.1 Layout Guidelines
Place the power-supply bypass capacitor as close as possible to the supply and ground pins when in supply
powered mode (see Figure 9-4). The recommended value of the capacitor is 0.1 µF. The open-drain SDQ pin
requires an external pullup resistor which must not be higher than RPUR.
When in bus powered mode, only the external pullup resistor is required for the open-drain SDQ pin. As shown
in Figure 9-5, TI recommends to place a 20-KΩ pullup resistor when connecting IO to SDQ pin to avoid shorting
the SDQ to GND in case the IO is configured as an output and driven low (see Figure 9-6). The ADDR pin
resistor uses very low current to decode the short address and must be placed close to the device, if possible.
Take care to avoid leakage currents to prevent incorrect decoding.
9.4.2 Layout Example

It is a good prac ce
to have a bypass
capacitor on supply

SDQ trace routed on the bo
om layer

to simplify roung and component
placement on the top layer

Figure 9-4. VDD Powered Layout Example

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VDD pin must be connected to ground

Pull up resistor required on
to ensure device powers up in bus-
the SDQ bus to provide
powered mode and mi
gate system
power when bus is idle
EMI issues.

It is generally best
prac ce to solder the
package thermal pad
to ground.

Figure 9-5. Bus Powered Layout Example

Device short Op
onal resistor of

address of 00h 20 k
IO0,IO1,IO2,IO3
connected to GND

Device short address of 01h

IO0 connected to SDQ and
IO1,IO2,IO3 connected to GND

Figure 9-6. IO Hardware Address in Bus Powered Mode

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10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, TMP1827 EVM User's Guide
• Texas Instruments, TMP1827 Security Programming Guide
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
1-Wire® is a registered trademark of Maxim Integrated Products, Inc.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2023) to Revision B (January 2025) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated the formatting of trademarks throughout the document....................................................................... 1

Changes from Revision * (September 2022) to Revision A (May 2023) Page

• Changed data sheet status from Advanced Information to Production Data......................................................1
• Added Functional Safety information to the Features section............................................................................ 1
• Added device comparison table......................................................................................................................... 2
• Changed maximum operating temperature range for standard speed mode in footnote 2 ............................... 4
• Changed NGR package maximum accuracy for +10°C to +45°C from ±0.3°C to ±0.2°C and full range from
±1.0°C to ±0.4°C.................................................................................................................................................4
• Added accuracy specification for TMP1827N.....................................................................................................4
• Changed VIL of IO from 0.2×VS to 0.3×VS .........................................................................................................4

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• Changed VIH of IO from 0.8×VS to 0.7×VS ........................................................................................................ 4

• Changed pullup current from 300 µA to 400 µA................................................................................................. 4
• Added standby current specification for continuous conversion mode...............................................................4
• Changed tSLOT minimum in standard mode from 60 µs to tWR0L + tRC ..............................................................5
• Removed tSLOT maximum in standard mode......................................................................................................5
• Changed tSLOT minimum in overdrive mode from 11 µs to tWR0L + tRC ............................................................. 5
• Changed tRL minimum from 2 µs to 2.5 µs.........................................................................................................5
• Changed tREADIDLE from 400 µs to 560 µs......................................................................................................... 6
• Changed IDD_PROG from 214 µA to 230 µA........................................................................................................ 6
• Added typical Endurance spec for EEPROM..................................................................................................... 6
• Removed GPIO read and CRC byte from the GPIO WRITE section............................................................... 35

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TMP1827NGRR ACTIVE WSON NGR 8 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -55 to 150 T1827 Samples

TMP1827NNGRR ACTIVE WSON NGR 8 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -55 to 150 35DP Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Jan-2025

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jan-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP1827NGRR WSON NGR 8 3000 178.0 8.4 2.75 2.75 0.95 4.0 8.0 Q2
TMP1827NNGRR WSON NGR 8 3000 178.0 8.4 2.75 2.75 0.95 4.0 8.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jan-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP1827NGRR WSON NGR 8 3000 205.0 200.0 33.0
TMP1827NNGRR WSON NGR 8 3000 205.0 200.0 33.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
NGR 8 WSON - 0.8 mm max height
2.5 x 2.5, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4227146/A

www.ti.com
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