VERILOG LAB 8
FINITE STATE MACHINES
EXAMPLE 1
• This is a state machine with two states, one input, and one output. Implement
this state machine. Notice that the reset is asynchronous active-high that reset
current state to B.
Eng. Amr Al Iraqi
DESIGN 1
TESTBENCH 1
WAVEFORM 1
EXAMPLE 2
• This is a state machine with two states, two inputs, and one output. Implement
this state machine. . Notice that the reset is asynchronous active-high that reset
current state to OFF.
Eng. Amr Al Iraqi
DESIGN 2
TESTBENCH 2
WAVEFORM 2
EXAMPLE 3
• The following is the state transition
table for a state machine with one
input, one output, and four states. Use
the following state encoding:
A=2'b00, B=2'b01, C=2'b10,
D=2'b11. Implement this state
machine. . Notice that the reset is
asynchronous active-high that reset
current state to A.
Eng. Amr Al Iraqi
DESIGN 3
TESTBENCH 3
WAVEFORM 3
EXAMPLE 4
• Design an FSM-based traffic light controller for a campus
intersection with two inputs (TA, TB) indicating traffic
presence on Academic Avenue and Bravado Boulevard, and
two outputs (LA, LB) controlling the traffic lights. The system
starts with LA green and LB red on reset, keeps LA green
while TA is TRUE, transitions LA to yellow for 1 clock cycle
when TA becomes FALSE, then switches LA to red and LB to
green. Similarly, LB remains green while TB is TRUE,
transitions to yellow for 1 clock cycle when TB becomes
FALSE, then switches to red and LA to green, repeating the
cycle.
Eng. Amr Al Iraqi
STATE TRANSITION DIAGRAM
Eng. Amr Al Iraqi
DESIGN 4
TESTBENCH 4
WAVEFORM 4
EXAMPLE 5
• Amr Al Iraqi owns a robotic snail with an FSM brain. The
snail moves from left to right along a paper tape
containing a sequence of 1’s and 0’s. On each clock
cycle, the snail moves to the next bit. The snail glows
when the last two bits it crawled over are 01. Design the
FSM to compute when the snail should glow. The input in
is the bit underneath the snail’s antennae. The output out
is TRUE when the snail glows. Notice that the reset is
asynchronous active-high that reset current state to S0.
Test the circuit as the snail moves along the sequence
0100110111.
Eng. Amr Al Iraqi
STATE TRANSITION DIAGRAM
Eng. Amr Al Iraqi
DESIGN 5
TESTBENCH 5
WAVEFORM 5
TASK
• Design an FSM that detects the sequence "01010" by
transitioning through states Sreset (initial state, no bits
received), S0 (received "0"), S01 (received "01"), S010
(received "010"), S0101 (received "0101"), and S01010
(final state, sequence "01010" detected). The FSM
transitions between these states based on the input bit A
and outputs Q=1 when the sequence is detected, and
Q=0 otherwise. The machine starts in state Sreset and
updates its state with each incoming bit, following the
sequence detection pattern.
Eng. Amr Al Iraqi
