Realization of ENCODER design.
Verilog Code for 2 to 4 Encoder Circuit
RTL Code:
module encoder (input [3:0] d, output reg [1:0] y);
always @ (*)
begin
case(d)
4'b0001: y=2'b00;
4'b0010: y=2'b01;
4'b0100: y=2'b10;
4'b1000: y=2'b11;
endcase
end
endmodule
Test bench Code:
module entb;
reg [3:0] d;
wire [1:0] y;
encoder uut (. d (d),. y(y));
initial
begin
#5 $display ("input:d=%b, output:y=%b",d,y);
d=4'b0010;
#5 $display ("input:d=%b, output:y=%b",d,y);
d=4'b0100;
#5 $display ("input:d=%b, output:y=%b",d,y);
d=4'b1000;
#5 $display ("input:d=%b, output:y=%b",d,y);
end
initial
begin
#25 $finish;
end
endmodule
Result:
input:d=0001, output:y=00
input:d=0010, output:y=01
input:d=0100, output:y=10
input:d=1000, output:y=11
Stopped at time: 25 ns: File "D:/pp/entb.v" Line 43
Realization of DECODER design.
Verilog Code for 8 to 3 decoder Circuit
RTL Code:
module decode (input a,b,c, output reg [7:0] y);
always @ (*)
begin
case({a,b,c})
3'b000: y=8'b00000001;
3'b001: y=8'b00000010;
3'b010: y=8'b00000100;
3'b011: y=8'b00001000;
3'b100: y=8'b00010000;
3'b101: y=8'b00100000;
3'b110: y=8'b01000000;
3'b111: y=8'b10000000;
endcase
end
endmodule
Test bench Code:
module decodetb;
reg a;
reg b;
reg c;
wire [7:0] y;
decode uut (.a(a), .b(b), .c(c), .y(y));
initial
begin
a=0; b=0; c=0;
#5 $display("input: a=%b b=%b c=%b,output: y=%b",a,b,c,y);
a=0; b=0; c=1;
#5 $display("input: a=%b b=%b c=%b,output: y=%b",a,b,c,y);
a=0; b=1; c=0;
#5 $display("input: a=%b b=%b c=%b,output: y=%b",a,b,c,y);
a=0; b=1; c=1;
#5 $display("input: a=%b b=%b c=%b,output: y=%b",a,b,c,y);
a=1; b=0; c=0;
#5 $display("input: a=%b b=%b c=%b,output: y=%b",a,b,c,y);
a=1; b=0; c=1;
#5 $display("input: a=%b b=%b c=%b,output: y=%b",a,b,c,y);
a=1; b=1; c=0;
#5 $display("input: a=%b b=%b c=%b,output: y=%b",a,b,c,y);
a=1; b=1; c=1;
#5 $display("input: a=%b b=%b c=%b,output: y=%b",a,b,c,y);
end
endmodule
Result:
