AKGEC/IQAC/QP/03
Ajay Kumar Garg Engineering College, Ghaziabad
Department of Electronics & Communication Engg.
Stage Two Test (STT-ST1)
Course: B. Tech Semester: 1st
Session: 2024-25 Section: S-11 to S-20
Subject: Fundamentals of Electronics Engg. Sub. Code: BEC-101
Max Marks: 75 Time: 3 hour
Note: Answer all the sections.
Section-A
A. Attempt all the parts. (3x2 = 6)
1. Explain the formation of depletion layer in the diode.
2. Draw the V-I characteristics of Ideal PN Junction diode in forward & reverse bias condition.
3. Differentiate between avalanche and Zener breakdown.
Section-B
B. Attempt all the parts. (4x3 = 12)
4. Draw the output waveform of clamper circuit in Fig 1.
Fig 1.
5. Explain the working of voltage doubler using diode.
6. Explain the operation of Full wave bridge rectifier with the help of circuit diagram. Sketch input
and output waveform. Define PIV & Ripple factor
Section-C
C. Attempt all the parts. ( 7)
7. For the network of Fig.2, determine the range of RL that will result in VRL being maintained at
10 V.
Fig.2
Stage Two Test (STT-ST2)
Section-A (2*5=10)
8. Differentiate BJT and JFET
9. Calculate βdc and Icbo, if IE =5mA, Ic=4.95mA, Iceo=200μA.
10. What is CMRR?
11. Write down the characteristics of ideal and practical Op-Amp
12. Determine the output voltage of the following circuit.
Section-B (5*5=25)
13. What is Op-amp?.Calculate the output voltage V2 and V3 for a given network shown in Fig 3.
Fig 3.
14. Draw and explain the input and output characteristics of common emitter configuration.
15. Describe the construction, working and characteristics of n-channel Junction Field Effect Transistor.
16. Derive the relation between α, β and γ. Also explain all the stages with proper block diagram of Op-
amp.
17. Explain the concept of virtual ground in OP-AMP. Determine the output voltage of an op-amp for
input voltages of Vi1 = 250µV and Vi2 =190µV. The amplifier has a differential gain of Ad = 3000 and
the CMRR is 100.
Section-C (7.5*2=15)
18. Minimize F ( A, B, C , D) = M (3, 4,5, 7,9,13,14,15).D(0, 2,8) using K-Map and realize logic
circuit using NOR gates only
19. Explain:
i) Integrator circuit using Op-Amp.
ii) Unity Gain Follower using Op-Amp.
iii) Subtractor using Op-Amp.
Faculty Sign HoD Sign
