BEARYS INSTITUTE OF TECHNOLOGY

MANGALORE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

DIGITAL SYSTEM DESIGN USING VERILOG(BEC302)
(2022 Scheme)

LAB MANUAL
 EXPERIMENTS

1. To simplify the given Boolean expressions and realize using Verilog

program
2. To realize Adder/Subtractor (Full/half) circuits using Verilog data flow
description.
3. To realize 4-bit ALU using Verilog program.
4. To realize the following Code converters using Verilog Behavioral
description a) Gray to binary and vice versa
b) Binary to excess3 and vice versa
5. To realize using Verilog Behavioral description:8:1mux, 8:3encoder,
Priority encoder
6. To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,
2–bit Comparator
7. To realize using Verilog Behavioral description:
Flip-flops: a) JK type b) SR type c) T type and d) D type
8. To realize Counters-up/down (BCD and binary) using Verilog Behavioral
description.
(1). Write a verilog program to realize combinational logic gates
module logic(a,b,and1,or1,nor1,xnor1,xor1,nand1,not1);
input a,b;
output and1, or1, nor1, xnor1,xor1,nand1,not1;
assign and1 = a&b;
assign or1 = a|b;
assign xor1 = a^b;
assign nand1 = ~ (a&b);
assign nor1 = ~ (a|b);
assign xnor1 = ~ (a^b);
assign not1 = ~a;
endmodule

TRUTH TABLE:

a b and1 or1 nand1 nor1 xor1 xnor1 not1

0 0 0 0 1 1 0 1 1
0 1 0 1 1 0 1 0 1
1 0 0 1 1 0 1 0 0
1 1 1 1 0 0 0 1 0

2. a) write a verilog program to design function of Half Adder

module halfadder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum= a^b;
assign carry= a&b;
endmodule

TRUTH TABLE:
a b sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
2.b) Write a verilog program to design function of full adder
module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

TRUTH TABLE:
a b c sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

2.c) write a verilog program to design function of Half subtractor

module halfsubtractors(a,b,diff,borrow);
input a,b;
output diff,borrow;
assign diff= a^b;
assign borrow= (~a)&b;
endmodule

TRUTH TABLE:
a b diff borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
2.d) write a verilog program to design function of full subtractor
module fullsub(a,b,c,diff,borrow);
input a,b,c;
output diff,borrow;
assign diff=a^b^c;
assign borrow=((~a)&b)|((~a)&c)|(b&c);
endmodule

TRUTH TABLE:
a b c diff borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
3. Write a verilog program to design 4 bit ALU
module alu(a,b,op,y1,y2);
input [3:0] a,b;
input [2:0] op;
output [3:0] y1;
output [7:0] y2;
reg [3:0] y1;
reg [7:0] y2;
always @(a or b or op)
begin
case (op)
4'd0: y1=a+b;
4'd1: y1=a-b;
4'd2: y1=~a;
4'd3: y1=a&b;
4'd4: y1=a|b;
4'd5: y1=~(a&b);
4'd6: y1=~(a|b);
4'd7: y2= a*b;
endcase
end
endmodule

TRUTH TABLE:
op(2) op(1) op(0) y1 y2
0 0 0 a+b -
0 0 1 a-b -
0 1 0 ~a -
0 1 1 a&b -
1 0 0 a|b -
1 0 1 ~(a&b) -
1 1 0 ~(a|b) -
1 1 1 a*b
4. i) Write verilog code for 4 bit binary to gray converter

module binarytogrey(b,g)
Input [3:0]b;
Output [3:0]g;
Reg [3:0]g;
always@(b,g)
Begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule

TRUTH TABLE:
BINARY INPUT GRAY INPUT
b(3) b(2) b(1) b(0) g(3) g(2) g(1) g(0)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
ii) Write verilog code for 4 bit gray to binary converter

module graytbinary(g,b);
input [3:0]g;
output [3:0]b;
reg [3:0]b;
always@(g)
begin
b[3]=g[3];
b[2]=g[3]^g[2];
b[1]=g[3]^g[2]^g[1];
b[0]=g[3]^g[2]^g[1]^g[0];
end
endmodule

TRUTH TABLE:
GRAY INPUTS BINARY OUTPUTS
g(3) g(2) g(1) g(0) b(3) b(2) b(1) b(0)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 1
1 0 1 1 1 0 1 0
1 0 1 0 1 0 1 1
1 1 1 0 1 1 0 0
1 1 1 1 1 1 0 1
1 1 0 1 1 1 1 0
1 1 0 0 1 1 1 1
 5.i) Write verilog code for 8 to 3 encoder

module encode(din, e,dout);

input En;
input [7:0]din;
output[2:0]dout;
reg [2:0]dout;
always @ (e or din)
begin
if (e==1)
dout=3'b0;
else
case (din)
8'b00000001:dout=3'b000;
8'b00000010:dout=3'b001;
8'b00000100:dout=3'b010;
8'b00001000:dout=3'b011;
8'b00010000:dout=3'b100;
8'b00100000:dout=3'b101;
8'b01000000:dout=3'b110;
8'b10000000:dout=3'b111;
default:dout=3'b000;
endcase
end
endmodule

TRUTH TABLE:

e din(7) din(6) din(5) din(4) din(3) din(2) din(1) din(0) dout(2) dout(1) dout(0)
1 X X X X X X X X 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 0 1 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 1 1 0
0 1 0 0 0 0 0 0 0 1 1 1
 5 ii) Write verilog code for 8 to 3 encoder with priority
module prienco1(e,din,dout);
input[7:0]din;
input e;
output[2:0]dout;
reg[2:0]dout;
always@(din,e)
begin
if (e= =1)
dout=3'b000;
else if (din[0]==1)dout=3'b000;
else if(din[1]==1)dout=3'b001;
else if(din[2]==1)dout=3'b010;
else if(din[3]==1)dout=3'b011;
else if(din[4]==1)dout=3'b100;
else if(din[5]==1)dout=3'b101;
else if(din[6]==1)dout=3'b110;
else if(din[7]==1)dout=3'b111;
else
dout=3'b000;
end
endmodule

TRUTH TABLE:

e din(7) din(6) din(5) din(4) din(3) din(2) din(1) din(0) dout(2) dout(1) dout(0)

1 X X X X X X X X 0 0 0
0 1 X X X X X X X 1 1 1
0 X 1 X X X X X X 1 1 0
0 X X 1 X X X X X 1 0 1
0 X X X 1 X X X X 1 0 0
0 X X X X 1 X X X 0 1 1
0 X X X X X 1 X X 0 1 0
0 X X X X X X 1 X 0 0 1
0 X X X X X X X 1 0 0 0
 5 iii) Write verilog code for 8 to 1 multiplexer

module mux(e, din, dout,sel);

input e;
input[7:0]din;
input[2:0]sel;
output dout;
reg dout;
always@(e or din)
begin
if(e==1)
dout=1'b0;
else case(sel)
3'b000:dout=din[7];
3'b001:dout=din[6];
3'b010:dout=din[5];
3'b011:dout=din[4];
3'b100:dout=din[3];
3'b101:dout=din[2];
3'b110:dout=din[1];
3'b111:dout=din[0];
endcase
end
endmodule

TRUTH TABLE:
e sel(2) sel(1) sel(0) din(7) din(6) din(5) din(4) din(3) din(2) din(1) din(0) dout
0 0 0 0 X X X X X X X X din(0)
0 0 0 1 X X X X X X X X din(1)
0 0 1 0 X X X X X X X X din(2)
0 0 1 1 X X X X X X X X din(3)
0 1 0 0 X X X X X X X X din(4)
0 1 0 1 X X X X X X X X din(5)
0 1 1 0 X X X X X X X X din(6)
0 1 1 1 X X X X X X X X din(7)
1 X X X X X X X X X X X 0
6 i) Write a verilog program to design 1:4 demux
module demux14(din,sel,dout);
input din;
input [1:0] sel;
output [3:0] dout;
reg [3:0] dout;
always @(din,sel)
begin
dout=4’b0000;
case(sel)
2'b00: dout[0]=din;
2'b01: dout[1]=din;
2'b10: dout[2]=din;
default: dout[3]=din;
endcase
end
endmodule

TRUTH TABLE:
sel(0) sel(1) Din dout(0) dout(1) dout(2) dout(3)
0 0 1 din X X X
0 1 1 X din X X
1 0 1 X X din X
1 1 1 X X X din
6 ii)Write verilog code for 2 to 4 decoder
module decoder(din, en,dout);
input[1:0]din;
input en;
output[3:0]dout;
reg[3:0]dout;
always@(en or din)
begin
if(en= =1)
dout=4'b0001;
else
case(din)
2'b00:dout =4'b0001;
2'b01:dout= 4'b0010;
2'b10:dout= 4'b0100;
2'b11:dout= 4'b1000;
default :dout=4'b0000;
endcase
end
endmodule

TRUTH TABLE:
en din(1) din(0) dout(3) dout(2) dout(1) dout(0)
1 X X 0 0 0 0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0
6 iii)Write verilog module for 2-bit comparator
module comparator(a,b,alb,agb,aeb);
input [1:0]a,b;
output alb,agb,aeb;
reg alb,agb,aeb;
always@(a,b)
begin
if(a > b)
agb=1;
else
agb=0;
if(a==a)
aeb=1;
else
aeb=0;
if (a<b)
alb=1;
else
alb=0;
end
endmodule

TRUTH TABLE:
a(1) a(0) b(1) b(0) agb aeb alb
1 1 0 1 1 0 0
1 1 1 1 0 1 0
0 0 1 1 0 0 1
7 i)Write a verilog code for D flip-flop
module sync_dff(d,clk,reset,q);
input d,clk,reset;
output q;
reg q;
initial
q=1'b1;
always@(posedge clk)
if(~reset)
q=1'b0;
else
q=d;
endmodule

TRUTH TABLE:
clk reset d q

 0 x 0
 1 0 0
 1 1 1

7 ii) Write a verilog code for T flip-flop

module tffv(t,q,clk);
input t,clk;
output q;
reg q;
initial
q=1;
always@(posedge clk)
begin
case (t)
1'b0: q=q;
1'b1: q=~q;
endcase
end
endmodule

TRUTH TABLE:
clk t q
 0 q
 1 not q
7 iii) Write a verilog code for JK flip-flop
module jkff(clk,reset,jk,q);
input clk,reset;
input [1:0]jk;
output q;
reg q;
initial
q=1'b0;
always@(posedge clk)
begin
if(reset)
q=0;
else
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
end
endmodule

TRUTH TABLE:
Clk reset jk(1) jk(0) Q
 0 0 0 Q
 0 0 1 0
 0 1 0 1
 0 1 1 not Q
 1 x x 0
7 iv) Write a verilog code for SR flip-flop
module sr1(sr,q,qnot,clk);
input [1:0] sr;
input clk;
output q,qnot;
reg q,qnot;
initial
begin
q=0;
qnot=1;
end
always@(posedge clk)
begin
case (sr)
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=1'bz;
endcase
qnot=~q;
end
endmodule

TRUTH TABLE:
clk sr(1) sr(0) q qnot
 0 0 Q not Q

 0 1 0 1

 1 0 1 0

 1 1 Z Z
8 i) Write a verilog code for 4-bit binary counter with synchronous reset
module syncrst(clk, reset, count);
input clk;
input reset;
output [3:0] count;
reg [3:0]count;
initial
count=4'b1010;
always@(posedge clk)
begin
if (reset==1)
count=4'b0000;
else
count=count+1;
end
endmodule

TRUTH TABLE:
clk reset Count(3) Count(2) Count(1) Count(0)
 1 0 0 0 0
 0 0 0 0 1
 0 0 0 1 0
 0 0 0 1 1
 0 0 1 0 0
 0 0 1 0 1
 0 0 1 1 0
 0 0 1 1 1
 0 1 0 0 0
 0 1 0 0 1
 0 1 0 1 0
 0 1 0 1 1
 0 1 1 0 0
 0 1 1 0 1
 0 1 1 1 0
 0 1 1 1 1
8 ii) Write a verilog code for BCD counter
module bcdverilog(clk, reset, count);
input clk;
input reset;
output [3:0] count;
reg [3:0] count;
initial
begin
count=4'b1001;
end
always @(posedge clk)
begin
if(reset==1)
count=4'b0000;
else if (count==4'b1001)
count=4'b0000;
else
count=count+1;
end
endmodule

TRUTH TABLE:
clk reset Count(3) Count(2) Count(1) Count(0)
X 1 0 0 0 0
 0 0 0 0 1
 0 0 0 1 0
 0 0 0 1 1
 0 0 1 0 0
 0 0 1 0 1
 0 0 1 1 0
 0 0 1 1 1
 0 1 0 0 0
 0 1 0 0 1
 0 0 0 0 0