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Experiment 6 Verilog Decoder

DIGITAL_LOGIC_DESIGN: LAB_SHEET_DECODER_DESIGN_USING_VERILOG

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74 views2 pages

Experiment 6 Verilog Decoder

DIGITAL_LOGIC_DESIGN: LAB_SHEET_DECODER_DESIGN_USING_VERILOG

Uploaded by

fma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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East West University

Department of Electrical and Electronic Engineering

EEE 205: Digital Logic Design

Experiment – 6
Verilog modules: Decoders

1 Objective

The objective of this experiment is –

1. to use the Verilog Hardware Description Language (HDL) in the implementation


of decoder circuits.

2 Theory

Design of decoders using logic gates and combinational logic implementation using
decoders are discussed in the textbook (Brown) in section 6.2.

3 Pre-lab Work

Decoders:
1. Draw a 3-to-8 decoder using 2-to-4 decoders.

4 Lab Work

1. Implement a 2-to-4 decoder using the structural Verilog code in Quartus II


software. Verify their truth tables with vector waveforms. The required Verilog
code is given below:
module decod2(EN, A0, A1, D0, D1, D2, D3);
input EN, A0, A1;
output D0, D1, D2, D3;
assign D0 = (EN & ~A1 & ~A0);
assign D1 = (EN & ~A1 & A0);

Department of Electrical and Electronic Engineering, East West University Page 1 of 2


EEE 205 lab manual for students Experiment – 5

assign D2 = (EN & A1 & ~A0);


assign D3 = (EN & A1 & A0);
endmodule

2. Implement a 3-to-8 decoder using the 2-to-4 decoder in Quartus II software. Verify
with vector waveforms.

Department of Electrical and Electronic Engineering, East West University Page 2 of 2

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