Q1: Write the write and read instructions.

Explain with the

registers in the keyboard and display interface in program-
controlled I/O.

Program-Controlled I/O:

• In program-controlled I/O, the CPU is responsible for performing all

input/output operations.

• It continuously monitors the status of I/O devices and executes

appropriate read/write instructions.

Write Instruction:

1. Purpose: To send data to an output device.

2. Steps:

o CPU checks the status register of the output device.

o If the device is ready, the CPU writes data to the data register
of the device.

o Device processes the data.

3. Example for Display Interface:

o Registers:

▪ Status Register: Indicates whether the display device

is ready to accept data.

▪ Data Register: Holds the character to be displayed.

o Steps:

1. CPU checks the status register.

2. If the ready flag is set, CPU writes data to the data register.

Read Instruction:
 1. Purpose: To receive data from an input device.

2. Steps:

o CPU checks the status register of the input device.

o If data is available, the CPU reads it from the data register.

3. Example for Keyboard Interface:

o Registers:

▪ Status Register: Indicates whether a keypress is

available.

▪ Data Register: Holds the ASCII value of the pressed

key.

o Steps:

1. CPU checks the status register for a "data available" flag.

2. If the flag is set, the CPU reads the data from the data register.

Q2: What is an Interrupt? Discuss Interrupt & Response (I&R) for

a compute and display routine or similar examples.

Interrupt:

1. Definition:

o An interrupt is a signal sent to the CPU to indicate that an

external or internal event needs immediate attention.

2. Types:

o Hardware Interrupts: Generated by hardware devices (e.g.,

keyboard, mouse).

o Software Interrupts: Generated by software to request

specific CPU operations.
Interrupt & Response (I&R):

1. Interrupt Handling:

o When an interrupt occurs, the CPU:

1. Suspends the execution of the current program.

2. Saves the program counter (PC) and registers.

3. Jumps to the interrupt service routine (ISR).

2. Compute and Display Routine:

o Example: A program that computes a value and displays the

result on a screen.

o Scenario:

▪ CPU is executing a compute routine.

▪ An interrupt from the display device occurs, indicating

readiness to accept new data.

o Response:

▪ CPU saves the current state of the compute routine.

▪ Executes the ISR to send data to the display device.

▪ Resumes the compute routine.

Q3: How are interrupts handled in multiple devices? [Vectored

Interrupt and Interrupt Nesting].

Handling Interrupts from Multiple Devices:

1. Problem:

o When multiple devices generate interrupts simultaneously, the

system must prioritize and handle them efficiently.
 2. Methods:

o Polling: CPU checks each device to identify the source of the

interrupt (inefficient for multiple devices).

o Interrupt Priority: Assigns priorities to devices.

Vectored Interrupts:

1. Definition:

o The interrupting device provides the CPU with the address of

its ISR.

2. Advantages:

o Faster than polling.

o Reduces CPU overhead.

3. Example:

o Device A and Device B generate interrupts.

o Device A has a higher priority and provides its ISR address to

the CPU.

Interrupt Nesting:

1. Definition:

o Allows higher-priority interrupts to preempt lower-priority

ISRs.

2. Implementation:

o CPU checks the priority of incoming interrupts.

o Saves the state of the current ISR if a higher-priority interrupt

occurs.

3. Example:
 o Device A’s ISR is executing, but Device B (higher priority)
generates an interrupt.

o CPU suspends Device A’s ISR, handles Device B, and then

resumes Device A.

Q4: Internal Organization of a Memory Chip

Structure:

1. Basic Components:

o Memory Cells: Store data as binary bits (0 or 1).

o Row and Column Decoders: Translate addresses into

specific rows and columns.

o Sense Amplifiers: Detect the stored charge and amplify it

for reading.

o Control Circuitry: Manages read, write, and refresh

operations.

2. Organization:

o Memory is divided into rows and columns.

o Each cell is accessed by its row and column address.

Q5: Explain Dynamic RAM (DRAM) with a Diagram.

Dynamic RAM:

1. Definition:

o A type of volatile memory that stores data using a capacitor.

2. Working:

o Each memory cell consists of a capacitor and a transistor.

 o The capacitor stores a charge, representing binary 1 or 0.

o Data must be refreshed periodically to maintain the charge.

3. Advantages:

o Higher density and lower cost than SRAM.

4. Disadvantages:

o Slower access speed.

Q6: Explain Synchronous DRAM (SDRAM) with a Diagram.

Synchronous DRAM (SDRAM):

1. Definition:

o SDRAM is a type of DRAM synchronized with the system clock,

ensuring precise timing for data operations.

o Unlike traditional DRAM, which operates asynchronously,

SDRAM operates in sync with the CPU.

2. Features:

o Uses a clock signal for all operations.

o Supports burst mode to transfer multiple words in a single

operation.

o Employs pipelining, enabling a new operation to begin before

the previous one completes.

3. Working:

o The CPU sends commands such as row activate, read, or

write.

o SDRAM retrieves data in bursts, reducing latency.

o Data is transferred on each clock cycle.

 4. Advantages:

o Faster than asynchronous DRAM.

o Optimized for high-performance computing systems.

Q7: Types of ROM

Types of Read-Only Memory (ROM):

1. Mask ROM:

o Programmed during manufacturing and cannot be modified.

o Used for fixed firmware applications.

2. Programmable ROM (PROM):

o Initially blank; can be programmed once using a PROM

programmer.

o Used in applications requiring permanent but programmable

storage.

3. Erasable PROM (EPROM):

o Data can be erased using ultraviolet (UV) light and

reprogrammed.

o Common in applications requiring firmware updates.

4. Electrically Erasable PROM (EEPROM):

o Data can be erased and rewritten electrically.

o Used in BIOS chips.

5. Flash Memory:

o A modern type of EEPROM with faster erase/write cycles.

o Widely used in USB drives, SSDs, and portable devices.

Q8: Explain DMA (Direct Memory Access) with a Diagram.

Direct Memory Access (DMA):

1. Definition:

o DMA is a method where an I/O device can directly transfer

data to/from memory without CPU involvement.

2. Components:

o DMA Controller: Manages data transfer.

o Memory Address Register: Specifies source/destination

addresses.

o Control Signals: Include Read/Write and transfer complete

interrupts.

3. Working:

o The CPU initializes the DMA controller with data transfer

details (source, destination, and size).

o DMA controller takes control of the bus and performs the data
transfer.

o After the transfer, DMA sends an interrupt to the CPU.

4. Advantages:

o Reduces CPU workload.

o Faster data transfers, especially for high-speed devices.

Q9: Explain Cache Memory & Types of Mapping Functions.

Cache Memory:

1. Definition:
 o A high-speed memory located between the CPU and main
memory to store frequently accessed data.

2. Features:

o Reduces latency for data access.

o Acts as a buffer between slow main memory and the CPU.

3. Operation:

o CPU checks the cache for the required data:

▪ Cache Hit: Data is found in the cache.

▪ Cache Miss: Data is fetched from the main memory

and stored in the cache.

Types of Mapping Functions:

1. Direct Mapping:

o Each memory block maps to a specific cache line.

o Simple but causes conflicts if multiple blocks map to the same

line.

2. Associative Mapping:

o A memory block can be placed in any cache line.

o Eliminates conflicts but increases complexity.

3. Set-Associative Mapping:

o Divides the cache into sets.

o Each block maps to a specific set but can occupy any line
within the set.

Comparison Table:
Mapping Type Pros Cons

Direct Mapping Simple and fast High collision rate

Associative Mapping Flexible and collision-free Complex implementation

Set-Associative Balanced approach Moderate complexity

Q10: Explain Memory Hierarchy.

Memory Hierarchy:

1. Definition:

o A layered organization of memory systems designed to

balance speed, cost, and size.

2. Levels of Hierarchy:

o Registers:

▪ Smallest and fastest memory located within the CPU.

▪ Access time: 1 CPU cycle.

o Cache Memory:

▪ Small and fast memory located close to the CPU.

▪ Stores frequently used data and instructions.

o Main Memory (RAM):

▪ Medium speed and size; stores active programs.

o Secondary Storage:

▪ Non-volatile storage (e.g., HDD, SSD).

▪ High capacity but slower than RAM.

o Tertiary Storage:
 ▪ Used for archival purposes (e.g., tape drives).

Principles:

1. Locality of Reference:

o Temporal Locality: Recently accessed data is likely to be

accessed again.

o Spatial Locality: Data near recently accessed locations is

likely to be accessed.

2. Trade-Offs:

o Faster memory is more expensive.

o Slower memory is cheaper and larger.