Q1.

Write the code of following programme

A. Six basic gates with n input operation
B. 4 bit full adder
C. 4 Bit Adder Subtractor
D. Carry look ahead adder.
E. Parity Generator and checker
F. 4 Bit magnitude comparator

Soln. -
A.
module basic_gates_n_input(
input [n-1:0] A, // n-bit input
output Y_and, // AND output
output Y_or, // OR output
output Y_nand, // NAND output
output Y_nor, // NOR output
output Y_xor, // XOR output
output Y_xnor // XNOR output
);
// AND Gate with n inputs
assign Y_and = &A; // AND operation on all bits

// OR Gate with n inputs

assign Y_or = |A; // OR operation on all bits

// NAND Gate with n inputs

assign Y_nand = ~( &A ); // NAND is the negation of AND

// NOR Gate with n inputs

assign Y_nor = ~( |A ); // NOR is the negation of OR

// XOR Gate with n inputs

assign Y_xor = ^A; // XOR operation on all bits (parity)

// XNOR Gate with n inputs

assign Y_xnor = ~( ^A ); // XNOR is the negation of XOR

endmodule

B.

1 bit Full Adder-

module full_adder_1bit(
input A, B, Cin, // 1-bit inputs
 output Sum, Cout // Sum and Carry output
);
assign Sum = A ^ B ^ Cin; // Sum = A XOR B XOR Cin
assign Cout = (A & B) | (B & Cin) | (A & Cin); // Carry = (A AND B) OR (B AND Cin) OR (A
AND Cin)
endmodule

4 bit full adder

module full_adder_4bit(
input [3:0] A, B, // 4-bit inputs
input Cin, // Carry input
output [3:0] Sum, // 4-bit Sum output
output Cout // Carry output
);
wire c1, c2, c3; // Intermediate carry bits

// Instantiate 1-bit full adders

full_adder_1bit FA0 (
.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(c1)
);

full_adder_1bit FA1 (
.A(A[1]), .B(B[1]), .Cin(c1), .Sum(Sum[1]), .Cout(c2)
);

full_adder_1bit FA2 (
.A(A[2]), .B(B[2]), .Cin(c2), .Sum(Sum[2]), .Cout(c3)
);

full_adder_1bit FA3 (
.A(A[3]), .B(B[3]), .Cin(c3), .Sum(Sum[3]), .Cout(Cout)
);

endmodule

C.

module subtractor_4bit(
input [3:0] A, B, // 4-bit inputs A and B
output [3:0] Diff, // 4-bit difference (A - B)
output Borrow // Borrow output
);
wire [3:0] B_complement; // 1's complement of B
wire carry_in; // Carry-in for the addition

// Generate 2's complement of B (invert B and add 1)

 assign B_complement = ~B; // 1's complement of B
assign carry_in = 1; // Add 1 to the 1's complement for 2's complement

// Perform the subtraction: A + 2's complement of B

assign {Borrow, Diff} = A + B_complement + carry_in;

endmodule

D.

4 bit carry look ahead adder

module cla_4bit_adder(
input [3:0] A, B, // 4-bit inputs A and B
input Cin, // Carry input
output [3:0] Sum, // 4-bit Sum output
output Cout // Carry output
);
wire [3:0] G, P; // Generate and Propagate signals
wire [4:0] C; // Carry signals

// Generate the Carry Generate and Carry Propagate signals

assign G = A & B; // G_i = A_i AND B_i
assign P = A | B; // P_i = A_i OR B_i

// Calculate Carry bits using Look-Ahead logic

assign C[0] = Cin; // First carry input is Cin
assign C[1] = G[0] | (P[0] & C[0]); // Carry 1
assign C[2] = G[1] | (P[1] & C[1]); // Carry 2
assign C[3] = G[2] | (P[2] & C[2]); // Carry 3
assign C[4] = G[3] | (P[3] & C[3]); // Carry 4 (final carry-out)

// Sum = A XOR B XOR Carry-in

assign Sum = A ^ B ^ C[3:0]; // XOR for sum bits

// Carry out is the final carry bit (C[4])

assign Cout = C[4];

endmodule

E.

4 bit input parity Generator

(even)

module parity_generator(
input [3:0] data, // 4-bit data input
 output parity_bit // Parity bit output
);
assign parity_bit = data[0] ^ data[1] ^ data[2] ^ data[3]; // XOR all bits to generate parity
endmodule

(odd)

module odd_parity_generator(
input [3:0] data, // 4-bit data input
output parity_bit // Parity bit output
);
assign parity_bit = ~(data[0] ^ data[1] ^ data[2] ^ data[3]); // Invert XOR result for odd
parity
endmodule

4 bit input parity checker

(even)

module parity_checker(
input [3:0] data, // 4-bit data input
input parity_bit, // Parity bit input
output parity_ok // Output: 1 if parity is correct, 0 if error detected
);
wire parity_check;

assign parity_check = data[0] ^ data[1] ^ data[2] ^ data[3] ^ parity_bit; // XOR all bits
including parity bit

assign parity_ok = (parity_check == 0); // If result is 0, parity is correct (even parity)

endmodule

(odd)

module odd_parity_checker(
input [3:0] data, // 4-bit data input
input parity_bit, // Parity bit input
output parity_ok // Output: 1 if parity is correct, 0 if error detected
);
wire parity_check;

assign parity_check = data[0] ^ data[1] ^ data[2] ^ data[3] ^ parity_bit; // XOR all bits
including parity bit

assign parity_ok = (parity_check == 1); // For odd parity, the result should be 1 for correct
parity
endmodule
F.

module magnitude_comparator(
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
output A_eq_B, // Output: 1 if A == B
output A_gt_B, // Output: 1 if A > B
output A_lt_B // Output: 1 if A < B
);
// Check if A is equal to B
assign A_eq_B = (A == B);

// Check if A is greater than B

assign A_gt_B = (A > B);

// Check if A is less than B

assign A_lt_B = (A < B);

endmodule

Q2.
Write the code of MSI logic like ( choose appropriate programming process)
A. 4 bit , 8 bit , 16 bit MUX
B. 4 bit , 8 bit , 16 bit Demux
C. 16 bit MUX using MUX tree
D. 64 bit MUX using MUX tree
E. Full adder using MUX
F. 3-8 Decoder
G. BCD encoder
H. BCD to Excess three converter using Decoder
I. BCD to Grey code converter using Decoder
J. Priority Encoder

Soln-

A.

4 bit Mux

module mux4to1 (
input [3:0] data_in, // 4-bit input data
input [1:0] select, // 2-bit select line
output reg out // MUX output
);
 always @ (data_in or select) begin
case(select)
2'b00: out = data_in[0]; // Select input 0
2'b01: out = data_in[1]; // Select input 1
2'b10: out = data_in[2]; // Select input 2
2'b11: out = data_in[3]; // Select input 3
default: out = 0;
endcase
end

endmodule

8 bit mux

module mux4to1 (
input [3:0] data_in [3:0], // 4 inputs, each 4-bit wide
input [1:0] select, // 2-bit select line
output reg [3:0] out // 4-bit output
);

always @ (data_in or select) begin

case(select)
2'b00: out = data_in[0]; // Select input 0
2'b01: out = data_in[1]; // Select input 1
2'b10: out = data_in[2]; // Select input 2
2'b11: out = data_in[3]; // Select input 3
default: out = 4'b0000; // Default case
endcase
end

endmodule

module mux8to1_using_4bit_mux (
input [7:0] data_in [7:0], // 8 inputs, each 8-bit wide
input [2:0] select, // 3-bit select line
output [7:0] out // 8-bit output
);

wire [3:0] mux1_out, mux2_out; // Intermediate 4-bit outputs

// First 4-bit MUX for lower 4 bits

mux4to1 mux1 (
.data_in({data_in[0][3:0], data_in[1][3:0], data_in[2][3:0], data_in[3][3:0]}),
.select(select[1:0]),
.out(mux1_out)
);
 // Second 4-bit MUX for upper 4 bits
mux4to1 mux2 (
.data_in({data_in[4][3:0], data_in[5][3:0], data_in[6][3:0], data_in[7][3:0]}),
.select(select[1:0]),
.out(mux2_out)
);

// Combine the two 4-bit outputs based on the select line

assign out = (select[2] == 0) ? {mux1_out, mux2_out} : {mux2_out, mux1_out};

endmodule

16 bit mux

module mux4to1 (
input [3:0] data_in [3:0], // 4 inputs, each 4-bit wide
input [1:0] select, // 2-bit select line
output reg [3:0] out // 4-bit output
);

always @ (data_in or select) begin

case(select)
2'b00: out = data_in[0]; // Select input 0
2'b01: out = data_in[1]; // Select input 1
2'b10: out = data_in[2]; // Select input 2
2'b11: out = data_in[3]; // Select input 3
default: out = 4'b0000; // Default case
endcase
end

endmodule

module mux16to1_using_4bit_mux (
input [15:0] data_in [15:0], // 16 inputs, each 16-bit wide
input [3:0] select, // 4-bit select line
output [15:0] out // 16-bit output
);

wire [3:0] mux1_out, mux2_out, mux3_out, mux4_out; // Intermediate 4-bit outputs

// First 4-bit MUX for lower 4 bits

mux4to1 mux1 (
.data_in({data_in[0][3:0], data_in[1][3:0], data_in[2][3:0], data_in[3][3:0]}),
.select(select[1:0]),
.out(mux1_out)
);
 // Second 4-bit MUX for next 4 bits
mux4to1 mux2 (
.data_in({data_in[4][3:0], data_in[5][3:0], data_in[6][3:0], data_in[7][3:0]}),
.select(select[1:0]),
.out(mux2_out)
);

// Third 4-bit MUX for next 4 bits

mux4to1 mux3 (
.data_in({data_in[8][3:0], data_in[9][3:0], data_in[10][3:0], data_in[11][3:0]}),
.select(select[1:0]),
.out(mux3_out)
);

// Fourth 4-bit MUX for upper 4 bits

mux4to1 mux4 (
.data_in({data_in[12][3:0], data_in[13][3:0], data_in[14][3:0], data_in[15][3:0]}),
.select(select[1:0]),
.out(mux4_out)
);

// Combine the four 4-bit outputs based on the select line

assign out = (select[3] == 0) ? {mux1_out, mux2_out} : {mux3_out, mux4_out};

endmodule

B.

4 bit dmux

module demux_4bit(
input [3:0] data, // 4-bit data input
input [3:0] sel, // 4-bit select signal
output reg [3:0] out0, out1, out2, out3, out4, out5, out6, out7,
out8, out9, out10, out11, out12, out13, out14, out15 // 16 outputs
);

always @(*) begin

// Default all outputs to 0
out0 = 4'b0; out1 = 4'b0; out2 = 4'b0; out3 = 4'b0;
out4 = 4'b0; out5 = 4'b0; out6 = 4'b0; out7 = 4'b0;
out8 = 4'b0; out9 = 4'b0; out10 = 4'b0; out11 = 4'b0;
out12 = 4'b0; out13 = 4'b0; out14 = 4'b0; out15 = 4'b0;

// Based on the select signal, route data to the correct output

case(sel)
4'b0000: out0 = data;
 4'b0001: out1 = data;
4'b0010: out2 = data;
4'b0011: out3 = data;
4'b0100: out4 = data;
4'b0101: out5 = data;
4'b0110: out6 = data;
4'b0111: out7 = data;
4'b1000: out8 = data;
4'b1001: out9 = data;
4'b1010: out10 = data;
4'b1011: out11 = data;
4'b1100: out12 = data;
4'b1101: out13 = data;
4'b1110: out14 = data;
4'b1111: out15 = data;
default: begin
out0 = 4'b0; out1 = 4'b0; out2 = 4'b0; out3 = 4'b0;
out4 = 4'b0; out5 = 4'b0; out6 = 4'b0; out7 = 4'b0;
out8 = 4'b0; out9 = 4'b0; out10 = 4'b0; out11 = 4'b0;
out12 = 4'b0; out13 = 4'b0; out14 = 4'b0; out15 = 4'b0;
end
endcase
end

endmodule

8 bit demux

module demux_8bit(
input [7:0] data, // 8-bit data input
input [3:0] sel, // 4-bit select signal
output [3:0] out0, out1, out2, out3, out4, out5, out6, out7,
out8, out9, out10, out11, out12, out13, out14, out15 // 16 outputs
);

wire [3:0] data0 = data[3:0]; // Lower 4 bits

wire [3:0] data1 = data[7:4]; // Upper 4 bits

// Use two 4-bit demuxes for the upper and lower 4 bits
demux_4bit demux_lower (
.data(data0),
.sel(sel),
.out0(out0), .out1(out1), .out2(out2), .out3(out3),
.out4(out4), .out5(out5), .out6(out6), .out7(out7),
.out8(out8), .out9(out9), .out10(out10), .out11(out11),
.out12(out12), .out13(out13), .out14(out14), .out15(out15)
);
demux_4bit demux_upper (
.data(data1),
.sel(sel),
.out0(out0), .out1(out1), .out2(out2), .out3(out3),
.out4(out4), .out5(out5), .out6(out6), .out7(out7),
.out8(out8), .out9(out9), .out10(out10), .out11(out11),
.out12(out12), .out13(out13), .out14(out14), .out15(out15)
);

endmodule

16 bit demux

module demux_16bit(
input [15:0] data, // 16-bit data input
input [3:0] sel, // 4-bit select signal
output [3:0] out0, out1, out2, out3, out4, out5, out6, out7,
out8, out9, out10, out11, out12, out13, out14, out15 // 16 outputs
);

wire [7:0] data0 = data[7:0]; // Lower 8 bits

wire [7:0] data1 = data[15:8]; // Upper 8 bits

// Use two 8-bit demuxes for the lower and upper 8 bits
demux_8bit demux_lower (
.data(data0),
.sel(sel),
.out0(out0), .out1(out1), .out2(out2), .out3(out3),
.out4(out4), .out5(out5), .out6(out6), .out7(out7),
.out8(out8), .out9(out9), .out10(out10), .out11(out11),
.out12(out12), .out13(out13), .out14(out14), .out15(out15)
);

demux_8bit demux_upper (
.data(data1),
.sel(sel),
.out0(out0), .out1(out1), .out2(out2), .out3(out3),
.out4(out4), .out5(out5), .out6(out6), .out7(out7),
.out8(out8), .out9(out9), .out10(out10), .out11(out11),
.out12(out12), .out13(out13), .out14(out14), .out15(out15)
);

endmodule

C.

module mux_16bit (
input [15:0] data, // 16-bit input data
 input [3:0] sel, // 4-bit select signal
output reg [15:0] out // 16-bit output
);

wire [15:0] mux_level1[7:0]; // 8 outputs from level 1 (each 16-bit)

wire [15:0] mux_level2[3:0]; // 4 outputs from level 2 (each 16-bit)
wire [15:0] mux_level3[1:0]; // 2 outputs from level 3 (each 16-bit)

// Level 1: 8 multiplexers (2-to-1), each with 16-bit inputs and output

mux_2to1 mux1 ( .a(data[0]), .b(data[1]), .sel(sel[0]), .out(mux_level1[0]) );
mux_2to1 mux2 ( .a(data[2]), .b(data[3]), .sel(sel[0]), .out(mux_level1[1]) );
mux_2to1 mux3 ( .a(data[4]), .b(data[5]), .sel(sel[0]), .out(mux_level1[2]) );
mux_2to1 mux4 ( .a(data[6]), .b(data[7]), .sel(sel[0]), .out(mux_level1[3]) );
mux_2to1 mux5 ( .a(data[8]), .b(data[9]), .sel(sel[0]), .out(mux_level1[4]) );
mux_2to1 mux6 ( .a(data[10]), .b(data[11]), .sel(sel[0]), .out(mux_level1[5]) );
mux_2to1 mux7 ( .a(data[12]), .b(data[13]), .sel(sel[0]), .out(mux_level1[6]) );
mux_2to1 mux8 ( .a(data[14]), .b(data[15]), .sel(sel[0]), .out(mux_level1[7]) );

// Level 2: 4 multiplexers (2-to-1), each with 16-bit inputs and output

mux_2to1 mux9 ( .a(mux_level1[0]), .b(mux_level1[1]), .sel(sel[1]), .out(mux_level2[0]) );
mux_2to1 mux10 ( .a(mux_level1[2]), .b(mux_level1[3]), .sel(sel[1]), .out(mux_level2[1]) );
mux_2to1 mux11 ( .a(mux_level1[4]), .b(mux_level1[5]), .sel(sel[1]), .out(mux_level2[2]) );
mux_2to1 mux12 ( .a(mux_level1[6]), .b(mux_level1[7]), .sel(sel[1]), .out(mux_level2[3]) );

// Level 3: 2 multiplexers (2-to-1), each with 16-bit inputs and output

mux_2to1 mux13 ( .a(mux_level2[0]), .b(mux_level2[1]), .sel(sel[2]), .out(mux_level3[0]) );
mux_2to1 mux14 ( .a(mux_level2[2]), .b(mux_level2[3]), .sel(sel[2]), .out(mux_level3[1]) );

// Level 4: Final multiplexer (2-to-1), selecting between two 16-bit inputs

mux_2to1 mux15 ( .a(mux_level3[0]), .b(mux_level3[1]), .sel(sel[3]), .out(out) );

endmodule

// 2-to-1 MUX (16-bit)

module mux_2to1 (
input [15:0] a, // 16-bit input a
input [15:0] b, // 16-bit input b
input sel, // Select signal
output [15:0] out // 16-bit output
);

assign out = (sel) ? b : a; // Select between inputs a and b based on sel

endmodule

D.

module mux_64bit (
 input [63:0] data, // 64-bit input data
input [5:0] sel, // 6-bit select signal
output reg [63:0] out // 64-bit output
);

wire [63:0] mux_level1[31:0]; // 32 outputs from level 1 (each 64-bit)

wire [63:0] mux_level2[15:0]; // 16 outputs from level 2 (each 64-bit)
wire [63:0] mux_level3[7:0]; // 8 outputs from level 3 (each 64-bit)
wire [63:0] mux_level4[3:0]; // 4 outputs from level 4 (each 64-bit)
wire [63:0] mux_level5[1:0]; // 2 outputs from level 5 (each 64-bit)

// Level 1: 32 multiplexers (2-to-1), each with 64-bit inputs and output

genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : level1_mux
mux_2to1 mux1 (
.a(data[2*i + 0]), .b(data[2*i + 1]),
.sel(sel[0]),
.out(mux_level1[i])
);
end
endgenerate

// Level 2: 16 multiplexers (2-to-1), each with 64-bit inputs and output

generate
for (i = 0; i < 16; i = i + 1) begin : level2_mux
mux_2to1 mux2 (
.a(mux_level1[2*i + 0]), .b(mux_level1[2*i + 1]),
.sel(sel[1]),
.out(mux_level2[i])
);
end
endgenerate

// Level 3: 8 multiplexers (2-to-1), each with 64-bit inputs and output

generate
for (i = 0; i < 8; i = i + 1) begin : level3_mux
mux_2to1 mux3 (
.a(mux_level2[2*i + 0]), .b(mux_level2[2*i + 1]),
.sel(sel[2]),
.out(mux_level3[i])
);
end
endgenerate

// Level 4: 4 multiplexers (2-to-1), each with 64-bit inputs and output

generate
for (i = 0; i < 4; i = i + 1) begin : level4_mux
 mux_2to1 mux4 (
.a(mux_level3[2*i + 0]), .b(mux_level3[2*i + 1]),
.sel(sel[3]),
.out(mux_level4[i])
);
end
endgenerate

// Level 5: 2 multiplexers (2-to-1), each with 64-bit inputs and output

generate
for (i = 0; i < 2; i = i + 1) begin : level5_mux
mux_2to1 mux5 (
.a(mux_level4[2*i + 0]), .b(mux_level4[2*i + 1]),
.sel(sel[4]),
.out(mux_level5[i])
);
end
endgenerate

// Level 6: Final multiplexer (2-to-1), selecting between two 64-bit inputs

mux_2to1 mux6 (
.a(mux_level5[0]), .b(mux_level5[1]),
.sel(sel[5]),
.out(out)
);

endmodule

// 2-to-1 MUX (64-bit)

module mux_2to1 (
input [63:0] a, // 64-bit input a
input [63:0] b, // 64-bit input b
input sel, // Select signal
output [63:0] out // 64-bit output
);

assign out = (sel) ? b : a; // Select between inputs a and b based on sel

endmodule

E.

Full adder using 2x1 mux

module full_adder_mux (
input A, // Input A
input B, // Input B
input Cin, // Carry-in
 output Sum, // Sum output
output Cout // Carry-out output
);

// MUX for Sum

wire mux_sum_0, mux_sum_1;
mux_2to1 mux_sum0 (.a(1'b0), .b(1'b1), .sel(A), .out(mux_sum_0));
mux_2to1 mux_sum1 (.a(Cin), .b(mux_sum_0), .sel(B), .out(Sum));

// MUX for Carry-out

wire mux_cout_0, mux_cout_1;
mux_2to1 mux_cout0 (.a(1'b0), .b(1'b1), .sel(A), .out(mux_cout_0));
mux_2to1 mux_cout1 (.a(1'b0), .b(Cin), .sel(B), .out(mux_cout_1));
mux_2to1 mux_cout2 (.a(mux_cout_0), .b(mux_cout_1), .sel(A), .out(Cout));

endmodule

// 2-to-1 MUX implementation (used for Sum and Carry)

module mux_2to1 (
input a, // Input a
input b, // Input b
input sel, // Select line
output out // Output
);

assign out = (sel) ? b : a; // If sel = 1, output b; if sel = 0, output a

endmodule

F.

module decoder3to8 (
input [2:0] A, // 3-bit input
output reg [7:0] Y // 8-bit output
);

always @ (A) begin

case (A)
3'b000: Y = 8'b00000001; // Activate output 0
3'b001: Y = 8'b00000010; // Activate output 1
3'b010: Y = 8'b00000100; // Activate output 2
3'b011: Y = 8'b00001000; // Activate output 3
3'b100: Y = 8'b00010000; // Activate output 4
3'b101: Y = 8'b00100000; // Activate output 5
3'b110: Y = 8'b01000000; // Activate output 6
3'b111: Y = 8'b10000000; // Activate output 7
default: Y = 8'b00000000; // Default case: no output active
 endcase
end

endmodule

G.

module bcd_encoder (
input [9:0] bcd_in, // 10-bit input for BCD digits (from 0 to 9)
output reg [3:0] bcd_out // 4-bit output BCD representation
);

always @ (bcd_in) begin

case (bcd_in)
10'b0000000001: bcd_out = 4'b0000; // 0
10'b0000000010: bcd_out = 4'b0001; // 1
10'b0000000100: bcd_out = 4'b0010; // 2
10'b0000001000: bcd_out = 4'b0011; // 3
10'b0000010000: bcd_out = 4'b0100; // 4
10'b0000100000: bcd_out = 4'b0101; // 5
10'b0001000000: bcd_out = 4'b0110; // 6
10'b0010000000: bcd_out = 4'b0111; // 7
10'b0100000000: bcd_out = 4'b1000; // 8
10'b1000000000: bcd_out = 4'b1001; // 9
default: bcd_out = 4'bxxxx; // Undefined input
endcase
end
endmodule

H.

module bcd_to_excess3_using_decoder (
input [3:0] bcd, // 4-bit BCD input (0 to 9)
output reg [3:0] excess3 // 4-bit Excess-3 output
);
// 4-to-10 Decoder logic for BCD inputs
always @(*) begin
case (bcd)
4'b0000: excess3 = 4'b0011; // BCD 0 -> Excess-3 3
4'b0001: excess3 = 4'b0100; // BCD 1 -> Excess-3 4
4'b0010: excess3 = 4'b0101; // BCD 2 -> Excess-3 5
4'b0011: excess3 = 4'b0110; // BCD 3 -> Excess-3 6
4'b0100: excess3 = 4'b0111; // BCD 4 -> Excess-3 7
4'b0101: excess3 = 4'b1000; // BCD 5 -> Excess-3 8
4'b0110: excess3 = 4'b1001; // BCD 6 -> Excess-3 9
4'b0111: excess3 = 4'b1010; // BCD 7 -> Excess-3 10
4'b1000: excess3 = 4'b1011; // BCD 8 -> Excess-3 11
4'b1001: excess3 = 4'b1100; // BCD 9 -> Excess-3 12
 default: excess3 = 4'b0000; // Default case (for invalid BCD)
endcase
end
endmodule

I.

module bcd_to_gray_using_decoder (
input [3:0] bcd, // 4-bit BCD input (0 to 9)
output reg [3:0] gray // 4-bit Gray code output
);
// 4-to-10 Decoder logic for BCD inputs to Gray code
always @(*) begin
case (bcd)
4'b0000: gray = 4'b0000; // BCD 0 -> Gray Code 0000
4'b0001: gray = 4'b0001; // BCD 1 -> Gray Code 0001
4'b0010: gray = 4'b0011; // BCD 2 -> Gray Code 0011
4'b0011: gray = 4'b0010; // BCD 3 -> Gray Code 0010
4'b0100: gray = 4'b0110; // BCD 4 -> Gray Code 0110
4'b0101: gray = 4'b0111; // BCD 5 -> Gray Code 0111
4'b0110: gray = 4'b0101; // BCD 6 -> Gray Code 0101
4'b0111: gray = 4'b0100; // BCD 7 -> Gray Code 0100
4'b1000: gray = 4'b1100; // BCD 8 -> Gray Code 1100
4'b1001: gray = 4'b1101; // BCD 9 -> Gray Code 1101
default: gray = 4'b0000; // Default case (invalid BCD)
endcase
end
endmodule

J.

module priority_encoder (
input [3:0] in, // 4-bit input (I0 to I3)
output reg [1:0] out, // 2-bit output (Y1, Y0)
output reg valid // Valid signal to indicate any input is active
);

always @(*) begin

// Default output values
out = 2'b00; // Default output (no input active)
valid = 0; // Default valid output (no input active)

// Priority encoder logic

if (in[3] == 1) begin
out = 2'b11; // If I3 is active, output is 3
valid = 1; // Set valid signal to 1
end
else if (in[2] == 1) begin
 out = 2'b10; // If I2 is active, output is 2
valid = 1; // Set valid signal to 1
end
else if (in[1] == 1) begin
out = 2'b01; // If I1 is active, output is 1
valid = 1; // Set valid signal to 1
end
else if (in[0] == 1) begin
out = 2'b00; // If I0 is active, output is 0
valid = 1; // Set valid signal to 1
end
else begin
valid = 0; // If no input is active, valid is 0
end
end
endmodule

Q3.
Write the code for following sequential logic
A. J-K , D and T flipflop
B. Pulse generator
C. 3 bit up down ripple counter
D. 3 bit ring counter
E. 3 bit Shift right-left register ( choose clock as per req)
F. Mod 2, Mod 5, Mod 10 counter
G. 4-bit Unsigned Up Counter with Asynchronous Clear

Soln-

A.

J-K FF

module jk_flip_flop (
input J, // J input
input K, // K input
input CLK, // Clock input
input RESET, // Asynchronous Reset
output reg Q // Output Q
);

// Behavioral description of J-K flip-flop with asynchronous reset

always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
Q <= 0; // Reset output Q to 0
end else begin
 case ({J, K})
2'b00: Q <= Q; // No change
2'b01: Q <= 0; // Reset Q to 0
2'b10: Q <= 1; // Set Q to 1
2'b11: Q <= ~Q; // Toggle Q
default: Q <= Q; // Default case (shouldn't occur)
endcase
end
end

endmodule

D FF

module d_flip_flop (
input D, // Data input
input CLK, // Clock input
input RESET, // Asynchronous reset
output reg Q // Output Q
);

// Behavioral description of D flip-flop with asynchronous reset

always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
Q <= 0; // Reset the output Q to 0
end else begin
Q <= D; // Transfer D to Q on the rising edge of CLK
end
end

endmodule

T FF

module t_flip_flop (
input T, // Toggle input
input CLK, // Clock input
input RESET, // Asynchronous reset
output reg Q // Output Q
);

// Behavioral description of T flip-flop with asynchronous reset

always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
Q <= 0; // Reset output Q to 0
end else if (T) begin
Q <= ~Q; // Toggle Q when T is high
end
 end

endmodule

B.

module pulse_generator (
input CLK, // Input clock
input RESET, // Asynchronous reset
output reg PULSE // Output pulse signal
);

reg Q; // Internal Q to toggle the pulse

// Use a T Flip-Flop for pulse generation

always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
Q <= 0; // Reset the internal Q to 0
PULSE <= 0; // Reset the pulse output to 0
end else begin
Q <= ~Q; // Toggle Q on each clock cycle
PULSE <= Q; // Output PULSE is the value of Q
end
end

endmodule

C.

module up_down_ripple_counter (
input CLK, // Clock input
input RESET, // Asynchronous reset
input UP_DOWN, // Up/Down control (1 for up, 0 for down)
output reg [2:0] Q // 3-bit output (Q2, Q1, Q0)
);

// Internal flip-flops (D flip-flops)

reg Q0, Q1, Q2;

// Asynchronous reset and counting logic

always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
Q0 <= 0; // Reset Q0 to 0
Q1 <= 0; // Reset Q1 to 0
Q2 <= 0; // Reset Q2 to 0
end else begin
 if (UP_DOWN) begin
// Counting Up (increment)
Q0 <= ~Q0; // Toggle Q0 on every clock cycle
if (Q0 == 1) begin
Q1 <= ~Q1; // Toggle Q1 when Q0 rolls over
if (Q1 == 1) begin
Q2 <= ~Q2; // Toggle Q2 when Q1 rolls over
end
end
end else begin
// Counting Down (decrement)
Q0 <= ~Q0; // Toggle Q0 on every clock cycle
if (Q0 == 0) begin
Q1 <= ~Q1; // Toggle Q1 when Q0 rolls over
if (Q1 == 0) begin
Q2 <= ~Q2; // Toggle Q2 when Q1 rolls over
end
end
end
end
end

// Output the 3-bit counter value

always @ (*) begin
Q = {Q2, Q1, Q0};
end

endmodule

D.

module ring_counter (
input CLK, // Clock input
input RESET, // Asynchronous reset
output reg [2:0] Q // 3-bit output (Q2, Q1, Q0)
);

// Internal flip-flops (D flip-flops)

reg Q0, Q1, Q2;

// Ring counter logic

always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
// Reset all flip-flops to 0, and set Q0 to 1 for the initial state
Q0 <= 1;
Q1 <= 0;
Q2 <= 0;
end else begin
 // Shift the "1" through the flip-flops
Q0 <= Q2; // Q0 gets the value of Q2
Q1 <= Q0; // Q1 gets the value of Q0
Q2 <= Q1; // Q2 gets the value of Q1
end
end

// Assign the 3-bit output to the flip-flop values

always @ (*) begin
Q = {Q2, Q1, Q0}; // Concatenate Q2, Q1, Q0 to form the 3-bit output
end

endmodule

E.

module shift_register (
input CLK, // Clock input
input RESET, // Asynchronous reset
input SHIFT_LEFT, // Shift left control (1 for shift left)
input SHIFT_RIGHT, // Shift right control (1 for shift right)
input [2:0] D, // 3-bit input data to load
output reg [2:0] Q // 3-bit output register value
);

always @ (posedge CLK or posedge RESET) begin

if (RESET) begin
Q <= 3'b000; // Reset register Q to 000
end else if (SHIFT_LEFT) begin
Q <= {Q[1:0], 1'b0}; // Shift left, insert 0 at Q0
end else if (SHIFT_RIGHT) begin
Q <= {1'b0, Q[2:1]}; // Shift right, insert 0 at Q2
end else begin
Q <= D; // Load input data D directly into Q if no shift
end
end

endmodule

F.

MOD 2

module mod2_counter (
input CLK, // Clock input
input RESET, // Asynchronous reset
 output reg [0:0] Q // 1-bit output (Q0)
);

always @ (posedge CLK or posedge RESET) begin

if (RESET) begin
Q <= 1'b0; // Reset to 0
end else begin
Q <= ~Q; // Toggle between 0 and 1
end
end
endmodule

MOD 5

module mod5_counter (
input CLK, // Clock input
input RESET, // Asynchronous reset
output reg [2:0] Q // 3-bit output (Q2, Q1, Q0)
);

always @ (posedge CLK or posedge RESET) begin

if (RESET) begin
Q <= 3'b000; // Reset to 000
end else begin
if (Q == 3'b100) begin
Q <= 3'b000; // Reset when it reaches 4 (100)
end else begin
Q <= Q + 1; // Increment the counter
end
end
end
endmodule

MOD 10

module mod10_counter (
input CLK, // Clock input
input RESET, // Asynchronous reset
output reg [3:0] Q // 4-bit output (Q3, Q2, Q1, Q0)
);

always @ (posedge CLK or posedge RESET) begin

if (RESET) begin
Q <= 4'b0000; // Reset to 0000
end else begin
if (Q == 4'b1001) begin
Q <= 4'b0000; // Reset when it reaches 9 (1001)
 end else begin
Q <= Q + 1; // Increment the counter
end
end
end
endmodule

G.

module up_counter (
input wire clk, // Clock signal
input wire clear, // Asynchronous clear signal
output reg [3:0] count // 4-bit counter output
);

// Asynchronous reset for the counter

always @(posedge clk or posedge clear) begin
if (clear)
count <= 4'b0000; // Clear the counter when 'clear' is high
else
count <= count + 1; // Increment the counter on each clock cycle
end

endmodule

Q4.
Write code for 16 word 8 bit RAM

Soln-
module ram_16x8 (
input wire clk, // Clock signal
input wire we, // Write enable signal
input wire [3:0] addr, // 4-bit address (16 words = 2^4 address bits)
input wire [7:0] din, // 8-bit data input (to be written into RAM)
output reg [7:0] dout // 8-bit data output (data read from RAM)
);

// Declare 16x8-bit RAM (16 words, 8 bits each)

reg [7:0] ram [0:15];

// Always block to handle read/write operations

always @(posedge clk) begin
if (we) begin
 ram[addr] <= din; // Write data to RAM at the specified address
end
dout <= ram[addr]; // Read data from RAM at the specified address
end

endmodule

Q5. Write a code for Mealy Machine

Soln-

module mealy_machine (
input wire clk, // Clock signal
input wire reset, // Asynchronous reset
input wire x, // Input signal
output reg y // Output signal
);

// Define the states

typedef enum reg [1:0] {
S0 = 2'b00, // State S0
S1 = 2'b01 // State S1
} state_t;

// Declare the current and next state variables

state_t current_state, next_state;

// State transition and output logic (combinational)

always @(*) begin
case (current_state)
S0: begin
y = x; // Output depends on x when in state S0
next_state = (x) ? S1 : S0; // Transition to S1 if x=1, stay in S0 if x=0
end
S1: begin
y = ~x; // Output is the negation of x in state S1
next_state = (x) ? S0 : S1; // Transition to S0 if x=1, stay in S1 if x=0
end
default: begin
y = 1'b0;
next_state = S0;
end
endcase
end

// State update logic (sequential)

always @(posedge clk or posedge reset) begin
 if (reset) begin
current_state <= S0; // Reset to state S0
end else begin
current_state <= next_state; // Update state on clock edge
end
end

endmodule

Q6. Write a code for Moore Machine

Soln-

module moore_machine (
input wire clk, // Clock signal
input wire reset, // Asynchronous reset
input wire x, // Input signal
output reg y // Output signal
);

// Define the states (2-bit encoding)

typedef enum reg [1:0] {
S0 = 2'b00, // State S0
S1 = 2'b01 // State S1
} state_t;

// Declare the current and next state variables

state_t current_state, next_state;

// State transition logic (combinational)

always @(*) begin
case (current_state)
S0: begin
next_state = (x) ? S1 : S0; // Transition to S1 if x=1, stay in S0 if x=0
end
S1: begin
next_state = (x) ? S1 : S0; // Transition to S0 if x=0, stay in S1 if x=1
end
default: begin
next_state = S0;
end
endcase
end

// Output logic (Moore machine: output depends only on the current state)
always @(current_state) begin
 case (current_state)
S0: y = 0; // Output 0 in state S0
S1: y = 1; // Output 1 in state S1
default: y = 0;
endcase
end

// State update logic (sequential)

always @(posedge clk or posedge reset) begin
if (reset) begin
current_state <= S0; // Reset to state S0
end else begin
current_state <= next_state; // Update state on clock edge
end
end

endmodule

Q7. Write test bench for following

A. Mealy Machine
B. Moore Machine
C. 16 bit MUX tree
D. Ring counter
E. 4 bit Parallel adder
F. n bit Ex-or

Soln-

A.

module tb_mealy_machine;

reg clk;
reg reset;
reg x;
wire y;

// Instantiate the Mealy Machine

mealy_machine uut (
.clk(clk),
.reset(reset),
.x(x),
.y(y)
);
 // Clock generation
always #5 clk = ~clk;

// Test Sequence
initial begin
// Initialize signals
clk = 0;
reset = 1;
x = 0;

// Reset the machine

#10 reset = 0;

// Test transitions and outputs

#10 x = 0; // y will depend on the current state (S0)
#10 x = 1; // Transition to S1, y will depend on x
#10 x = 0; // Transition to S0, y will depend on x
#10 x = 1; // y will depend on the current state (S1)
#10 $stop;
end

endmodule

B.

module tb_moore_machine;

reg clk;
reg reset;
reg x;
wire y;

// Instantiate the Moore Machine

moore_machine uut (
.clk(clk),
.reset(reset),
.x(x),
.y(y)
);

// Clock generation
always #5 clk = ~clk;

// Test Sequence
initial begin
// Initialize signals
 clk = 0;
reset = 1;
x = 0;

// Reset the machine

#10 reset = 0;

// Test transitions and outputs

#10 x = 0; // y will be 0 in state S0
#10 x = 1; // Transition to state S1, y will be 1
#10 x = 0; // Transition to state S0, y will be 0
#10 x = 1; // Stay in state S1, y will be 1
#10 $stop;
end

endmodule

C.

module tb_mux_tree;

reg [15:0] data_in;

reg [3:0] select;
wire mux_out;

// Instantiate the 16-bit MUX tree

mux_tree uut (
.data_in(data_in),
.select(select),
.mux_out(mux_out)
);

// Test Sequence
initial begin
// Initialize signals
data_in = 16'b1010101010101010;
select = 4'b0000;

// Test different select lines

#10 select = 4'b0000; // MUX should select the first bit of data_in
#10 select = 4'b0001; // MUX should select the second bit of data_in
#10 select = 4'b0010; // MUX should select the third bit of data_in
#10 select = 4'b1111; // MUX should select the last bit of data_in
#10 $stop;
end

endmodule
D.

module tb_ring_counter;

reg clk;
reg reset;
wire [3:0] out;

// Instantiate the Ring Counter

ring_counter uut (
.clk(clk),
.reset(reset),
.out(out)
);

// Clock generation
always #5 clk = ~clk;

// Test Sequence
initial begin
// Initialize signals
clk = 0;
reset = 1;

// Apply reset
#10 reset = 0;

// Test the ring counter

#10 reset = 1; // Reset the ring counter
#10 reset = 0; // Observe the counter output
#40 $stop; // Run for a while to see the ring counting
end

endmodule

E.

module tb_parallel_adder;

reg [3:0] A, B;
reg Cin;
wire [3:0] Sum;
wire Cout;

// Instantiate the 4-bit Parallel Adder

 parallel_adder uut (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);

// Test Sequence
initial begin
// Initialize signals
A = 4'b0000;
B = 4'b0000;
Cin = 0;

// Apply test cases

#10 A = 4'b0001; B = 4'b0010; Cin = 0; // A + B = 3
#10 A = 4'b1111; B = 4'b0001; Cin = 0; // A + B = 16
#10 A = 4'b1111; B = 4'b1111; Cin = 1; // A + B + Cin = 31
#10 $stop;
end

endmodule

F.

module tb_nbit_xor;

reg [7:0] A; // 8-bit input for the testbench

reg [7:0] B; // 8-bit input for the testbench
wire [7:0] Y; // 8-bit output of XOR

// Instantiate the n-bit XOR gate (assuming it's an 8-bit XOR)

nbit_xor uut (
.A(A),
.B(B),
.Y(Y)
);

// Test Sequence
initial begin
// Initialize signals
A = 8'b00000000;
B = 8'b00000000;

// Apply test cases

#10 A = 8'b10101010; B = 8'b01010101; // Expected result: Y = 11111111
 #10 A = 8'b11110000; B = 8'b00001111; // Expected result: Y = 11111111
#10 A = 8'b11111111; B = 8'b00000000; // Expected result: Y = 11111111
#10 $stop;
end

endmodule

Q8.
Write a code for Dual-Port RAM with Asynchronous Read

Soln-

module dual_port_ram (
input wire clk, // Clock signal (only for write operations)
input wire we, // Write enable signal (active high)
input wire [3:0] addr_write, // 4-bit write address (16 locations)
input wire [3:0] addr_read, // 4-bit read address (16 locations)
input wire [7:0] data_in, // 8-bit data input (for writing)
output reg [7:0] data_out // 8-bit data output (for reading)
);

// Declare a 16x8-bit RAM array (16 words, 8 bits each)

reg [7:0] ram [0:15];

// Asynchronous read logic

always @(*) begin
data_out = ram[addr_read]; // Read data from the RAM at the given read address
end

// Synchronous write logic (on the rising edge of the clock)

always @(posedge clk) begin
if (we) begin
ram[addr_write] <= data_in; // Write data to the RAM at the given write address
end
end

endmodule