1.

Justify the need for Real-Time Clock (RTC) and Watchdog Timer (WDT) in an Embedded
System. What is the significance of a Watchdog Timer?

In an embedded system, the Real-Time Clock (RTC) and Watchdog Timer (WDT) are essential
components that serve critical roles in functionality and reliability.

Real-Time Clock (RTC):

•
Applications: RTCs are used in various devices, including digital clocks, data loggers,
and automation systems. For example, in a smart meter, the RTC logs energy
consumption at precise intervals, allowing accurate billing based on time-of-day usage.

• Importance in Embedded Systems: By providing precise timekeeping independent of

the system clock, the RTC ensures scheduled events occur accurately and reliably, even
after power loss. This feature is crucial for systems that require consistent
timestamping, such as in medical devices or security systems.

Watchdog Timer (WDT):

 • Significance in Embedded Systems: The WDT is vital for systems deployed in remote
or mission-critical environments, where a system failure can lead to serious
consequences. For example, in an automotive control system, the WDT ensures the
system can recover from software hangs, preventing unsafe situations.

• Applications: WDTs are commonly used in industrial systems, medical devices,

automotive controls, and other applications requiring high reliability. By providing
automatic system recovery, the WDT ensures system stability and minimizes the need
for manual intervention.

2. Discuss the Operational and Non-operational Quality Attributes of Embedded Systems.

Which Quality Attribute Determines the Warranty for a Product?

Quality attributes in embedded systems define the system's performance, usability, reliability,
and overall quality. These attributes are broadly classified into operational and non-
operational categories.

Operational Quality Attributes:

1. Response Time: Measures the time taken for the system to respond to inputs or events.
It is crucial for real-time systems like braking systems in vehicles, where delays can lead
to safety risks.

2. Throughput: Represents the data-handling capacity of the system within a given time.
High throughput is important in systems like network routers or video streaming devices.

3. Reliability: Indicates the system's ability to perform consistently over time without
failure. This attribute is critical for applications requiring high uptime, such as
healthcare devices.
 4. Maintainability: Refers to the ease with which the system can be maintained or
repaired. Systems with long lifespans, like industrial machinery, require high
maintainability to minimize downtime.

5. Security: Ensures data protection against unauthorized access, particularly important

in applications handling sensitive data, such as banking and healthcare.

6. Safety: Prevents the system from causing harm to users or the environment, essential
for systems like medical devices and automotive controls.

Non-operational Quality Attributes:

1. Testability and Debug-ability: Allows for efficient testing and debugging, reducing time
to detect and correct issues, especially in complex systems.

2. Evolvability: Describes how easily the system can be updated or enhanced, vital for
systems that need regular feature updates.

3. Portability: Measures how easily the system can be adapted to different environments
or hardware platforms.

4. Time to Prototype and Market: Indicates the speed of development and production,
impacting competitive advantage.

5. Cost (Per Unit and Total Cost): Involves the cost of development, manufacturing, and
maintenance, influencing the system's economic feasibility.

Quality Attribute Determining Warranty: Reliability is the primary quality attribute that affects
a product's warranty. High reliability implies that the product will consistently perform well over
time, minimizing the likelihood of failures, which justifies a longer warranty period. A highly
reliable product assures the customer of its long-term performance, which is a key factor in
determining warranty duration.

3.Design an 8KX8 RAMmodule using 2KX8 RAM chips. The module should be connected on
an 8-bit processor witha 16-bit address bus, and occupy the address range starting from
the address A000. Show the circuit and the memory map.

Number of memory devices needed = 8K/2K = 4

Decoder needed=2X4

Number of address lines on each 2KX8 memory chip = 11

2^m=2K=2^1x 2^10=2^11(A0..A10)

Decoder needed=2X4

2 address lines are needed for the decoder. (A11..A12)

Number of address lines needed for the address selection

= 16- 11- 2 =3 (A13,A14A15)

4. Compare and contrast RISC vs. CISC processors/controllers, GPP vs. ASIP,
Microprocessor vs. Microcontroller, and embedded system classification based on
performance and functional requirements vs. microcontroller performance.

LPO ORP FSH

CDGITP
CCAPTRD

5. Mention the criteria for choosing a Microcontroller/Memory for an Embedded

System.
Choosing a microcontroller and memory for an embedded system requires careful
consideration of system requirements and constraints: (PPMPCE)

1. Power Efficiency: Low power consumption is crucial for battery-operated or low-power

applications, such as IoT devices and wearable technology.
2. Processing Speed and Performance: The microcontroller must have adequate
processing power to meet real-time requirements. High-performance applications, like
motor controls or multimedia processing, require higher clock speeds.
3. Memory Requirements: Sufficient memory (both Flash and RAM) is needed to store the
program code and data. The size depends on the application’s complexity and data-
handling needs.
4. Peripheral Requirements: Embedded systems often require specific peripherals like
ADCs, DACs, timers, and communication modules (e.g., UART, SPI, I2C) to interact with
sensors, actuators, and other components.
5. Cost and Availability: Budget constraints often dictate the choice of components.
Cost-effective solutions that meet the requirements are prioritized, and availability
ensures production scalability.
6. Environmental Tolerance: For industrial or automotive applications, selecting
components that can withstand extreme temperatures and physical stress is essential.

Each of these factors helps ensure that the microcontroller and memory meet the application’s
functional and operational requirements efficiently and cost-effectively.

6. Design the SRAM Cell Implementation for Writing a “1” into the Cell.

Static Random Access Memory (SRAM) is a type of volatile memory used for high-speed data
storage. An SRAM cell is typically implemented using a bistable circuit (latch) formed by two
cross-coupled inverters. Each SRAM cell can store a single bit of data (either “1” or “0”) by
holding it in a stable state until it is changed or power is removed.

Structure of a Basic SRAM Cell

1. Bistable Circuit: The basic storage element in an SRAM cell is a latch composed of two
cross-coupled inverters. This latch holds the data bit in a stable state.
2. Access Transistors: Two NMOS transistors are connected to the latch to control read
and write operations. These access transistors are connected to bit lines (BL and BL')
and are controlled by a word line (WL).
3. Bit Lines (BL and BL'): The bit lines are used to read from and write to the SRAM cell.
The bit lines are typically complementary (BL and BL') to provide higher stability and
noise resistance.
4. Word Line (WL): The word line is activated to enable the access transistors during read
and write operations.

Writing a “1” into the SRAM Cell

1. Pre-charge the Bit Lines: During a write operation, both bit lines (BL and BL') are pre-
charged to a specific voltage level.
2. Set BL and BL' Values: To write a “1” into the cell, the bit line (BL) is set to a high voltage
(logic “1”), and the complementary bit line (BL') is set to a low voltage (logic “0”).
3. Activate the Word Line (WL): When the WL is activated, the access transistors connect
the bit lines to the cell’s storage nodes.
4. Data Writing: The high voltage on BL causes one side of the cross-coupled inverters to
drive the node to “1” and the other node to “0”. This state is latched into the cell, storing
the bit value as “1”.
5. Deactivation: After the data is written, the WL is deactivated, and the access
transistors disconnect the cell from the bit lines. The cell now retains the “1” value until
overwritten or powered off.

This process ensures that a “1” is successfully written and stored in the SRAM cell, allowing for
stable, fast data access and low power consumption compared to DRAM.

7. An Embedded Engineer Needs to Make a Judicious Choice of the Memory Type for a
Specific Application. Analyze the Type to Be Used with an Example for Each Type.

Choosing the right memory type in an embedded system is crucial to meet application
requirements, such as speed, capacity, and power efficiency. Here’s an analysis of common
memory types, along with examples of their typical applications.

1. ROM (Read-Only Memory):

o Characteristics: Non-volatile memory, used to store firmware or application
code that doesn’t change during operation.
o Application Example: Used in appliances like washing machines to store
control firmware. Once programmed, the ROM remains unchanged, making it
ideal for read-only code that doesn’t require updates.
o Masked ROM (MROM): One-time programmable memory. Uses hardwired
technology for storing data. The device is factory programmed by masking and
metallization process according to the data provided by the end user. The
 primary advantage of MROM is low cost for high volume production. They are the
least expensive type of solid-state memory.
o Programmable Read Only Memory (PROM) / (OTP): Unlike MROM it is not pre-
programmed by the manufacturer. PROM/OTP has nichrome or polysilicon wires
arranged in a matrix, these wires can be functionally viewed as fuses . It is
programmed by a PROM programmer which selectively burns the fuses
according to the bit pattern to be stored. Fuses which are not blown/burned
represents a logic “1” whereas fuses which are blown/burned represents a logic
“0.The default state is logic “1”
2. EEPROM (Electrically Erasable Programmable ROM):
o Characteristics: Non-volatile, byte-addressable, and electrically erasable,
allowing selective reprogramming without removing the chip.
o Application Example: Commonly used for storing configuration data in network
devices, where settings need to be updated occasionally but retained across
power cycles.
3. Flash Memory:
o Characteristics: Non-volatile, block-erasable memory with fast read and write
access. Used for applications requiring a large data storage capacity with
occasional updates.
o Application Example: Widely used in smartphones and digital cameras to store
operating systems and media files. Flash is well-suited for applications needing
frequent read access and less frequent write operations.
4. SRAM (Static Random Access Memory):
o Characteristics: Volatile memory that retains data as long as power is supplied.
Faster than DRAM, with higher power consumption and lower density.
o Application Example: Used in cache memory in processors to store frequently
accessed data, allowing faster access and reducing latency in computations.
5. DRAM (Dynamic Random Access Memory):
o Characteristics: Volatile, high-density, and requires periodic refreshing to
retain data. Suitable for high-capacity storage needs.
o Application Example: Commonly used in main memory (RAM) in computers
and embedded systems requiring large data storage capacity for temporary
data.

8. Smart Card Design for Embedded Systems

Analyze the selection of i) Embedded hardware components. ii) Embedded software

components Required. iii) Input,Internal Signals, Events and Notifications.

Finally design Smart Card hardware system with component function and specifications
UNIT-2

1. With an example, illustrate how the use of a barrel shifter with an ALU improves
the power and flexibility of many data processing operations.

In ARM processors, the barrel shifter is a powerful component that works alongside the
Arithmetic Logic Unit (ALU) to perform efficient data manipulation in a single instruction. The
barrel shifter enhances the processor’s capability by allowing a shift or rotation operation to be
applied directly to an operand before it enters the ALU. This capability is integrated within many
ARM instructions, which means that the processor can perform a shift or rotate and an
arithmetic or logical operation simultaneously. This feature not only reduces the number of
instructions needed but also saves execution time and power, which is essential in embedded
systems.

The barrel shifter can perform a variety of operations, including:

• Logical Shift Left (LSL): Shifts bits to the left, filling in zeros on the right.
• Logical Shift Right (LSR): Shifts bits to the right, filling in zeros on the left.
• Arithmetic Shift Right (ASR): Shifts bits to the right, preserving the sign bit for signed
numbers.
• Rotate Right (ROR): Rotates bits to the right, wrapping bits around to the left.
• Rotate Right with Extend (RRX): Rotates bits to the right with the carry flag, useful in
handling carry operations in extended precision arithmetic.

Example: Suppose we need to multiply a value by 32 and then add another value. Normally,
multiplication could require several cycles if done using repeated additions or a dedicated
multiplier circuit. However, with a barrel shifter, multiplication by powers of 2 can be done in
one instruction using a left shift.

Consider this example in ARM assembly:

MOV R0, #5 ; Load 5 into R0

LSL R1, R0, #5 ; Shift R0 left by 5, equivalent to R0 * 32, and store in R1
ADD R2, R1, #10 ; Add 10 to the result and store in R2

In this example:

1. MOV loads the value 5 into register R0.

2. LSL (Logical Shift Left) shifts R0 left by 5 bits, effectively multiplying it by 25=322^5 =
3225=32. So 5 * 32 = 160 is stored in R1.
3. ADD adds 10 to 160, resulting in 170 in R2.

Here, the use of a barrel shifter saves instructions and cycles by performing the multiplication
in one shift operation instead of using multiple instructions or a dedicated multiplier. The barrel
shifter provides flexibility to handle various shift and rotate operations without extra cycles or
dedicated hardware, making it ideal for embedded applications where power and processing
efficiency are critical.

2. With a neat diagram explain the different general purpose registers of ARM processors.
In ARM processors, general-purpose registers play a critical role in executing instructions and
holding temporary data. ARM architectures, particularly the ARM Cortex-M and ARM7 families,
are designed with a set of general-purpose registers, as well as specific registers dedicated to
system control. ARM processors typically use a 32-bit architecture with 16 main registers,
labeled from R0 to R15.
Here’s an explanation of the different general-purpose registers in ARM, along with a diagram to
illustrate their roles:
Diagram of ARM General Purpose Registers
Here is a typical layout of the ARM processor registers:
markdown
Copy code
-------------------------------------
| Program Counter (R15) | <-- Holds address of next instruction
-------------------------------------
| Link Register (R14) | <-- Stores return address for subroutines
-------------------------------------
| Stack Pointer (R13) | <-- Points to top of the stack
-------------------------------------
| R12 | <-- General-purpose register
-------------------------------------
| R11 | <-- General-purpose register (frame pointer)
-------------------------------------
| R10 | <-- General-purpose register
-------------------------------------
| R9 | <-- General-purpose register
-------------------------------------
| R8 | <-- General-purpose register
-------------------------------------
| R7 | <-- General-purpose register
-------------------------------------
| R6 | <-- General-purpose register
-------------------------------------
| R5 | <-- General-purpose register
-------------------------------------
| R4 | <-- General-purpose register
-------------------------------------
| R3 | <-- General-purpose register
-------------------------------------
| R2 | <-- General-purpose register
-------------------------------------
| R1 | <-- General-purpose register
-------------------------------------
| R0 | <-- General-purpose register (function argument/return value)
-------------------------------------
Explanation of ARM General-Purpose Registers
1. R0–R12: These are general-purpose registers available for any kind of data storage or
computation during program execution.
o R0–R3: Often used to hold arguments for functions and to return results. For
instance, R0 typically stores the return value of functions.
 o R4–R12: Commonly used as general-purpose registers in computations and can
hold any intermediate values, loop counters, pointers, or flags as needed by the
program.
2. R13 (Stack Pointer):
o The Stack Pointer (SP) is used to point to the top of the stack, a memory area
used for temporary storage of data, return addresses, and local variables in
subroutines.
o It is crucial for managing function calls and returns, especially in applications
with recursive calls.
3. R14 (Link Register):
o The Link Register (LR) stores the return address for subroutines. When a
function is called, the address of the next instruction is stored in the LR, allowing
the program to return to this point after the function completes.
o In many ARM subroutine calls, the BL (branch with link) instruction
automatically places the return address in R14.
4. R15 (Program Counter):
o The Program Counter (PC) holds the address of the next instruction to execute.
ARM processors increment this register automatically after each instruction,
pointing to the next operation in sequence.
o In certain instructions, it can be modified directly to control program flow, such
as in branching instructions for loops or conditional statements.
Additional Points on ARM Register Organization
• Current Program Status Register (CPSR): Though not one of the general-purpose
registers, the CPSR holds flags that reflect the current state of the processor (such as
zero, negative, carry, overflow flags, and other control flags).
• Register Usage in Calling Conventions: In ARM’s Application Binary Interface (ABI),
registers are assigned specific roles:
o R0–R3 are used for parameter passing and function return values.
o R4–R11 are typically preserved across function calls, meaning if a function
modifies these registers, it must restore them before returning.

3. Differentiate ARM and Thumb instruction set features.

ARM processors support two primary instruction sets: the ARM instruction set and the Thumb
instruction set. Both sets are designed to maximize the processor’s efficiency and adaptability
in different scenarios, such as high-performance and low-power applications.
4. What are banked registers? Show how the banked registers are utilized when the
user mode changes to IRQ mode.

Banked registers are special registers in ARM architecture that exist as separate versions for
different processor modes (User, FIQ, IRQ, Supervisor, etc.). Banked registers allow the
processor to switch modes without saving and restoring specific registers, making mode
switching faster and more efficient. ARM has banked registers for critical registers, such as the
Stack Pointer (SP) and Link Register (LR), to avoid data corruption and ensure smooth
transitions between modes.

For example, in IRQ (Interrupt Request) mode, which is used to handle standard interrupts,
the ARM processor has dedicated registers:

• R13_irq (Stack Pointer for IRQ mode): Stores the IRQ mode stack pointer, allowing the
processor to use a separate stack for interrupts.
• R14_irq (Link Register for IRQ mode): Holds the return address for the IRQ mode,
preserving the return address from User mode.

When a transition from User mode to IRQ mode occurs:

1. The processor saves the User mode’s Program Counter (PC) and Current Program
Status Register (CPSR) in the banked Link Register (R14_irq) and Saved Program Status
Register (SPSR_irq).
2. It loads the IRQ mode stack pointer (R13_irq) to manage the interrupt’s call stack
separately.
3. After handling the interrupt, the processor uses the banked registers to restore the
previous state without affecting the User mode’s registers.

This approach improves interrupt handling speed and efficiency by isolating mode-specific
data, which is crucial for real-time applications where interrupts need to be processed
promptly without corrupting the state of the main program.

5. What are interrupts or exceptions? How are they handled in ARM processors?

Interrupts (or exceptions) are events that temporarily halt the normal execution flow of a
program to handle specific, often critical, conditions. They allow the processor to respond to
events, such as hardware signals, software requests, or system errors, by invoking a specific
routine, known as an interrupt handler or exception handler.

In ARM processors, interrupts are handled through predefined exception vectors, which are
specific memory locations associated with each interrupt type. Common exceptions in ARM
include Reset, Undefined Instruction, Supervisor Call (SVC), Prefetch Abort, Data Abort, IRQ
(Interrupt Request), and FIQ (Fast Interrupt Request).

Steps for Handling Interrupts in ARM:

 1. Save the Current State: When an interrupt occurs, ARM saves the current Program
Counter (PC) and Current Program Status Register (CPSR) into a Link Register (LR) and a
Saved Program Status Register (SPSR) associated with the current mode. This ensures
that the processor can return to its previous state after handling the interrupt.
2. Switch to the Appropriate Mode: ARM switches to a specific processor mode based on
the type of interrupt. For example, IRQs switch the processor to IRQ mode, while FIQs
switch to FIQ mode. Each mode has its own set of banked registers, allowing seamless
context switching.
3. Execute the Interrupt Handler: The processor loads the interrupt handler’s address
into the PC and begins executing the handler. This handler is a piece of code that
performs specific tasks based on the interrupt type.
4. Clear the Interrupt and Restore State: After the handler finishes, the processor clears
the interrupt request. Then, it restores the previous PC and CPSR from the saved
registers, allowing the interrupted program to resume execution as if uninterrupted.

ARM’s interrupt handling is efficient due to its use of banked registers, allowing quick context
switching and enabling real-time responsiveness essential for embedded systems.

7. Indicate how the CPSR that resides in the register file of the ARM core is used to
monitor and control internal operations.
The Current Program Status Register (CPSR) is a special-purpose register in ARM architecture
that monitors and controls the processor’s internal state and status. It contains flags and mode
bits that provide information on the processor’s current state and control specific operations.

Key Fields in CPSR:

1. Condition Flags:
o Negative (N): Set if the result of an arithmetic operation is negative.
o Zero (Z): Set if the result of an operation is zero.
o Carry (C): Set if an arithmetic operation results in a carry out or borrow.
o Overflow (V): Set if an arithmetic operation causes an overflow. These flags are
updated by ALU operations and are used by conditional instructions to
determine the execution flow based on computation results.
2. Mode Bits:
o M[4:0]: Indicates the current operating mode, such as User, FIQ, IRQ,
Supervisor, Abort, or Undefined.
o Interrupt Disable Bits (I and F): Control whether IRQ and FIQ interrupts are
enabled or disabled. Setting these bits prevents the processor from handling
specific types of interrupts, which is useful during critical code sections where
interrupts could disrupt operations.
3. Thumb State (T) Bit:
o Indicates whether the processor is in ARM (32-bit instructions) or Thumb (16-bit
instructions) state. This bit controls the instruction set the processor executes,
allowing flexibility between ARM and Thumb mode.

How CPSR Controls Operations:

• The condition flags (N, Z, C, V) directly affect the execution of conditional instructions
like BEQ (Branch if Equal) or BNE (Branch if Not Equal), enabling the processor to take
different execution paths based on computation results.
 • The mode bits (M[4:0]) control the current processor mode. When an exception occurs,
the CPSR mode bits change to reflect the new mode (e.g., IRQ mode for an interrupt),
ensuring the processor executes the correct exception handler.
• The interrupt disable bits allow specific code sections to be executed without the risk of
interruption, which is crucial for atomic operations.

By using CPSR to control these aspects, ARM processors efficiently handle internal states,
enabling robust, flexible, and responsive system operation.

8. Output for this

MOV R0, #0x02 ; Step 1

ADD R1, R0, R0 ; Step 2
MOV R2, #0x9B1D ; Step 3
MOV R3, #-0x281 ; Step 4
LSL R4, R1, #6 ; Step 5
LSL R5, R3, R0 ; Step 6
LSR R6, R2, #5 ; Step 7

Answer:

MOV R0, #0x02

• Operation: The MOV (move) instruction loads the immediate value 0x02 into register
R0.
• Result: R0 = 0x02

ADD R1, R0, R0

• Operation: The ADD instruction adds the value in R0 to itself and stores the result in R1.
• Calculation: R1 = R0 + R0 = 0x02 + 0x02 = 0x04
• Result: R1 = 0x04

MOV R2, #0x9B1D

• Operation: The MOV instruction loads the immediate value 0x9B1D into register R2.
• Result: R2 = 0x9B1D

MOV R3, #-0x281

• Operation: The MOV instruction loads the negative value -0x281 into register R3. ARM uses two’s
complement notation for negative numbers.
• Calculation: To represent -0x281 in a 32-bit register:
o First, find the positive hex value: 0x281 = 641 in decimal.
o Take the two’s complement: 0xFFFFFFFF - 0x281 + 1 = 0xFFFFFD7F.
• Result: R3 = 0xFFFFFD7F

LSL R4, R1, #6

• Operation: The LSL (Logical Shift Left) instruction shifts the bits of R1 left by 6 positions and
stores the result in R4.
 • Calculation: R4 = R1 << 6 = 0x04 << 6 = 0x0100
• Result: R4 = 0x0100

LSL R5, R3, R0

• Operation: This LSL instruction shifts the bits of R3 left by the number of positions
specified in R0 (which is 2).
• Calculation: R5 = R3 << 2 = 0xFFFFFD7F << 2
o The value 0xFFFFFD7F in binary is 1111 1111 1111 1111 1111 1101 0111 1111.
o Shifting this by 2 bits left results in 1111 1111 1111 1111 1111 0101 1111 1100 in
binary, which is 0xFFFFF5FC in hexadecimal.
• Result: R5 = 0xFFFFF5FC

LSR R6, R2, #5

• Operation: The LSR (Logical Shift Right) instruction shifts the bits of R2 right by 5
positions and stores the result in R6.
• Calculation: R6 = R2 >> 5 = 0x9B1D >> 5
o The value 0x9B1D in binary is 1001 1011 0001 1101.
o Shifting this by 5 bits right results in 0000 0100 1101 1000 in binary, which is
0x04D8 in hexadecimal.
• Result: R6 = 0x04D8

9. With respect to memory map in Cortex-M3, answer the following:

• a) What is the purpose of a memory map?

The memory map in Cortex-M3 defines specific address ranges for different types of
memory and peripherals. This map organizes memory into regions (e.g., Flash, SRAM,
peripherals), enabling efficient access and allocation for program code, data storage,
and device control.
• b) How much memory does the ARM Cortex-M3 have?
The ARM Cortex-M3 supports up to 4 GB of addressable memory space, segmented into
different regions like Code, SRAM, peripherals, and system control space.
• c) Contents of System Control Space:
System Control Space (SCS) contains special registers for system configuration,
exception handling, and system control. It includes the NVIC (Nested Vectored Interrupt
Controller), SysTick Timer, and system control registers.
• d) Memory Map Diagram for Cortex-M3 Partitioning: