K.S.

SCHOOL OF ENGINEERING AND MANAGEMENT, BANGALORE - 560109

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SESSION: 2024-2025 (ODD SEMESTER)
I Model QP SCHEME AND SOLUTION
SET-A

USN

Degree : B.E Semester : VII ‘A’ ‘B’

Branch : ECE Course Code : 21EC71
Course Title : Advanced VLSI Date : 3/01/2025
Duration : 180 Minutes Max Marks : 100

Sl.
Scheme and Solution Marks
No.

Module 3

Explain the verification process in VLSI design. Discuss the role of functional
coverage in enhancing the verification process.

The purpose of a test bench is to determine the correctness of the DUT.

This is accomplished by the following steps.
• Generate stimulus
• Apply stimulus to the DUT
• Capture the response
• Check for correctness
5(a) 6
• Measure progress against the overall verification goals ……3marks

Functional coverage is essential in modern hardware verification, as it ensures that

all specified functionalities of a design are thoroughly tested. It helps in identifying
gaps in test coverage, improving test quality, guiding resource allocation, and
providing a means of measuring the completeness of the verification process. By
focusing on the functional aspects of the design, functional coverage enables more
effective, efficient, and reliable verification, reducing the risk of undetected bugs and
improving the overall quality of the final product………3marks
Discuss the role of constrained random stimulus in design verification.

It is a testing method where random inputs are generated within specific constraints
to explore a wide range of scenarios while ensuring valid test conditions.

(b) 7

First in the above figure, notice that a random test often covers a wider space than a
directed one. This extra coverage may overlap other tests, or may explore new areas
that you did not anticipate. If these new areas find a bug, you are in luck! If the new
area is not legal, you need to write more constraints to keep random generation
 from creating illegal design functionality. Lastly, you may still have to write a few
directed tests to find cases not covered by any other constrained-random
tests……1.5 marks fig and 1.5 marks for explanation

Figure above shows the paths to achieve complete coverage. Start at the upper left
with basic constrained-random tests. Run them with many different seeds. When
you look at the functional coverage reports, find the holes where there are gaps in
the coverage. Then you make minimal code changes, perhaps by using new
constraints, or by injecting errors or delays into the DUT. Spend most of your time in
this outer loop, writing directed
tests for only the few features that are very unlikely to be
reached by random tests…..1.5 marks fig and 1.5 marks for explanation

Explain the use of associative arrays and queues in System Verilog with examples.
Associative array:
System Verilog offers associative arrays that store entries in a sparse matrix. This
means that while you can address a very large address space, System Verilog only
allocates memory for an element when you write to it.
Study program no. 10 given in activity. 4marks for program
Queue:

(c) 7

A queue is declared with word subscripts containing a dollar sign: [$]. The elements
of a queue are numbered from 0 to $. Sample 2.22 shows how you can add and
remove values from a queue using methods. Note that queue literals only have curly
braces, and are missing the initial apostrophe of array literals……….3marks for
 program

Write and explain a System Verilog code snippet using associative arrays.
module tb;
int array1 [int]; // An integer array with integer index
int array2 [string]; // An integer array with string index
string array3 [string]; // A string array with string index
initial begin
// Initialize each dynamic array with some values
array1 = '{ 1 : 22, 6 : 34 };
array2 = '{ "Ross" : 100, "Joey" : 60 };
array3 = '{ "Apples" : "Oranges", "Pears" : "44" };
6(a) // Print each array 7
$display ("array1 = %p", array1);
$display ("array2 = %p", array2);
$display ("array3 = %p", array3);
end
endmodule
Output:
array1 = '{0x1:22, 0x6:34}
array2 = '{"Joey":60, "Ross":100}
array3 = '{"Apples":"Oranges", "Pears":"44"}

How are fixed arrays and dynamic arrays different in System Verilog? Provide examples.
Dynamic arrays example

(b) 6

Describe the purpose of typedef and user-defined structures in System Verilog.

typedef is a System Verilog construct that allows you to define new, more meaningful,
or abstract data types from existing ones. It provides an alias to an existing type, making
the code easier to understand and maintain. One of the most useful types you can
create is an unsigned, 2-state, 32-bit integer.

(c) 7

In System Verilog you can create a structure using the struct statement. A user-defined
 structure (struct) is a composite data type that allows you to group different variables
(or fields) together into a single unit. These fields can have different data types and
represent various pieces of related information.

Module 4
Differentiate between tasks and functions in System Verilog. Provide suitable examples.
Function:
 A function must return a single value of a specific type. This return value can be
used in expressions.
 Functions cannot contain time-consuming operations, such as # (delays), wait, or
forever loops. They must execute in zero simulation time and return immediately.
 Functions can have input arguments, but they cannot have output or inout
arguments.
 Functions execute quickly and do not involve waiting on any events, time controls,
or other processes.

7(a) 7

Task:
 A task does not return a value directly. Instead, it performs actions or changes
states, and its results are typically passed via arguments.
 Tasks can contain time control operations, such as # (delays), wait, or even forever
loops. This makes them more flexible for modeling time-dependent behavior.
 Tasks can have input, output, and inout arguments, allowing more flexible
communication with the calling module.
 Tasks can have complex execution, potentially blocking the caller for a period of
time depending on time controls and waiting conditions.
 Describe the significance of separating the test bench and design in verification.

In an ideal world, all projects have two separate groups: one to create the design and
one to verify it. In the real world, limited budgets may require you to wear both hats.
Each team has its own set of specialized skills, such as creating synthesizable RTL
code, or figuring out new ways to find bugs in the design. These two groups each
read the original design specification and make their own interpretations. The
(b) 6
designer has to create code that meets that specification, whereas your job as the
verification engineer is to create scenarios where the design does not match its
description.
Using a module to hold the test bench often causes timing problems around driving and
sampling, so System Verilog introduces the program block to separate the test bench,
both logically and temporally.

Write and explain a System Verilog code that integrates an interface with assertions to
validate a basic logic circuit.
1. // Define an interface for the AND gate
interface and_gate_if(input logic a, b, output logic y);
// No need for internal logic here, just connect inputs and output
endinterface

2. // Define the design under test (DUT) - a simple 2-input AND gate
module and_gate(input logic a, b, output logic y);
assign y = a & b; // AND operation
endmodule

3. // Testbench to instantiate the design and perform assertions

module tb_and_gate;
(c) 7
// Declare signals for the interface
and_gate_if and_if_inst(a, b, y);

// Declare internal signals for connecting the interface

logic a, b, y;

// Instantiate the AND gate design

and_gate uut (
.a(a),
.b(b),
.y(y)
);

4. // Assertion to check the AND gate behavior

 // If both inputs are 1, output should be 1, else 0.
property and_gate_behavior;
@(posedge clk) disable iff (!reset) (a == 1 && b == 1) -> (y == 1);
@(posedge clk) disable iff (!reset) (a == 0 || b == 0) -> (y == 0);
endproperty

5. // Bind the assertions to the testbench

assert property(and_gate_behavior) else $fatal("Assertion failed: AND gate
behavior is incorrect!");

6. // Clock generation for the simulation

logic clk;
always #5 clk = ~clk; // Generate a clock with period 10 time units

// Reset signal
logic reset;
initial begin
reset = 1;
#10 reset = 0;
end

7. // Test stimulus generation

initial begin
// Initialize signals
a = 0;
b = 0;
#10;

// Apply test vectors

a = 0; b = 0; #10; // Expect y = 0
a = 0; b = 1; #10; // Expect y = 0
a = 1; b = 0; #10; // Expect y = 0
a = 1; b = 1; #10; // Expect y = 1

$finish; // End the simulation

end
endmodule
Explain the purpose and structure of interface constructs in System Verilog.
As designs grow in complexity, the connections between the blocks increase. Two RTL
blocks may share dozens of signals, which must be listed in the correct order for them to
communicate properly.
One mismatched or misplaced connection and the design will not work. You can reduce
errors by using the connect-by-name syntax, but this more than doubles your typing
burden. If it is a subtle error, such as swapping pins that only toggle occasionally, you
8(a) 7
may not notice the problem for some time.
Worse yet is when you add a new signal between two blocks. You have to edit not only
the blocks to add the new port but also the higher-level modules that wire up the
devices. Again, one wrong connection at any level and the design stops working.
The solution is the interface, the System Verilog construct that represents a bundle of
wires.
An interface is instantiated like a module but is connected to ports like a signal.
The first improvement to the arbiter example is to bundle the wires together into an
interface. Figure shows the test bench and arbiter, communicating using an interface.
Note how the interface extends into the two blocks, representing the drivers and
receivers that are functionally part of both the test and the DUT. The clock can be part
of the interface or a separate port.
 Discuss stimulus timing and its importance in System Verilog test benches.

At a cycle level, you need to drive and receive the synchronous signals at the proper
time in relation to the clock.
Drive too late or sample too early, and your test bench is off a cycle. Even within a single
time slot (for example, everything that happens at time 100ns), mixing design and test
bench events can cause a race condition, such as when a signal is both read and written
at the same time.
Do you read the old value, or the one just written?
Hence System Verilog has several constructs to help you control the timing of the
communication.

(b) 6

Discuss the role of assertions in System Verilog. Provide examples of immediate and
concurrent assertions
(c) 7
You can create temporal assertions about signals in your design to check their behavior
and temporal relationship with System Verilog Assertions (SVA). The simulator keeps
 track of what assertions have triggered, so you can gather functional coverage data on
them.
Immediate assertions:
An immediate assertion checks if an expression is true when the statement is executed.
Your test bench procedural code can check the values of design signals and
Test bench variables and take action if there is a problem. For example, if you have
asserted the bus request, you expect that grant will be asserted two cycles later. You
could use an if -statement as shown in Sample.

concurrent assertions:
The other type of assertion is the concurrent assertion that you can think of as a small
model that runs continuously, checking the values of signals for the entire simulation.

Module 5
What is randomization in System Verilog? Explain how random number generators can
be used for generating constrained inputs.
Randomization in System Verilog refers to the process of generating random values for
variables in a controlled manner, which is essential for verification, especially in
scenarios like constrained random testing.

9(a) 10

Illustrate the use of a cover group with a practical example. Explain how cross-coverage
enhances the verification process.
(b) To measure functional coverage, you begin with the verification plan and write an 10
executable version of it for simulation. In your System Verilog test bench, sample
the values of variables and expressions. These sample locations are known as cover
 points. Multiple cover points that are sampled at the same time (such as when a
transaction completes) are placed together in a cover group.

Cross Coverage:
A cover point records the observed values of a single variable or expression. You
may want to know not only what bus transactions occurred but also what errors
happened during those transactions, and their source and destination. For this you need
cross coverage that measures what values were seen for two or more cover points at
the same time. Note that when you measure cross coverage of a variable with N
values, and of another with M values, System Verilog needs N ´ M cross bins to store
all the combinations.
Explain the strategies for improving functional coverage during simulation.
Gather Information, not Data
Example: To thoroughly test a 1K FIFO, focus on measuring the read and write indices
rather than tracking all possible data combinations. The key corner cases are when the
FIFO is Empty and Full, as these represent critical states. Break down large ranges into
smaller, meaningful segments (e.g., memory vs. I/O space), and ensure that edge cases
like counter rollovers are tested.
Only Measure What you are Going to Use
10(a) Functional coverage provides a more efficient approach than waveform traces and code 6
coverage, although it may slow down simulations. Use simulation switches or
conditional compilation to control coverage data collection, but avoid suppressing
coverage as it leads to misleading reports with many 0% sections. Only gather coverage
data if you plan to analyze the final reports.
Measuring Completeness
If functional coverage is high but code coverage is low, your verification plan may be
inadequate, requiring updates and additional coverage points. Conversely, if code
coverage is high but functional coverage is low, the design might not be exercised in all
 interesting states, potentially needing formal verification tools. The goal is high code and
functional coverage, but always assesses bug rates—persistent bugs may indicate
missed scenarios, while a low bug rate might suggest a need for new verification
strategies.

Explain how automated bin creation in System Verilog enhances the efficiency and
accuracy of functional coverage analysis.

In SystemVerilog, functional coverage is tracked using covergroups and bins. A

covergroup defines the set of signals or conditions to be tracked, and the bins represent
different values or ranges of values within those signals. Automated bin creation allows
the simulation to dynamically generate bins based on the values observed during
simulation, rather than requiring manual bin definitions for every possible value or
condition.

Covergroup Definition: A covergroup is used to specify which signals or variables are

of interest for coverage collection. It contains one or more bins, which categorize the
possible values or conditions of the signal being monitored.

covergroup my_covergroup;
(b) coverpoint signal_1; // Coverage for signal_1 10
coverpoint signal_2; // Coverage for signal_2
endgroup
Bins: A bin is a specific condition or value range for a given signal that will be tracked for
coverage. The bins are automatically generated based on the signals' observed values
during the simulation.
covergroup my_covergroup;
coverpoint signal_1 {
bins bin_1 = {0, 1};
bins bin_2 = {2, 3};
}
endgroup
By dynamically generating bins for different signal values or ranges, it reduces the
manual effort involved in coverage model creation, ensures that all critical conditions
are tested, and produces more focused and actionable coverage reports.
Explain coverage types with necessary example.

Coverage is a generic term for measuring progress to complete design verification.

(c) 1. Code Coverage 4
The easiest way to measure verifi cation progress is with code coverage. Here you
are measuring how many lines of code have been executed (line coverage), which
paths through the code and expressions have been executed (path coverage),
 which single-bit variables have had the values 0 or 1 (toggle coverage), and which
states and transitions in a state machine have been visited (FSM coverage).

2. Functional Coverage
Functional coverage is tied to the design intent and is sometimes called “specification
coverage,” while code coverage measures how well you have tested the RTL
code and is known as, “implementation coverage.” These are two very different
metrics. Consider what happens if a block of code is missing from the design. Code
coverage cannot catch this mistake and could report that you have executed 100%
of the lines, but functional coverage will show that the functionality does not exist.

3. Assertion Coverage
Assertions are pieces of declarative code that check the relationships between design
signals, either once or over a period of time. These can be simulated along with the
design and test bench, or proven by formal tools. Sometimes you can write the
equivalent check using System Verilog procedural code, but many assertions are
more easily expressed using System Verilog Assertions (SVA).

Course Incharge HOD Principal

 K.S. SCHOOL OF ENGINEERING AND MANAGEMENT, BANGALORE - 560109
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SESSION: 2024-2025 (ODD SEMESTER)
III SESSIONAL SCHEME AND SOLUTION
SET-B
USN

Degree : B.E Semester : VII ‘A’ ‘B’

Branch : ECE Course Code : 21EC71
Course Title : Advanced VLSI Date : 12/12/2024
Duration : 60 Minutes Max Marks : 20

Sl.
Scheme and Solution Marks
No.
Tasks, functions and Void functions in SV with example.

1(a) 5

Function: 2marks, task: 2marks, void function: 1mark

An SV code to explain randomization problem of using signed variables over unsigned
variables.
Signed variables over unsigned variables: byte-signed, bit-unsigned

5
(b)
 Each 2.5 marks
Advanced argument types and default argument values with SV program example.
Advanced argument types: Passing arrays withy ref and const

Default argument values

2(a) 5

Advanced argument: 2marks, default argument : 3marks

An SV code to generate pseudo random number.

(b) 5

Test bench-arbiter with interface

SV code for the arbiter model using interface, test bench using interface, top-level with
interface.

3(a) 5
 Interface: 1mark, design: 2marks, test bench: 1mark, top module 1mark.
Randomization in SV with example code
Randomization is the process of making something random; System Verilog randomization is 5
(b)
the process of generating random values to a variable.
 Definition 1mark, example code 4marks
An SV code that specifies time values using $time and $realtime.
The system task $time returns an integer scaled to the time unit of the current module, but
missing any fractional units, while $realtime returns a real number with the complete time
value, including fractions.

4(a) 5

Code 4 marks and explanation 1 mark.

Any four random number functions with example.
$random
$urandom
$urandom_range
$dist_normal
(b) 5

List: 2marks, example 3marks

Course Incharge HOD Principal