Small Outline, 5 Lead, High

CMR, High Speed, Logic Gate

Optocouplers

Technical Data HCPL-M600

HCPL-M601
HCPL-M611

Features Description
• Surface Mountable These small outline high CMR,
• Very Small, Low Profile high speed, logic gate optocoup-
JEDEC Registered Package lers are single channel devices in
Outline a five lead miniature footprint.
They are electrically equivalent to
• Compatible with Infrared
the following Agilent
Vapor Phase Reflow and
optocouplers (except there is no
Wave Soldering Processes
output enable feature):
• Internal Shield for High
Common Mode Rejection
(CMR) SO-5 Package Standard DIP SO-8 Package
HCPL-M601: 10,000 V/µs at HCPL-M600 6N137 HCPL-0600
VCM = 50 V HCPL-M601 HCPL-2601 HCPL-0601
HCPL-M611: 15,000 V/µs at
VCM = 1000 V HCPL-M611 HCPL-2611 HCPL-0611
• High Speed: 10 Mbd
The SO-5 JEDEC registered (MO- Schottky-clamped transistor. The
• LSTTL/TTL Compatible
155) package outline does not internal shield provides a
• Low Input Current require “through holes” in a PCB. guaranteed common mode
Capability: 5 mA This package occupies transient immunity specification of
• Guaranteed ac and dc approximately one fourth the 5,000 V/µs for the HCPL-M601,
Performance over footprint area of the standard and 10,000 V/µs for the HCPL-
Temperature: -40°C to 85°C dual-in-line package. The lead M611.
• Recognized under the profile is designed to be com-
Component Program of U.L. patible with standard surface This unique design provides
(File No. E55361) for mount processes. maximum ac and dc circuit
Dielectric Withstand Proof isolation while achieving TTL
Test Voltage of 2500 Vac, 1 The HCPL-M600/01/11 optically compatibility. The optocoupler ac
Minute coupled gates combine a GaAsP and dc operational parameters are
light emitting diode and an guaranteed from -40°C to 85°C
integrated high gain photon allowing trouble free system
detector. The output of the performance.
detector I.C. is an Open-collector

CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken
in handling and assembly of this component to prevent damage and/or degradation which may be induced by
ESD.
 2

The HCPL-M600/01/11 are line receivers cannot tolerate, and Applications

suitable for high speed logic are recommended for use in • Isolated Line Receiver
interfacing, input/output extremely high ground or induced • Simplex/Multiplex Data
buffering, as line receivers in noise environments. Transmission
environments that conventional
• Computer-Peripheral
Interface
Outline Drawing (JEDEC MO-155) • Microprocessor System
Interface
• Digital Isolation for A/D, D/A
Conversion
ANODE 1 6 VCC • Switching Power Supply
4.4 ± 0.1
MXXX 7.0 ± 0.2 5 VOUT • Instrument Input/Output
(0.276 ± 0.008)
(0.173 ± 0.004) XXX Isolation
CATHODE 3 4 GND • Ground Loop Elimination
• Pulse Transformer
Replacement
0.4 ± 0.05
(0.016 ± 0.002)

3.6 ± 0.1*
(0.142 ± 0.004)

0.102 ± 0.102
2.5 ± 0.1 (0.004 ± 0.004) 0.15 ± 0.025
(0.098 ± 0.004) (0.006 ± 0.001)

7° MAX.
1.27 BSG 0.71 MIN.
(0.050) (0.028)

MAX. LEAD COPLANARITY

= 0.102 (0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
"Agilent" IS MARKED ON THE
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) UNDERSIDE OF THE PACKAGE

Pin Location (for reference only) Schematic

0.3
4.4 (0.01) + IF ICC
(0.17) VCC
1 6
IO
VO
5
1.3
(0.05)
2.5
(0.10)
–
GND
3 4
HCPL-M601/11 SHIELD
0.9
(0.04) 0.5 USE OF A 0.1 µF BYPASS CAPACITOR TRUTH TABLE
(0.02) MUST BE CONNECTED BETWEEN PINS (POSITIVE LOGIC)
7.2 6 AND 4 (SEE NOTE 1). LED OUTPUT
(0.28) ON L
OFF H
 3

Recommended Operating Conditions

Parameter Symbol Min. Max. Units
Input Current, Low Level IFL* 0 250 µA
Input Current, High Level IFH 5 15 mA
Supply Voltage, Output VCC 4.5 5.5 V
Fan Out (RL = 1 kΩ) N 5 TTL
Loads
Output Pull-Up Resistor RL 330 4,000 Ω
Operating Temperature TA -40 85 °C

* The off condition can also be guaranteed by ensuring that VF(off) ≤ 0.8 volts.

Absolute Maximum Ratings

(No Derating Required up to 85°C)
Storage Temperature .................................................... -55°C to +125°C
Operating Temperature .................................................. -40°C to +85°C
Forward Input Current - IF (see Note 2) ....................................... 20 mA
Reverse Input Voltage - VR ................................................................. 5 V
Supply Voltage - VCC (1 Minute Maximum) ........................................ 7 V
Output Collector Current - IO ........................................................ 50 mA
Output Collector Power Dissipation ............................................ 85 mW
Output Collector Voltage - VO ............................................................ 7 V
(Selection for higher output voltages up to 20 V is available)
Infrared and Vapor Phase Reflow Temperature ....................... see below

260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
TEMPERATURE – °C

180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12
TIME – MINUTES

Maximum Solder Reflow Thermal Profile.

(Note: Use of Non-Chlorine Activated Fluxes is Recommended.)
 4

Insulation Related Specifications

Parameter Symbol Value Units Conditions
Min. External Air Gap L(IO1) ≥5 mm Measured from input terminals
(Clearance) to output terminals
Min. External Tracking Path L(IO2) ≥5 mm Measured from input terminals
(Creepage) to output terminals
Min. Internal Plastic Gap 0.08 mm Through insulation distance
(Clearance) conductor to conductor
Tracking Resistance CTI 175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group (per DIN VDE 0109) IIIa Material Group DIN VDE 0109

Electrical Specifications
Over recommended temperature (TA = -40°C to 85°C) unless otherwise specified. (See note 1.)

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Input Threshold ITH 2 5 mA VCC = 5.5 V, IO ≥13 mA, 13
Current VO = 0.6 V
High Level Output IOH 5.5 100 µA VCC = 5.5 V, VO = 5.5 V 1
Current IF = 250 µA
Low Level Output VOL 0.4 0.6 V VCC = 5.5 V, IF = 5 mA, 2, 4,
Voltage IOL (Sinking) = 13 mA 5, 13
High Level Supply ICCH 4 7.5 mA VCC = 5.5 V, IF = 0 mA,
Current
Low Level Supply ICCL 6 10.5 VCC = 5.5 V, IF = 10 mA,
Current
Input Forward VF 1.4 1.75 V TA = 25°C 3
Voltage 1.5
1.3 1.85 IF = 10 mA
Input Reverse BVR 5 IR = 10 µA
Breakdown Voltage
Input Capacitance CIN 60 pF VF = 0V, f = 1 MHz
Input Diode ∆VF /∆TA -1.6 mV/°C IF = 10 mA 12
Temperature
Coefficient
Input-Output VISO 2500 VRMS RH ≤ 50%, t = 1 min. 3, 4
Insulation
Resistance RI-O 1012 Ω VI-O = 500 V 3
(Input-Output)
Capacitance CI-O 0.6 pF f = 1 MHz 3
(Input-Output)

*All typicals at TA = 25°C, VCC = 5 V.

 5

Switching Specifications
Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
Device
Parameter Symbol HCPL- Min. Typ.* Max. Unit Test Conditions Fig. Note
Propagation tPLH 20 48 75 ns TA = 25°C 6, 7 5
Delay Time
to High 100 8
Output Level
Propagation tPHL 25 50 75 TA = 25°C 6, 7 6
Delay Time
to Low 100 RL = 350 Ω 8
Output Level
Propagation tPSK 40 10,
Delay Skew 11
Pulse Width |tPHL - tPLH| 3.5 35 CL = 15 pF 9 10
Distortion
Output Rise trise 24
Time 10
(10%-90%)
Output Fall tfall 10
Time 10
(10%-90%)
Common |CM H| M600 10,000 V/µs VCM = 10 V VO(min) = 2 V 11 7, 9
Mode RL = 350 Ω
M601 5,000 10,000 VCM = 50 V
Transient IF = 0 mA
Immunity at M611 10,000 15,000 VCM = 1000 V TA = 25°C
High Output
Level
Common |CM H| M600 10,000 VCM = 10 V VO(max) = 0.8 V 11 8, 9
Mode RL = 350 Ω
M601 5,000 10,000 VCM = 50 V
Transient IF = 7.5 mA
Immunity at M611 10,000 15,000 VCM = 1000 V T A = 25°C
Low Output
Level
*All typicals at TA = 25°C, VCC = 5 V.
Notes:
1. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler. The total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 20 mA.
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 VRMS for 1 second
(Leakage detection current limit, II-O ≤ 5 µA).
5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., VOUT > 2.0 V).
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., VOUT > 0.8 V).
9. For sinusoidal voltages, (|dVCM|/dt)max = πfCMVCM(p-p).
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the worst case operating condition range.
 6

VOL – LOW LEVEL OUTPUT VOLTAGE – V

IOH – HIGH LEVEL OUTPUT CURRENT – µA

15 0.5 100
VCC = 5.5 V VCC = 5.5 V TA = 25°C

IF – FORWARD CURRENT – mA
VO = 5.5 V IF = 5.0 mA
IF = 250 µA 10 IF
0.4
10 IO = 12.8 mA +
1.0 VF
IO = 16 mA –
0.3
0.1
5
0.2 IO = 6.4 mA
IO = 9.6 mA 0.01

0 0.1 0.001
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 1.10 1.20 1.30 1.40 1.50 1.60
TA – TEMPERATURE – °C TA – TEMPERATURE – °C VF – FORWARD VOLTAGE – VOLTS

Figure 1. High Level Output Figure 2. Low Level Output Voltage Figure 3. Input Diode Forward
Current vs. Temperature. vs. Temperature. Characteristic.

6
VCC = 5 V
TA = 25 °C
VO – OUTPUT VOLTAGE – V

4
RL = 350 Ω
3 PULSE GEN.
RL = 1 KΩ ZO = 50 Ω
tf = tr = 5 ns +5 V
2
RL = 4 KΩ IF
1 1 VCC 6
RL
0.1µF
BYPASS OUTPUT VO
0 5 MONITORING
0 1 2 3 4 5 6 NODE
*CL
IF – FORWARD INPUT CURRENT – mA INPUT
MONITORING 3 4
NODE GND

Figure 4. Output Voltage vs. RM

Forward Input current.

*CL IS APPROXIMATELY 15 pF WHICH INCLUDES

PROBE AND STRAY WIRING CAPACITANCE.
IOL – LOW LEVEL OUTPUT CURRENT – mA

80
VCC = 5.0 V
VOL = 0.6 V IF = 7.5 mA
INPUT
IF = 3.75 mA
60 IF
IF = 10 mA, 15 mA tPHL tPLH

OUTPUT
40
VO 1.5 V
IF = 5.0 mA

20

Figure 6. Test Circuit for tPHL and t PLH.

0
-60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C

Figure 5. Low Level Output Current

vs. Temperature.
 7

PWD – PULSE WIDTH DISTORTION – ns

100 105 40
VCC = 5.0 V VCC = 5.0 V
tP – PROPAGATION DELAY – ns

IF = 7.5 mA RL = 4 kΩ

tP – PROPAGATION DELAY – ns
TA = 25°C
80 tPLH , RL = 4 KΩ 90 tPLH , RL = 4 KΩ 30
VCC = 5.0 V
tPHL , RL = 350 Ω IF = 7.5 mA
1 KΩ
60 4 KΩ 75 20

tPLH , RL = 350 Ω RL = 350 kΩ

40 tPLH , RL = 1 KΩ 60 10
tPLH , RL = 1 KΩ
tPLH , RL = 350 Ω
20 45 0
tPHL , RL = 350 Ω
1 KΩ RL = 1 kΩ
4 KΩ
0 30 -10
-60 -40 -20 0 20 40 60 80 100 5 7 9 11 13 15 -60 -40 -20 0 20 40 60 80 100

TA – TEMPERATURE – °C IF – PULSE INPUT CURRENT – mA TA – TEMPERATURE – °C

Figure 7. Propagation Delay vs. Figure 8. Propagation Delay vs. Figure 9. Pulse Width Distortion vs.
Temperature. Pulse Input Current. Temperature.

VCC = 5.0 V tRISE

IF = 7.5 mA tFALL
tr, tf – RISE, FALL TIME – ns

IF

B +5 V
300 RL = 4 kΩ 1 VCC 6
0.1 µF 350 Ω
290 A BYPASS OUTPUT VO
60 5 MONITORING
RL = 1 kΩ VFF NODE
40
3 4
GND
20 RL = 350 Ω

RL = 350 Ω, 1 kΩ, 4 kΩ
0 _
-60 -40 -20 0 20 40 60 80 100 +
TA – TEMPERATURE – °C PULSE
GENERATOR
ZO = 50 Ω

Figure 10. Rise and Fall Time vs.

Temperature. VCM (PEAK)
VCM
0V
SWITCH AT A: IF = 0 mA
5V CMH
VO VO (MIN.)
-2.4 SWITCH AT B: IF = 7.5 mA
TEMPERATURE COEFFICIENT – mV/°C

VO VO (MAX.)
dVF/dT – FORWARD VOLTAGE

-2.2 0.5 V CML

-2.0
Figure 11. Test Circuit for Common
-1.8 Mode Transient Immunity and
Typical Waveforms.
-1.6

-1.4

-1.2
0.1 1 10 100
IF – PULSE INPUT CURRENT – mA

Figure 12. Temperature Coefficient

for Forward Voltage vs. Input
Current.
 8

Propagation Delay, Pulse- being sent through a group of only one edge were used, the
Width Distortion and optocouplers, differences in clock signal would need to be
Propagation Delay Skew propagation delays will cause the twice as fast.
Propagation delay is a figure of data to arrive at the outputs of the
merit which describes how optocouplers at different times. If Propagation delay skew
quickly a logic signal propagates this difference in propagation represents the uncertainty of
through a system. The propaga- delays is large enough, it will where an edge might be after
tion delay from low to high (tPLH) determine the maximum rate at being sent through an
is the amount of time required for which parallel data can be sent optocoupler. Figure 16 shows
an input signal to propagate to through the optocouplers. that there will be uncertainty in
the output, causing the output to both the data and the clock lines.
change from low to high. Propagation delay skew is defined It is important that these two
Similarly, the propagation delay as the difference between the areas of uncertainty not overlap,
from high to low (tPHL) is the minimum and maximum otherwise the clock signal might
amount of time required for the propagation delays, either tPLH or arrive before all of the data
input signal to propagate to the tPHL, for any given group of outputs have settled, or some of
output, causing the output to optocouplers which are operating the data outputs may start to
change from high to low (see under the same conditions (i.e., change before the clock signal
Figure 7). the same drive current, supply has arrived. From these
voltage, output load, and considerations, the absolute
Pulse-width distortion (PWD) operating temperature). As minimum pulse width that can be
results when tPLH and tPHL differ in illustrated in Figure 15, if the sent through optocouplers in a
value. PWD is defined as the inputs of a group of optocouplers parallel application is twice tPSK. A
difference between tPLH and tPHL are switched either ON or OFF at cautious design should use a
and often determines the maxi- the same time, tPSK is the slightly longer pulse width to
mum data rate capability of a difference between the shortest ensure that any additional
transmission system. PWD can propagation delay, either tPLH or uncertainty in the rest of the
be expressed in percent by tPHL, and the longest propagation circuit does not cause a problem.
dividing the PWD (in ns) by the delay, either tPLH or tPHL.
minimum pulse width (in ns) The tPSK specified optocouplers
being transmitted. Typically, PWD As mentioned earlier, tPSK can offer the advantages of
on the order of 20-30% of the determine the maximum parallel guaranteed specifications for
minimum pulse width is tolerable; data transmission rate. Figure 11 propagation delays, pulse-width
the exact figure depends on the is the timing diagram of a typical distortion and propagation delay
particular application (RS232, parallel data application with both skew over the recommended
RS422, T-1, etc.). the clock and the data lines being temperature, and input current,
sent through optocouplers. The and power supply ranges.
Propagation delay skew, tPSK, is figure shows data and clock
an important parameter to signals at the inputs and outputs
consider in parallel data appli- of the optocouplers. To obtain the
cations where synchronization of maximum data transmission rate,
signals on parallel data lines is a both edges of the clock signal are
concern. If the parallel data is being used to clock the data; if
 9

ITH – INPUT THRESHOLD CURRENT – mA

6
VCC = 5.0 V 5V 6
VCC1 5V
VO = 0.6 V VCC 2
5
470 390 Ω
4 IF 5
1

3 RL = 350 Ω *D1
RL = 1 kΩ VF 0.1 µF
BYPASS
2 3 4
GND 1 GND 2
SHIELD
1 1 2
RL = 4 kΩ

0 * DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED

-60 -40 -20 0 20 40 60 80 100 FOR UNITS WITH OPEN COLLECTOR OUTPUT.
TA – TEMPERATURE – °C

Figure 13. Input Threshold Current Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
vs. Temperature.

DATA

IF INPUTS
50%
CLOCK

VO 1.5 V

DATA
IF 50%

OUTPUTS
tPSK
VO 1.5 V CLOCK

tPSK
tPSK

Figure 15. Illustration of Figure 16. Parallel Data Transmission Example.

Propagation Delay Skew – tPSK.
[Link]
Data subject to change.
Copyright © 1999 Agilent Technologies
Obsoletes 5091-9635E (10/93)
5966-4942E (11/99)