8086
Microprocessor Overview
First 16- bit processor released by
INTEL in the year 1978
Originally HMOS, now manufactured
using HMOS III technique
Approximately 29, 000 transistors, 40
pin DIP, 5V supply
Does not have internal clock; external
asymmetric clock source with 33%
duty cycle
20-bit address to access memory can
address up to 2 20 = 1 megabytes of
memory space.
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Pins and signals
8086
Microprocessor Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are
multiplexed with data.
When AD lines are used to transmit
memory address the symbol A is used
instead of AD, for example A0-A15.
When data are transmitted over AD lines
the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are
multiplexed with status signals
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8086
Microprocessor Pins and Signals Common signals
BHE (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the most
significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation.
It is an output signal.
It is active when low.
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8086
Microprocessor Pins and Signals Common signals
READY
This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.
The signal made available by the devices
is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high. 10
8086
Microprocessor Pins and Signals Common signals
RESET (Input)
Causes the processor to immediately
terminate its present activity.
The signal must be active HIGH for at
least four clock cycles.
CLK
The clock input provides the basic timing
for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.
INTR Interrupt Request
This is a triggered input. This is sampled
during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.
This signal is active high and internally
synchronized. 11
12
8086
Microprocessor Pins and Signals Min/ Max Pins
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.
In the minimum mode of operation the
microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
In the maximum mode the 8086 can work
in multi-processor or co-processor
configuration.
Minimum or maximum mode operations
are decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in
minimum mode otherwise it operates in
Maximum mode.
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8086
Microprocessor Pins and Signals Minimum mode signals
(Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
(Data Enable) Output signal from the processor
used as out put enable for the transceivers
ALE (Address Latch Enable) Used to demultiplex the
address and data lines using external latches
Used to differentiate memory access and I/O
access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.
Write control signal; asserted low Whenever
processor writes data to memory or I/O port
(Interrupt Acknowledge) When the interrupt
request is accepted by the processor, the output is
low on this line.
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8086
Microprocessor Pins and Signals Minimum mode signals
HOLD Input signal to the processor form the bus masters
as a request to grant the control of the bus.
Usually used by the DMA controller to get the
control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the
processor to the bus master requesting the control
of the bus through HOLD.
The acknowledge is asserted high, when the
processor accepts HOLD.
15
8086
Microprocessor Pins and Signals Maximum mode signals
Status signals; used by the 8086 bus controller to
generate bus timing and control signals. These are
decoded as shown.
16
8086
Microprocessor Pins and Signals Maximum mode signals
(Queue Status) The processor provides the status
of queue in these lines.
The queue status can be used by external device to
track the internal status of the queue in 8086.
The output on QS0 and QS1 can be interpreted as
shown in the table.
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8086
Microprocessor Pins and Signals Maximum mode signals
18
Architecture
8086
Microprocessor Architecture
Execution Unit (EU) Bus Interface Unit (BIU)
EU executes instructions that have BIU fetches instructions, reads data
already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
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8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Dedicated Adder to generate
20 bit address
Four 16-bit segment
registers
Code Segment (CS)
Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Segment Registers >> 21
8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Segment
Registers
8086‟s 1-megabyte The 8086 can directly Programs obtain access
memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.
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8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Segment Code Segment Register
Registers
16-bit
CS contains the base or start of the current code segment;
IP contains the distance or offset from this address to the
next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically
shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the
contents of the CS register multiplied by 16 and then offset
is added provided by the IP.
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8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Segment Data Segment Register
Registers
16-bit
Points to the current data segment; operands for most
instructions are fetched from this segment.
The 16-bit contents of the Source Index (SI) or
Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.
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8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Segment Stack Segment Register
Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the
Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack
address is calculated from the Stack segment (SS) and the
Base Pointer (BP).
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8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Segment Extra Segment Register
Registers
16-bit
Points to the extra segment in which data (in excess of
64K pointed to by the DS) is stored.
String instructions use the ES and DI to determine the 20-
bit physical address for the destination.
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8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Segment Instruction Pointer
Registers
16-bit
Always points to the next instruction to be executed within
the currently executing code segment.
So, this register contains the 16-bit offset address pointing
to the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution
of the next instruction takes place.
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8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
This is done in order to
speed up the execution
by overlapping
instruction fetch with
execution.
This mechanism is known
as pipelining.
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8086
Architecture Execution Unit (EU)
Microprocessor
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
16-bit ALU for
performing arithmetic
and logic operation
Four general purpose
registers(AX, BX, CX, DX);
Pointer registers (Stack
Pointer, Base Pointer);
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 29
DX can be used as DH and DL
8086
Architecture Execution Unit (EU)
Microprocessor
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,
and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /
outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or
AL.
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8086
Architecture Execution Unit (EU)
Microprocessor
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,
and BH contains the high-order byte.
This is the only general purpose register whose contents
can be used for addressing the 8086 memory.
All memory references utilizing this register content for
addressing use DS as the default segment register.
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8086
Architecture Execution Unit (EU)
Microprocessor
EU Counter Register (CX)
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of
the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the
contents of CX as a counter.
Example:
The instruction LOOP START automatically decrements
CX by 1 without affecting flags and will check if [CX] =
0.
If it is zero, 8086 executes the next instruction;
otherwise the 8086 branches to the label START.
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8086
Architecture Execution Unit (EU)
Microprocessor
EU
Registers
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8086
Architecture Execution Unit (EU)
Microprocessor
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during
execution of instructions that involve the stack segment in
the external memory.
SP contents are automatically updated (incremented/
decremented) due to execution of a POP or PUSH
instruction.
BP contains an offset address in the current SS, which is
used by instructions utilizing the based addressing mode.
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8086
Architecture Execution Unit (EU)
Microprocessor
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
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8086
Architecture Execution Unit (EU)
Microprocessor
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
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8086
Architecture Execution Unit (EU)
Microprocessor
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 37
8086
Microprocessor Architecture
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
Sl.No. Type Register width Name of register
1 General purpose register 16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register
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8086
Microprocessor Architecture Registers and Special Functions
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic
operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic
operations
BX Base register Used to hold base value in base addressing mode
to access memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE
and LOOP instructions
DX Data Register Used to hold data for multiplication and division
operations
SP Stack Pointer Used to hold the offset address of top stack
memory
BP Base Pointer Used to hold the base value in base addressing
using SS register to access data from stack
memory
SI Source Index Used to hold index value of source operand (data)
for string instructions
DI Data Index Used to hold the index value of destination
operand (data) for string operations 39
