MP5461

Dual Input, 4-Switch Integrated

Buck-Boost Converter
with Input ORing and Selection

DESCRIPTION FEATURES
The MP5461 is a dual input, 4-switch, integrated  Dual Input ORing Switches:
buck-boost converter. It is capable of regulating o 4.2V to 5.5V Input Voltage Range for
the output voltage from 4.2V to 5.5V VIN1 and VIN1
2.5V to 5.5V VIN2. The VIN1 can support up to o Supports 22V Voltage Stress for VIN1
22V input voltage but is not functional after o 5.75V OVP Shutdown for VIN1
>5.75V. o 2.5V to 5.5V Input Voltage Range for
VIN2
The MP5461 has two auto-ORing switches from o Fast Reverse Block within 2μs
VIN1 and VIN2 to achieve a stable input for the o 1A Current Capability for Each Channel
buck-boost converter. The two sets of ORing o Soft-Start Control
MOSFETs are integrated. If one channel power o Fast SCP (Short-Circuit Protection) on
source falls, the fast turn-off protection OR_OUT
minimizes the reverse current. o Power-Path Selection Input
The buck-boost converter can operate from an o Power-Path Status Indication
input voltage above, equal to, or below the  Buck-Boost Converter
output voltage. It uses current-mode control with o 1.8MHz Switching Frequency for CCM
1.8MHz fixed PWM frequency to optimize o 3.3V Fixed Output Voltage
stability and transient response. In a light-load o 500mA Continuous Output Current
condition, it enters PFM mode to get high light- o 1ms Soft-Start Time
load efficiency. Integrated MOSFETs minimize o Auto PFM/PWM Mode
the solution size while maintaining high o Output Over-Voltage Protection
efficiency. o Hiccup Over-Current Protection
 1µA Shutdown Current
Fault protection includes VIN1 OVP shutdown,
output hiccup current limiting, and thermal  200µA Quiescent Current
shutdown.  Active Low System EN Pin
 EN to OR_OUT Start-Up Delay 300μs
The MP5461 is available in a tiny CSP-12  Over-Temperature Shutdown
(1.4mmx1.8mm) package.  Available in a Wafer Level Chip Scale
Packaging: CSP-12(1.4mmx1.8mm)
APPLICATIONS
 USB-C Cable
 VCONN Powered USB Device
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.

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 MP5461 – DUAL INPUT, INTEGRATED BUCK-BOOST

TYPICAL APPLICATION
L1 Efficiency vs. Load Current
1µH
VIN1 VOUT 100
4.2V-5.5V SW1 SW2
3.3V/0.5A
95
IN1
C1A OUT
1µF C2A C2B
90

EFFICIENCY (%)
22µF 22µF
85
VIN2
2.5V-5.5V
MP5461 80
IN2 OR_OUT
C1B C4
1µF
75
10µF
70 VIN2=5V
VCC VIN2=3.3V
R1 SEL VCC
65 VIN2=2.7V
10k C3
STATUS EN AGND GND
1µF 60
0.001 0.01 0.1 1
LOAD CURRENT (A)

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ORDERING INFORMATION
Part Number* Package Top Marking
MP5461GC CSP-12 (1.4mmx1.8mm) See Below
* For Tape & Reel, add suffix –Z (e.g. MP5461GC–Z).

TOP MARKING

JG: Product code of MP5461GC

Y: Year code
LLL: Lot number

PACKAGE REFERENCE
TOP VIEW

1 2 3

OR_ SW
A IN1 OUT 1

AG GN
B IN2 ND D

VC SW
C C
EN
2

SE STAT OU
D L US T

CSP-12 (1.4mmx1.8mm)

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PIN FUNCTIONS
CSP-12
Name Description
Pin #
VIN1 supply voltage. The MP5461 operates from a 4.2V to 5.5V VIN1 voltage
A1 IN1 and supports a 22V input voltage, but it is not functional >5.75V. CIN1 prevents
large voltage spikes at the input. Place CIN1 as close to the IC as possible.
IN1, IN2 ORing output. Also functions as the buck-boost input pin. Use a 10μF
A2 OR_OUT
or larger capacitor for decoupling.
Switch1. The first half-bridge switch node is connected to SW1. Connect an
A3 SW1
inductor between SW1 and SW2.
VIN2 supply voltage. The MP5461 operates from a 2.5V to 5.5V VIN2 voltage.
B1 IN2 CIN2 prevents large voltage spikes at the input. Place CIN2 as close to the IC
as possible.
Analog ground. Connect AGND to VCC capacitor's GND node by a Kelvin
B2 AGND
sense trace.
Power ground. Reference ground of the regulated output voltage. GND
B3 GND requires extra care during PCB layout. Connect to GND with copper traces and
vias.
C1 VCC Internal 5V LDO regulator output. Decouple with a 1µF capacitor.
On/off control for entire chip. EN is active low. Drive EN high to turn off the
C2 EN chip. Drive EN low or float to turn on the device. It has an internal 600kΩ pull-
down resistor to ground.
Switch2. The internal second half-bridge switch node is connected to SW2.
C3 SW2
Connect an inductor between SW1 and SW2.
Power path select input. If SEL=Low or is floated, VIN1 is selected; If
SEL=High, VIN2 is selected. The MP5461 will auto select the available power
D1 SEL
path if only one supply is available. It has an internal 600kΩ pull-down resistor
to ground.
Status indication. Open drain output. Indicates if the VIN1 or VIN2 channel is
D2 STATUS
selected. Refer to the truth table.
D3 OUT Output pin.

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Thermal Resistance (4) θJA θJC

ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage (VIN1) ....................-0.3V to +24V CSP-12 (1.4mmx1.8mm) ....... 110 ..... 12... C/W
VSW1..................................................................... Notes:
–0.3V (-5V for <10ns) to VOR_OUT + 0.3V(10V for 1) Exceeding these ratings may damage the device.
<10ns) 2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
VSW2..................................................................... ambient thermal resistance θJA, and the ambient temperature
–0.3V (-5V for <10ns) to VOUT + 0.3V (10V for TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
<10ns) (MAX)-TA)/θJA. Exceeding the maximum allowable power
VEN, VSEL,VSTATUS ......................... –0.3V to +5.5V dissipation will cause excessive die temperature, and the
All Other Pins ................................. –0.3V to +6V regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
Continuous Power Dissipation (TA = +25°C) (2) damage.
CSP-12 (1.4mmx1.8mm) ......................... 1.14W 3) The device is not guaranteed to function outside of its
operating conditions.
Junction Temperature ...............................150C 4) Measured on JESD51-7, 4-layer PCB. The value of θJA given
Lead Temperature ....................................260C in this table is only valid for comparison with other packages
Storage Temperature .............. –65C to +150C and cannot be used for design purposes. These values were
calculated in accordance with JESD51-7 and simulated on a
specified JEDEC board. They do not represent the
Recommended Operating Conditions (3) performance obtained in an actual application.
Operation Input Voltage VIN1 ......... 4.2V to 5.5V
Operation Input Voltage VIN2 ......... 2.5V to 5.5V
Output Current ........................................ 500mA
Operating Junction Temp. (TJ). -40°C to +125°C

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ELECTRICAL CHARACTERISTICS
VIN1 = 5V, VIN2=5V, VEN = 0V, TJ = -40°C to +125°C(5), unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
VEN=5V, VIN1=5V, VIN2=float,
IIN1 1 5 μA
TJ = +25°C
Supply current (Shutdown)
VEN=5V, VIN1=float, VIN2=5V,
IIN2 1 5 μA
TJ = +25°C
VEN=0V, VIN1=5V, VIN2=float, No
IQ1 210 260 μA
switching, TJ = -40°C to +85°C
Supply current (Quiescent)
VEN=0V, VIN1=float, VIN2=5V, No
IQ2 185 230 μA
switching, TJ = -40°C to +85°C
EN logic high input VEN_H Disable Part 1.2 V
EN logic low input VEN_L Enable Part 0.4 V
EN to ground resistance REN 600 kΩ
Thermal shutdown (6)
TSTD 150 C
Thermal hysteresis (6)
THYS 20 C
VCC regulator VCC VIN1=5.5V 4.5 5 5.5 V
VCC load regulation VCC_RG ICC=0-5mA 3 5 %
Dual Input ORing Switches
VIN1 under-voltage lockout
IN1UVVth 3.6 3.9 4.15 V
threshold rising
VIN1 under-voltage lockout
IN1UVHYS 400 mV
threshold hysteresis
VIN2 under-voltage lockout
IN2UVVth 2.05 2.25 2.45 V
threshold rising
VIN2 under-voltage lockout
IN2UVHYS 150 mV
threshold hysteresis
EN=0 to OR_OUT>90%, IN1=5V,
EN to OR_OUT startup tEN_DLY1 300 μs
IN2=0
delay
tEN_DLY2 IN2=5V, IN1=0 300 μs
Input over-voltage rising VOVP_R IN1 only 5.51 5.75 6.1 V
OVP recovery threshold VOVP_F IN1 only 5.5 V
Switch1 on resistance RDSON1 VCC=5V 160 mΩ
Switch2 on resistance RDSON2 VCC=5V 90 mΩ
IN1 to OR_OUT regulation
VREG1 Io=1mA, Io=100mA 5 40 100 mV
voltage
IN2 to OR_OUT regulation
VREG2 Io=1mA, Io=100mA 5 40 100 mV
voltage
Reverse voltage turn-off
tRV 2 μs
response time(7)
SEL logic high input VSEL_H VIN2 is selected 1.2 V
SEL logic low input VSEL_L VIN1 is selected 0.4 V
SEL to ground resistance RSEL 600 kΩ
STATUS pin leakage ISTA_LKG Pull-up with 5V 1 μA
STATUS low voltage VSTA_Low Sink 1mA 50 mV

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ELECTRICAL CHARACTERISTICS
VIN1 = 5V, VIN2=5V, VEN = 0V, TJ = -40°C to +125°C(5), unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Rising edge 25
STATUS delay TSTA_DEG μs
Falling edge 55
Buck-Boost
Output voltage VOUT -1.5% 3.3 +1.5% V
Output over-voltage
VOUT_OVP_R 110% 115% 120% VOUT
protection
Output OVP recovery VOUT_OVP_F 105% VOUT
OVP discharge resistance RDIS 1 kΩ
Oscillator frequency Fs 1.45 1.8 2.15 MHz
Steady state current limit ILIM VOUT=0V 1.65 2.5 3.35 A
SWD valley current limit(7) -1.5 A
PMOS on resistance RDS(on)-P SWA, SWD, 3.3Vin, 3.3Vout 90 mΩ
NMOS on resistance RDS(on)-N SWB, SWC, 3.3Vin, 3.3Vout 80 mΩ
Soft-start time Tss 0-100%Vout 1 ms
NOTE:
5) All min/max parameters are tested at TJ=25oC. Limits over temperature are guaranteed by design, characterization and correlation.
6) Guaranteed by design.
7) Guaranteed by engineering sample characterization.

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TYPICAL PERFORMANCE CHARACTERISTICS

VIN1 = 5V, VIN2 = 5V, VOUT = 3.3V, L =1µH, TA = 25°C, unless otherwise noted.
VIN1 Shutdown Current vs. VIN2 Shutdown Current vs.
Temperature, VIN1 = 5V Temperature, VIN2 = 5V
1000 1000

VIN2 SHUTDOWN CURRENT

VIN1 SHUTDOWN CURRENT

800 800

600 600

(nA)
(nA)

400 400

200 200

0 0
-45-35-25-15 -5 5 15 25 35 45 55 65 75 85 -45-35-25-15 -5 5 15 25 35 45 55 65 75 85
TEMPERATURE (℃) TEMPERATURE (℃)
VIN1 Quiescent Current vs. VIN2 Quiescent Current vs.
Temperature, VIN1 = 5V Temperature, VIN2 = 5V
300 300
VIN2 QUIESCENT CURRENT
VIN1 QUIESCENT CURRENT

250 250

200 200
(μA)
(μA)

150 150

100 100
-45-35-25-15 -5 5 15 25 35 45 55 65 75 85 -45-35-25-15 -5 5 15 25 35 45 55 65 75 85
TEMPERATURE (℃) TEMPERATURE (℃)

VCC Voltage vs. Temperature Efficiency vs. Load Current

5.5 100
5.4 95
5.3
90
5.2
VCC VOLTAGE (V)

EFFICIENCY (%)

5.1 85
5 80
4.9 75
4.8
70 VIN2=5V
4.7 VIN2=3.3V
4.6 65 VIN2=2.7V
4.5 60
-40 -25 -10 5 20 35 50 65 80 95 110 125 0.001 0.01 0.1 1
TEMPERATURE (℃) LOAD CURRENT (A)

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN1 = 5V, VIN2 = 5V, VOUT = 3.3V, L =1µH, TA = 25°C, unless otherwise noted.
Load Regulation Line Regulation
0.5 1
0.4 VIN2=5V 0.8
LOAD REGULATION (%)

VIN2=3.3V

LINE REGULATION (%)

0.3 0.6
VIN2=2.7V
0.2 0.4
0.1 0.2
0 0
-0.1 -0.2
-0.2 -0.4 Io=0A
-0.3 -0.6 Io=0.25A
-0.4 -0.8 Io=0.5A
-0.5 -1
-0.1 0.1 0.3 0.5 2.52.75 3 [Link] 4 [Link] 5 5.255.5
LOAD CURRENT (A) VIN2 INPUT VOLTAGE (V)

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN1 = 5V, VIN2 = 5V, VOUT = 3.3V, L =1µH, TA = 25°C, unless otherwise noted.
Output Ripple Output Ripple
VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0A VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0A

CH1: CH1:
VOUT/AC VOUT/AC
50mV/div. 50mV/div.
CH2: SW1 CH2: SW1
5V/div. 5V/div.

CH3: SW2 CH3: SW2

5V/div. 5V/div.
CH4: IL CH4: IL
1A/div. 1A/div.
20ms/div. 1µs/div.

Output Ripple Output Ripple

VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0.5A VIN2=5V, VIN1=Float, VOUT=3.3V, IOUT=0.5A

CH1: CH1:
VOUT/AC VOUT/AC
20mV/div. 20mV/div.
CH2: SW1 CH2: SW1
5V/div. 5V/div.

CH3: SW2 CH3: SW2

5V/div. 2V/div.
CH4: IL CH4: IL
1A/div. 1A/div.
500ns/div. 500ns/div.

Output Ripple Output Ripple

VIN2=3.3V, VIN1=Float, VOUT=3.3V, VIN2=2.5V, VIN1=Float, VOUT=3.3V, IOUT=0.5A,
IOUT=0.5A,Buck-boost mode Boost mode

CH1: CH1:
VOUT/AC VOUT/AC
50mV/div. 20mV/div.
CH2: SW1 CH2: SW1
2V/div. 2V/div.

CH3: SW2 CH3: SW2

2V/div. 2V/div.
CH4: IL CH4: IL
1A/div. 1A/div.
1µs/div. 500ns/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN1 = 5V, VIN2 = 5V, VOUT = 3.3V, L =1µH, TA = 25°C, unless otherwise noted.
Power Start-Up Power Start-Up
VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0A VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0.5A

CH1: VOUT
CH1: VOUT
2V/div.
2V/div.
CH2: SW1
CH2: SW1
5V/div.
5V/div.

CH3: VIN1
CH3: VIN1
5V/div.
5V/div.
CH4: IOUT
CH4: IOUT
2A/div.
2A/div.
5ms/div. 10ms/div.

Power Shutdown Power Shutdown

VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0A VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0.5A

CH1: VOUT
CH1: VOUT
2V/div.
2V/div.
CH2: SW1
CH2: SW1
5V/div.
5V/div.

CH3: VIN1
CH3: VIN1
5V/div.
5V/div.
CH4: IOUT
CH4: IOUT
2A/div. 1A/div.

100ms/div. 20ms/div.

EN Start-Up EN Start-Up
VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0A VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0.5A

CH1: VOUT CH1: VOUT

2V/div. 2V/div.
CH2: SW1 CH2: SW1
5V/div. 5V/div.

CH3: VEN CH3: VEN

2V/div. 2V/div.
CH4: IOUT CH4: IOUT
1A/div. 2A/div.
2ms/div. 20ms/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN1 = 5V, VIN2 = 5V, VOUT = 3.3V, L =1µH, TA = 25°C, unless otherwise noted.
EN Shutdown EN Shutdown
VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0A VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0.5A

CH1: VOUT CH1: VOUT

2V/div. 2V/div.
CH2: SW1 CH2: SW1
5V/div. 5V/div.

CH3: VEN CH3: VEN

2V/div. 2V/div.
CH4: IOUT CH4: IOUT
1A/div. 1A/div.

200ms/div. 5ms/div.

Input Voltage Selection by SEL Pin Input Voltage Selection by SEL Pin
VIN1=5V, VIN2=2.5V,VOUT=3.3V, IOUT=0.2A, SEL VIN1=5V, VIN2=2.5V,VOUT=3.3V, IOUT=0.2A, SEL
from Low to High from High to Low

CH1: VOUT CH1: VOUT

2V/div. 2V/div.

CH2: CH2:
OR_OUT OR_OUT
5V/div. 5V/div.
R1: STATUS R1:
5V/div. STATUS
CH3: SEL 5V/div.
2V/div. CH3: SEL
CH4: IOUT 2V/div.
500mA/div. CH4: IOUT
500mA/div.
2ms/div. 10ms/div.

Load Transient SCP Entry

VIN1=5V, VIN2=Float, VOUT=3.3V, IOUT=0A-0.5A, VIN1=5V, VIN2=Float, VOUT=3.3V, short output to
200mA/μs GND.

CH1: VOUT
CH1: 2V/div.
VOUT/AC
CH2: SW1
100mV/div.
5V/div.

CH3: SW2
5V/div.
CH4: IOUT
CH4: IL
500mA/div.
2A/div.
2ms/div. 10ms/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN1 = 5V, VIN2 = 5V, VOUT = 3.3V, L =1µH, TA = 25°C, unless otherwise noted.
SCP Recovery Line Transient
VIN1=5V, VIN2=Float, VOUT=3.3V, short output to VIN1=5V, VIN2=2.5V, IOUT=0.25A, input voltage
GND from VIN1 to VIN2

CH1:
VOUT
CH1: VOUT 2V/div.
2V/div.
CH2: VIN1
CH2: SW1 5V/div.
5V/div.
CH3: VIN2
2V/div.
CH3: SW2
5V/div.
CH4: IOUT
CH4: IL 500mA/div.
2A/div.
10ms/div. 10ms/div.

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BLOCK DIAGRAM
OR_OUT SW1 SW2

VCC

N-MOS
DRV Charge
Pump

LDO OUT
VCC
Q1 SWA SWD
IN1 OUT

Q3
SWB SWC
IN2
Similar
as Q1

SEL
600k
Control
Logic
STATUS Buck-Boost
VCC Control
EN
600k

1. Inrush Current control

2. Thremal Protection GND
3. OVP Shutdown
4. UVLO Function AGND
5. Path Selection

Figure 1. Functional Block Diagram

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Table 1: Truth Table of SEL and STATUS Logic

VIN1 VIN2 SEL Input Power path ORing STATUS
Output
(SEL=“low or (Open drain output.
float” selects
VIN1 Open drain: VIN1 is
selected; or VIN1/2
SEL=“high” N/A
selects VIN2)
Low: VIN2 is selected)

“0”, Select VIN1

OUT OUT=VIN1 Open drain
VIN1 VIN2

4.2V-5.5V 2.5V-5.5V

“1”, Select VIN1

OUT OUT=VIN2 0
VIN2 VIN2

“0”, Select
Not
VIN1 VIN1
available or OUT Open drain
4.2V-5.5V VIN2 OUT=VIN1
<2.5V
“1”, Select
VIN2 Open drain

“0”, Select
Not available VIN1 VIN1 0
or <4.2V 2.5V-5.5V OUT OUT=VIN2
or >5.75V VIN2
“1”, Select
0
VIN2

“0”, Select
>5.75V or Not Not VIN1 VIN1
available or available or OUT
VIN2 OUT=0 Open drain
<4.2V <2.5V “1”, Select
VIN2

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OPERATION Power Path Indication – STATUS

The MP5461 is a dual input, high-efficiency, buck- STATUS is an open drain output. It indicates if the
boost converter that provides regulated output VIN1 or VIN2 channel is selected. When VIN1 is
voltage above, equal to, or below the input voltage. selected, or there is no power supply at VIN1 and
VIN2, STATUS is an open drain output; when
Under-Voltage Lockout (UVLO) VIN2 is selected, STATUS is pulled low. Refer to
Under-voltage lockout (UVLO) is used to protect the truth table.
the device from operating at an insufficient supply
Buck - Boost Operation
voltage. The MP5461 UVLO circuit monitors the
IN1 and IN2 voltage. During start-up, either IN1 or The output voltage is sensed via an internal
IN2 must rise higher than VIN-UVLO to enable the IC. resistor divider from the output to ground. The
voltage difference between the VOUT feedback
EN
voltage and the internal reference is amplified by
EN is the system on/off control input. It's an active the error amplifier to generate a control signal (VC-
low input. EN has an internal weak pull-down Buck). By comparing VC-Buck with the internal current
resistor. Pull EN low or float to enable the MP5461. ramp signal (the sensed SWA’s current with slope
Pull EN high to disable the MP5461. compensation) through the buck comparator, a
VCC Power Supply pulse-width modulation (PWM) control signal for
the buck leg (SWA, SWB) is generated.
When EN is active, IN1 and IN2 charges the VCC.
IN1 is a high voltage pin; there is a LDO from IN1 Another control signal (VC-Boost) is derived from VC-
to VCC. An ORing block will determine using the Buck through the level shift. Similarly, VC-Boost is
IN1 LDO output or IN2 to supply VCC. All internal compared with the same ramp signal through the
circuits of the MP5461 are supplied by VCC. VCC boost comparator and generates a PWM control
only needs to be decoupled with a ceramic signal for the boost leg (SWC, SWD). The switch
capacitor less than 1µF. After the system starts up, topology for the buck-boost converter is shown in
VCC is powered by the higher value of IN1, IN2, Figure 2.
or VOUT internally. VIN VOUT

Dual Input - IN1 and IN2 SW1 SW2

SWA SWD
IN1 is a high voltage input pin, which can support
up to 22V voltage, but the part will be in input over- SWB SWC

voltage shutdown mode when IN1>5.75V.

IN2 is a low voltage input pin, which supports 5.5V
Figure 2: Buck-Boost Switch Topology
maximum operation voltage.
Buck Region (VIN > VOUT)
OR_OUT is the output of the IN1 and IN2 ORing.
The two sets of ORing MOSFETs (IN1 to When the input voltage is significantly higher than
OR_OUT, IN2 to OR_OUT) are integrated. The the output voltage, the converter can deliver
MP5461 employs soft-start control for both IN1 or energy to the load within SWA’s maximum duty
IN2 to OR_OUT start-up. cycle by switching SWA and SWB. The converter
operates in buck mode. In this condition, SWD
If the power source for one channel drops, the fast remains on and SWC remains off. VC-Buck
turn-off protection minimizes the reverse current. compares the current ramp signal and generates
SEL is the power path selection input. Applying a PWM output. Therefore, SWA/SWB is pulse-
low voltage or floating SEL can select the IN1 to width modulated to produce the required duty
OR_OUT power path. Applying a high voltage on cycle and eventually supports the output voltage.
SEL can select the IN2 to OR_OUT power path.
If only one power input is available, the MP5461
will auto use that power input to supply OR_OUT.
For additional details on the SEL input state, refer
to Table 1.

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 MP5461 – DUAL INPUT, INTEGRATED BUCK-BOOST

Buck-Boost Region (VIN ≈ VOUT) Internal Soft Start (SS)

When VIN is close to VOUT, the converter is When EN is active and OR_OUT is above the
unable to provide enough energy to the load due UVLO rising threshold, the MP5461 buck-boost
to SWA’s maximum duty cycle, so the current starts up with a soft-start function. The internal
ramp signal cannot trigger VC-Buck in the first cycle, soft-start (SS) signal ramps up and controls the
and SWA remains on with a 100% duty cycle. If feedback reference voltage.
SWB is not turned on in the first cycle, boost OCP/SCP
begins working in the second cycle (SWC
switches in the second cycle), and an offset The MP5461 employs peak current limits through
voltage is added to the current ramp signal to switch A current sensing. The current limit is 2.5A
allow it to reach VC-Buck. SWC turns off when the (typical).
current ramp signal intersects with VC-Boost in the In an overload or short-circuit condition, VOUT
second cycle, and SWD conducts the inductor drops due to the steady-state switching current
current when SWC is off. This is called boost limit. If VOUT drops below 60% of its normal
operation. output, the MP5461 stops switching and recovers
SWA turns off when the current ramp signal after ~12ms with hiccup mode protection. After the
intersects with VC-Buck in the second cycle, and switching stops in hiccup protection, the internal
SWB turns on to conduct the inductor current after soft-start signal is clamped to VFB + 0.3V, where
SWA turns off. This is called buck operation. VFB is the divided voltage from the residual VOUT.
This is used to make the soft start-up smooth
If SWB turns on in the second cycle, the boost when the MP5461 recovers from hiccup protection.
operation (SWC on) is disabled in the following
cycle. If SWA continues to conduct with 100% duty During the soft-start time, the MP5461 blanks
in the second cycle, boost operation is also during hiccup protection. After the soft-start time is
enabled in the following duty cycle. SWA/SWB finished, if VOUT is still lower than 60% of the
and SWC/SWD switch during this condition normal voltage, the MP5461 resumes hiccup
simultaneously. This is called buck-boost mode. mode. If VOUT rises above 60% of the normal
value, the MP5461 enters normal operation.
Boost Region (VIN < VOUT)
OVP
When the input voltage is significantly lower than
the output voltage, the control voltage (VC-Buck) is The MP5461 employs output over-voltage
always higher than the current ramp signal. The protection. A fast comparator will sense the output
offset voltage is added to the current signal, so voltage condition. Once it's triggered, the MP5461
SWB cannot turn on in all cycles. The boost will stop switching, and a 1k internal resistor will
operation (SWC on) is enabled in every cycle be switched on to discharge the output.
based on the logic, so only SWC and SWD switch.
This is called boost mode. In this condition,
SWC/SWD is pulse-width modulated to produce
the required duty cycle and eventually support the
output regulation voltage.

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 MP5461 – DUAL INPUT, INTEGRATED BUCK-BOOST

The input and output capacitors must be placed

APPLICATION INFORMATION as close to the device as possible.
Component Selection PC Board Layout (8)
Selecting the Inductor Efficient PCB layout is critical for standard
As a buck-boost topology circuit, the inductor operation and thermal dissipation. Refer to
must support buck application with the maximum Figure 3 and the PCB layout guidelines below to
input voltage and boost application with the ensure an effective layout design:
minimum input voltage. Two critical inductance 1) Place the OR_OUT capacitor and VOUT
values can be calculated according to the buck capacitor as close as possible to the OR_OUT
and boost mode current ripple using equation (1) and OUT pin as possible.
and equation (2).
2) Use a large ground plane directly connected
VOUT  ( VIN(MAX )  VOUT ) to GND. Add lots of GND vias to connect Cout's
L MINBUCK  (1) GND node and OR_OUT capacitor's GND.
VIN(MAX )  FREQ  IL
VIN(MIN)  ( VOUT  VIN(MIN) ) 3) Connect AGND to VCC capacitor's GND node
LMINBOOST  (2)
VOUT  FREQ  IL by a Kelvin sense trace.
Where: 4) Place the VCC decoupling capacitor as close
FREQ is the switching frequency as possible to VCC.
Notes:
∆IL is the peak-to-peak inductor current ripple. As (8) The recommended layout is based on the typical application
a rule of thumb, the peak-to-peak ripple can be circuit on the next page (see Figure 4).
set at 0.2A to 1A to achieve better balance of the Top Layer
BOM cost, output ripple, and efficiency. The
minimum inductor value for application should be
the highest value between the results from
equation (1) and equation (2).
In addition to the inductance value, the inductor
must support peak current based on equation (3)
and equation (4) to avoid saturation. OUT

VOUT  (VIN(MAX)  VOUT )

IPEAK BUCK  IOUT  (3) GND
2  VIN(MAX)  FREQ  L
VOUT  IOUT VIN(MIN)  (VOUT  VIN(MIN) ) Bottom Layer
IPEAK BOOST   (4)
 VIN(MIN) 2  VOUT  FREQ  L
IN2

Where η is the estimated efficiency of the IN1

MP5461.
Choose a proper inductor to make sure the
inductor current won’t trigger a peak current limit Connect AGND to
and valley current limit. VCC cap GND node

GND
Input and Output Capacitor Selection
It is recommended to use ceramic capacitors
with low ESR as input and output capacitors in
order to filter any disturbance present in the input
Figure 3: PC Board Layout
line and to obtain stable operation.
Minimum values of 1μF for input 1, and 1μF for
input 2 as well as 2х22μF for output capacitors
are needed to achieve optimal performance.

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 MP5461 – DUAL INPUT, INTEGRATED BUCK-BOOST

TYPICAL APPLICATION CIRCUITS

L1
1µH
VIN1
A3 C3 VOUT
4.2V-5.5V SW1 SW2
3.3V/0.5A
A1 D3
IN1
C1A OUT
1µF C2A C2B
22µF 22µF

VIN2 MP5461
2.5V-5.5V B1 A2
IN2 OR_OUT
C1B C4
1µF 10µF

VCC
D1
R1 SEL C1
VCC
10k C3
D2
1µF
STATUS EN AGND GND
C2 B2 B3

Figure 4: Typical application circuit with fixed 3.3V output voltage

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 MP5461 – DUAL INPUT, INTEGRATED BUCK-BOOST

PACKAGE INFORMATION
CSP-12 (1.4mmx1.8mm)

PIN 1 ID
MARKING

PIN 1 ID
INDEX AREA

TOP VIEW BOTTOM VIEW

SIDE VIEW

NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) BALL COPLANARITY SHALL BE 0.05
MILLIMETER MAX.
3) JEDEC REFERENCE IS MO-211.
4) DRAWING IS NOT TO SCALE.

RECOMMENDED LAND PATTERN

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume
any legal responsibility for any said applications.
MP5461 Rev. 1.0 [Link] 20
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