CHAPTER 3 : REGISTER

Learning Outcomes
 After learning this chapter, students should be able to;
 Identify the basic forms of data movement in shift registers.

 Explain how serial in/serial out (SISO), serial in/parallel out

(SIPO), parallel in/serial out (PISO) and parallel in/parallel out
(PIPO) shift registers operate.

 Determine how bidirectional shift register operates.

 Analyze output waveform for general shift register and 74HC195

shift register IC.

 Construct Johnson and ring counters from shift register.

 Describe shift register applications such as time delay, serial to

parallel converter, universal asynchronous receiver transmitter
(UART) and keyboard encoder.

2
Introduction
 Register – one or more flip-flops used to store or hold data.

 Shift registers
- A group of flip-flops used to shift/transfer data from flip-flop to flip-flop.

- a group of D flip-flops connected in a chain and the clock of the flip-flops

is connected in a synchronous manner.

- They are generally provided with a Clear or Reset connection so that they
can be "SET" or "RESET" as required.

- Shift registers are available in IC form or can be constructed from discrete

flip-flops.

3
 Introduction (continue)
Shift register has 2 basic functions such as;
◦ Data storage
◦ Data movement

Shift register has 4 classifications namely;

◦ Serial in/serial out (SISO)
◦ Serial in/parallel out (SIPO)
◦ Parallel in/serial out (PISO)
◦ Parallel in/parallel out (PIPO)
 Data Storage
 The storage capacity is the total number of bits
of digital data it can retain. The total number of
bits depend on the number of flip-flops being
used.

 Storage capability make it important type of

memory devices
 For example, FF0

 When 1 is applied to D flip-flop, its output 1 D

Q
1

becomes 1 at the triggering edge of clock

CLK
 The output remains 1 until next trigger
 Therefore, 1 is stored
 Next,
FF0
 When 0 is applied to D flip-flop, its output D
Q
0 0
becomes 0 at the triggering edge of clock
 The output remains 0 until next trigger CLK

 Therefore, 0 is stored
5
Data Movement
 Shift capability permits data movement within the register or into or out of
the register when trigger by clock pulse
 For example, various data movement of four 4-bit registers with direction
indicated by arrows

Data in

Data in Data out Data out Data in Data out

Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out

Data in

Data in

Rotate right Rotate left

Data out Data out

Serial in/parallel out Parallel in/parallel out

6
 SISO Shift Register
 The serial in/serial out shift register accepts data serially – that is, one bit at
a time on a single line.

 It produces the stored information on its output also in serial form.

 Example of IC: 74HC165, 74HC195

 Each clock pulse will move an input bit to the next flip-flop. Figure 1 shows
5-bit SISO shift register.

FF0 FF1 FF2 FF3 FF4

Serial Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output

C C C C C

CLK
Figure 1
7
SISO Shift Register (Continue)

Example: 5-bit serial-in serial-out register.

Each clock pulse will move an input bit to the next flip-
flop. For example, a 1 is shown as it moves across.

FF0 FF1 FF2 FF3 FF4

Serial 1 D0
1 D1
1 D2
1 D3
1 D4
1 Serial
data Q0 Q1 Q2 Q3 Q4 data
input output

C C C C C

CLCLKK
SISO Shift Register (continue)
Example: To shift 1011 in a 4-bit serial-in serial-out register starting
with LSB. The register is initially reset.
Q0 Q1 Q2 Q3

1st clock pulse

2nd clock pulse

3rd clock pulse

4th clock pulse

5th clock pulse

After 8th clock pulses, the register is CLEAR

SISO Shift Register (Continue)

Timing diagram for 1011 in a 4 bit SISO

CLK 1 2 3 4 5 6 7 8

Data inp ut 1 1 0 1 0 0 0 0

Q0 1 0

Q1 0 0

Q2 1 0

Q3 1 0
Data bits stored Data bits CLEAR
after 4 clock after 8 clock
pulses pulses
SISO Shift Register (continue..)
Eg: To shift 101 starting with LSB

 Initially, all FF are being RESET.

Q2Q1Q0=000
 1st clock, shift register contains
Q2Q1Q0=001

 2nd clock, shift register contains 010

 3rd clock, shift register contains 101, all 3-

bit input have been completely stored

11
SISO Shift Register (continue..)

 4th clock, the 1st bit is shifted out, shift

register contain 010

 5th clock, the 2nd bit is shifted out, shift

register contains 100

 6th clock, the 3rd bit is shifted out, shift

register is CLEAR

12
SISO Shift Register (continue..)

 Timing waveform for 3-bit SISO shift register

CLK 1 2 3 4 5 6

Data input 1 0 1 0 0 0

Q0 1 0

Q1 0 0

Q2 1 0

Data bits stored Data bits CLEAR

after 3 clock after 6 clock
pulses pulses

13
Exercise 1 (SISO)-Tutorial 4 no.6
 Show the states of the 5-bit register for the specified data input and
clock waveforms.Assume that the register is initially cleared (all 0s).
Show the states of the 5-bit register in Figure 4.6 for the specified data
input and clock waveforms.Assume that the register is initially cleared
(all 0s).

Figure 4.6
Answer Exercise 1

CLK

Data
inputs 1 1 0 1 0

Q0 0

Q1 1

Q2 0

Q3 1

Q4 1

Data bits CLEAR after 10 clock pulses

Exercise 2 (SISO)-Tutorial 4 no.7
Show the states of the 4-bit register (SRG 4) for the data input
and clock waveforms in Figure 4.7.The register initially contains
all 1s.

Figure 4.7
 Answer Exercise 2

0 1 1 0

LSB
0 1 1 0
Q0 Q1 Q2 Q3 Data in

0 1 1 1 1
CLK

1st clock pulse 1 0 1 1 1 1

Q0 1 0 1 1 0
2nd clock pulse 1 1 0 1 1 1 1
Q1 1 1 0 1 1

3rd clock pulse 0 1 1 0 1 1 1 1

Q2 1 1 1 0 1

4th clock pulse 0 1 1 0 1 1 1 1

Q3 1 1 1 1 0
After 4 clock
pulses

Data bits CLEAR after 8 clock pulses

 SIPO Shift Register
 Data bits are entered serially (LSB first) in a SIPO shift register in the same
manner as SISO. Example of IC: 74HC164, 74HC195

 The difference is the way in which the data bits are taken out of the
register; in the parallel output register.

 Data bits are taken out in parallel

 Once all bits are store, the bits are shifted out simultaneously

 Example, Figure 2 shows 4-bits SIPO shift register

FF0 FF1 FF2 FF3
Data input Data input
D D D D D SRG 4

CLK

Q0 Q1 Q2 Q3
CLK

Figure 2
Q0 Q1 Q2 Q3
18
SIPO Shift Register (continue)

An application of shift registers is conversion of serial

data to parallel form.
For example, assume the binary number 1101 is loaded
sequentially, one bit at each clock pulse.

After 4 clock pulses, the data is available at the parallel output.

FF0 FF1 FF2 FF3

Serri all X1 1 10 10 1
datta D
D00 Q
Q00 D
D11 Q
Q111 D
D222 Q
Q22 D
D33 Q
Q333
Q
i nputt
C
C C
C
C C
C
C C
C
C

CCLLK
SIPO Shift Register (continue)

CLK 1 2 3 4 5

1
Q0 0

Q1 0 1

Q2 0 0

Q3 0 1

All data bits are

stored and
shifted out after
4 clock pulses.

20
SIPO Shift Register (continue..)

 Example: Timing waveform for 4-bit SIPO shift register when data bits
0110 is entered. The register initially contains all 1’s.

CLK

Data in 0 1 1 0
(LSB)

Q0
0

Q1
1

Q2
1

Q3
0 (LSB)
All data bits are
stored and shifted
out after 4 clock
pulses

21
 Exercise 1 (SIPO)
Show the states of the 4 bit register (SRG 4) for the data input
and clock waveforms in the figure below.The register initially
contains all 0’s.

Data input
D SRG 4

CLK CLK

Data in 0 1 1 1
Q0 Q1 Q2 Q3
Answer Exercise 1 (SIPO)

CLK 1 2 3 4

Data in 0 1 1 1

Q0 0 0 1 1 1

Q1 0 0 0 1 1

Q2 0 0 0 0 1

Q3 0 0 0 0 0
All data bits
are stored and
shifted out
after 4 clock
pulses
PISO Shift Register
 Data bits are entered parallel on the same time and data bits are shifted out in a
single line. Example of IC: 74HC165, 74HC195.

 D0, D1, D2 and D3 are parallel inputs where, D0 is MSB and D3 is LSB.

 Example, Figure 3 shows 4-bits PISO shift register.

 To write data in, the mode control line is taken to LOW and the data is clocked in.
The data can be shifted when the mode control line is HIGH as SHIFT is active high.
D0 D1 D2 D3 Data in

SHIFT/LOAD D0 D1 D2 D3

G1 G5 G2 G6 G3 G7 G4 SHIFT/LOAD SRG 4
Serial data out
CLK

Serial
D D D D
data out
C C C C

FF0 FF1 FF2 FF3

Figure 3
CLK

24
PISO Shift Register (continue..)

 Example: Timing waveform for 4-bit PISO shift register when data bits
D0D1D2D3 = 0101 is entered. Assume D input remains a 1.

CLK 1 2 3 4 5

SHIFT/LOAD

Q0 0 1

All data bits

Q1 1 1 have been
shifted out
and only 1's
Q2 0 1 remain in
the register
Q3 1 1

Data out (Q3) 1 0 1 0

25
PISO Shift Register (continue..)

Write = Load, initial state = 0000, assume D input remains a 1

Exercise 1 (PISO)-Tutorial 4 no.8
Show the data output waveform for a 4-bit register with the
parallel input data and the clock and SHIFT / LOAD waveforms.
The register initially contains all 0’s.Assume the D input remains
a 0. 1 0 1 0
D0 D1 D2 D3

SHIFT/LOA SRG 4
D
Serial data
out
CLK

CLK 1 2 3 4 5 6

SHIFT/LOAD

Figure 4.8
Answer Exercise 1

CLK 1 2 3 4 5 6

SHIFT/LOAD

Q0 1 0

All data bits

Q1 0 0 have been
shifted out
and only 0's
Q2 1 0 remain in
the register
Q3 0 0

Data out (Q3) 0 1 0 1

Last data bit

PIPO Shift Register
 Example of IC: 74HC195

 Data bits are entered parallel on the same time

 Data bits are shifted out parallel on the same time

 Example, Figure 4 shows 4-bits PIPO shift register inserted with D0=1, D1=0, D2=1
and D3=0.
Parallel data inputs
CLK 1 2 3

D0 D1 D2 D3 D0 1 0 0

FF0 FF1 FF2 FF3

Parallel D1 0 0 0
D D D D data inputs
D2 1 0 0

D3 0 0 0

Q0 1 0 0
CLK
Parallel Q1 0 0 0
outputs
Q0 Q1 Q2 Q3
Q2 1 0 0

Parallel data outputs Q3 0 0 0

Figure 4 Data bits are inserted
and shifted out in
parallel 29
Bidirectional Shift Register

 Capable to shift data bits either left or right. Example of IC: 74HC194

 Use gate logic that enables the transfer of a data bit a stage to the next stage
to the left or right.
 Example, Figure 5 shows 4-bit bidirectional shift register.
 If the signal RIGHT/LEFT is 1, serial data bits will enter into FF0 and move
to the right , otherwise it will be entered into FF3 and move to the left.

Figure 5
30
Bidirectional Shift Register (continue..)

 Example: Timing waveform for 4-bit bidirectional assume that initial value
for Q0 = 1, Q1 = 1, Q2 = 0 and Q3 = 1 and the serial data-input line is LOW.

RIGHT/LEFT
(right) (left) (right) (left)

CLK

Q0 1 0 0 0 1 1 0 0 0 1

Q1 1 1 0 1 1 0 1 0 1 0

Q2 0 1 1 1 0 0 0 1 0 0

Q3 1 0 1 0 0 0 0 0 0 0

# Try the exercise on page 165

31
Shift register’s IC

1. An 8 bit serial in/parallel out shift register

74HC164 → SIPO
2. An 8 bit parallel load shift register
74HC165 → PISO,SISO
3. A 4 bit parallel access shift register
74HC195 → PIPO,SISO,SIPO and PISO.
4. A 4 bit bidirectional universal shift register
74HC194 → bidirectional shift register
A 4 bit parallel access shift register
(74HC195)

The 74HC195 4 bit parallel-access shift

register.(refer to page 493)
 The 74HC195 can be used for PIPO
operation.
 It also has a serial input,so it can be used
for SISO and SIPO operations.
 It can be used for PISO operation by
using Q3 as an output.

33
 74HC195 (Continue)
 74HC1945 block diagram D0 D1 D2 D3

(4) (5) (6) (7)

J (2)
Serial SRG 4
inputs K (3)

SH/LD (9)

CLR (1)

CLK (10)

(15) (14) (13) (12)

Q0 Q1 Q2 Q3

→ When SH/LD’ is LOW, the data on the parallel inputs are entered
synchronously on the positive transition of the clock.
→ When SH/LD’ is HIGH,stored data will shift right (Q0 to Q3)
synchronously with the clock.
→ Inputs J and K’ are the serial data inputs to the first stage of the register
(Q0). Q3 can be used for serial output data.
→ The active-LOW clear input is asynchronous.

34
74HC195 (Continue)
1 2 3 4 5 6 7 8 9 10 11 12

CLR

J 1 0 0 0 0 0 0 0 0
Serial
inputs
K 1 0 0 0 0 0 0 0 0

SH/LD

D0 1

Parallel D1
0
data
inputs
D2 1

D3 0

Q0 0 1 0 0 0 0 1 0 0 0 0

Q1 0 0 1 0 0 0 0 1 0 0 0
Parallel
outputs
Q2
0 0 0 1 0 0 1 0 1 0 0

Q3 0 0 0 0 1 0 0 1 0 1 0

Serial shift Serial shift

Clear Load

35
 Exercise (74HC195)
 For the 74HC195 4 bit shift register shown in
Figure 1,determine all the output of Q in Figure
2. Assume register is initially clear. (Page 172)
D0 D1 D2 D3

(4) (5) (6) (7)

J (2)
Serial SRG 4
inputs K (3)

SH/LD (9)

CLR (1)

CLK (10)

(15) (14) (13) (12)

Q0 Q1 Q2 Q3

Figure 1

36
 CLK 1 2 3 4 5 6 7 8 9 10

SH/LD

CLR

D0

D1

D2

D3

Figure 2

37
Answer Exercise (74HC195)

CLK 1 2 3 4 5 6 7 8 9 10

J 1 0

K 0 0

SH/LD

CLR

D0 0 0 0 0 1 1 0 0

D1 1 1 1 1 0 0 0 0

D2 0 1 1 1 1 0 0 0

D3 0 0 0 0 0 0 1 1

Q0 0 1 0 0 0 0 1 0 1 0 0

Q1 0 0 1 1 1 1 0 1 0 0 0

Q2 0 0 0 1 1 1 1 0 0 0 0

Q3 0 0 0 0 0 0 0 1 0 1 1

Shift Load Shift Load Clear

Shift Register Counters

 Shift registers can form useful counters by recirculating a pattern of 0’s

and 1’s. Two important shift register counters are:
1. Johnson counter
2. Ring counter.

39
Johnson counter
 Produce 2n modulus counter where n is the number of stages

 The complement of the last stage is feedback to the input of first flip-flop

 The Johnson counter is useful when you need a sequence that changes by only
one bit at a time but it has a limited number of states (2n, where n = number of
stages).

 For example, 4-bit Johnson counter using D flip-flop

2n = 2 x 4 = 8 stages

FF0 FF1 FF2 FF3

The Johnson counter can be
D0 Q0 D1 Q1 D2 Q2 D3 Q3
made with a series of D flip-
flops
C C C C

Q3 Q3

CLK

40
Johnson counter

FF0 FF1 FF2 FF3

… or with a series of J-K flip
J0 Q0 J1 Q1 J2 Q2 J3 Q3
Q3 flops. Here Q3 and Q3 are fed
back to the J and K inputs with a
C C C C
“twist”.
Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

41
Shift Register Counters (Continue)

 4 bit Johnson counter (8 stages)

CLOCK PULSE Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

Figure: 4 bit Johnson sequence

42
Shift Register Counters (continue..)

 Timing waveform for 4-bit Johnson counter

CLK 1 2 3 4 5 6 7 8

Q0

Q1

Q2

Q3

43
 Shift Register Counters (continue..)
Johnson counter
Redrawing the same Johnson counter (without the clock
shown) illustrates why it is sometimes called as a “twisted-
ring” counter.
FF0

J0 Q0

“twist” C

K0 Q0
Q3

Q3

K1

Q1
J1
Q3
Q3

FF1
FF3

Q1
C
J3

K3
Shift Register Counters (continue..)
 Example 2: 5 bit Johnson counter
2n = 2 x 5 = 10 stages

FF0 FF1 FF2 FF3 FF4

Q0 Q1 Q2 Q3
D D D D D

Q4

CLK

CLOCK PULSE Q0 Q1 Q2 Q3 Q4
0 0 0 0 0 0
1 1 0 0 0 0
2 1 1 0 0 0
3 1 1 1 0 0
4 1 1 1 1 0
5 1 1 1 1 1
6 0 1 1 1 1
7 0 0 1 1 1
8 0 0 0 1 1
9 0 0 0 0 1
Figure: 5 bit Johnson sequence

45
Exercise
 UsingT flip-flops with negative-going
triggered (NGT) clock,draw a circuits
diagram including timing diagram for a
MOD-8 Johnson counter with an initial
state of all “0’s”.

46
Shift Register Counters (continue..)
 The ring counter
 Produce n modulus counter where n is the number of stages

 The last stage is feedback to the input of first flip-flop

 The ring counter can also be implemented with either D flip-flops or J-K flip-
flops.

FF0 FF1 FF2 FF3

Q3
D0 Q0 D1 Q1 D2 Q2 D3 Q3
Here is a 4-bit ring counter
C C C C constructed from a series of D flip-
flops. Notice the feedback.

CLK

FF0 FF1 FF2 FF3

Q3
J0 Q0 J Q1 J2 Q2 J3 Q3
1
Like the Johnson counter, it can also
C C C C be implemented with J-K flip flops.
Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

47
Shift Register Counters (continue..)

 For example, 4-bit ring counter using D flip-flop

 Initially, FF0 is set while the others are cleared

PRE
FF0 FF1 FF2 FF3
Q0 Q1 Q2 Q3
D D D D

CLR

CLK

48
Shift Register Counters (continue..)

4 bit ring counter

Clock Pulse Q0 Q1 Q2 Q3

0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1

Figure: 4 bit Ring sequence

49
Shift Register Counters (continue..)

 Timing waveform for 4-bit ring counter which initially reset all flip-flop
except FF0

CLK 1 2 3 4 5

Q0 0 1 0 0 0 1

Q1 0 0 1 0 0 0

Q2 0 0 0 1 0 0

Q3 0 0 0 0 1 0

50
 Shift Register Counters (continue..)
Ring counter
Redrawing the Ring counter (without the clock shown)
shows why it is a “ring”.
FF0

The disadvantage to this counter J0 Q0

is that it must be preloaded with C

K0
the desired pattern (usually a Q0

single 0 or 1) and it has even

Q3

Q3

K1
fewer states than a Johnson

Q1
J1
Q3
Q3

FF1
FF3

Q1
C
counter (n, where n = number of

J3

K3
flip-flops.

On the other hand, it has the

advantage of being self-decoding
with a unique output for each state.
 Shift Register Applications
1. Time delay (for SISO)
 Shift registers such as SISO can be used to delay a digital signal by a
predetermined amount.
 The time delay can also be increased by cascading shift registers.

Example:
An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the
total delay through the register?
Solution: A SRG 8 Q7
Data in B Data out

CLK C Q7
40 MHz
The delay for each clock
is 1/40 MHz = 25 ns
CLK

Data in
The total delay is
8 x 25 ns = 200 ns Data out
td

52
Shift Register Applications (continue..)
2. Serial to parallel converter
 All computers process data in parallel form but must
communicate with external devices that send/receive data in
serial form → the requirement for serial to parallel converter
 Example of serial form: USB (Universal Serial Bus) is used to
connect keyboards, printers, scanners to the computer.
 Refer page 503

3. Universal Asynchronous Receiver Transmitter (UART)

 Used as interface between microprocessor and external devices
 Includes both serial-to-parallel and parallel-to-serial conversion.
 refer page 505 and 506
data bus

Serial data out

Microprocessor External
UART Serial data in
system device

(printer, communications
system, etc.)

53
Shift Register Applications (continue..)

4. Keyboard Encoder
❑ The keyboard encoder is an example of where a
ring counter is used in a small system to encode a
key press.
❑ Two 74HC195 shift registers are connected as an
8-bit ring counter preloaded with a single 0. As
the 0 circulate in the ring counter, it “scans” the
keyboard looking for any row that has a key
closure. When one is found, a corresponding
column line is connected to that row line.
❑ The combination of the unique column and row
lines identifies the key. The schematic is shown
on the following slide…
54
 Power on LOAD
SH/LD +VCC
Ring counter

D0 D1 D2 D3 D4 D5 D6 D7
J J
K SRG 4 K SRG 4
CLK 74HC195 74HC195
(5 kHz) C C +V
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Clock inhibit
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ROW encoder COLUMN encoder
74HC147 74HC147
1 2 4 1 2 4

Switch closure
Q Q D0 D1 D2 D3 D4 D5
C
Key code register
74HC174
C C
Q0 Q1 Q2 Q3 Q4 Q5

Q
One-shots To ROM