BENC 2413

DIGITAL SYSTEMS

CHAPTER 1 : FLIP FLOP & COUNTERS

 INTRODUCTION
• Flip-flops (FFs) IS the basic single-bit memory elements
used to build sequential circuit with one or two
inputs/outputs, designed using individual logic gates and
feedback loops.
• A flip-flop differs from a latch in the manner it changes
states.
• A flip-flop is a clocked device, in which only the clock
edge determines when a new bit is entered.
Chapter 1 : WEEK 1

1.1 : EdgeTriggered Flip-Flops

1.2: Master-Slave Flip-Flops
1.3: Flip-Flop Operating Characteristics
and Application
Edge Triggered Flip-Flops
FFs is a clocked device, which only the clock edge determines a new
bit is entered.
Change state either at:
- positive edge (rising edge) or
- negative edge (falling edge) of clock pulse

D Q D Q

C C

Q Q

(a) Positive edge-triggered (b) Negative edge-triggered

• +ve edge-triggered has no bubble at input.

• -ve edge-triggered has bubble at input.

• to identify edge-triggered FF by check it small triangle inside the block at clock (C) input.
(Dynamic indicator)
 CLOCK SIGNALS & SYNCHRONOUS
SEQUENTIAL CIRCUIT

1
Clock signal
0

Clock Cycle
Time
Rising edges of Falling edges
the clock of the clock
(Positive-edge (Negative-edge
triggered) triggered)

• A CLOCK SIGNAL IS A PERIODIC SQUARE WAVE THAT INDEFINITELY

SWITCHES VALUES FROM 0 TO 1 AND 1 TO 0 AT FIXED INTERVALS.
 EDGE-TRIGGERED FLIP-FLOPS
 Four types; Positive-edge Negative-edge
triggered triggered

 S-R flip flops S Q S Q

“Set-Reset” C C
R Q' R Q'

 D flip-flops D Q D Q

“Data or Delay”
C Q' C Q'

 J-K flip-flops J Q J Q

“Jack-Kilby” C C
K Q' K Q'

 T flip-flops T Q T Q
“Toggle”
C Q' C Q'

Dynamic input indicator=edge trigger

 Flip-flops (cont.)
(i) Positive-edge S-R FF

S Q

CLK C
R Q'
 Flip-flops (cont.)
(ii) Positive-edge D FF

D Q

CLK C Q'
 Flip-flops (cont.)
(iii) J-K flip-flop
 The basic gated SR NAND flip flop (S’R’ flip-flop) suffers from two basic
problems:
◦ the S = 0 and R = 0 condition (S = R = 0) must always be avoided (invalid state)
◦ if S or R change state while the enable input is high the correct latching action may not
occur.
→Then to overcome these two fundamental design problems with the SR flip-flop design, the
JK flip Flop was developed.
 JK flip-flop operates just like S’R’ flip-flop except that it does not have invalid
condition.A JK flip-flop is nothing but a RS flip-flop along with two AND gates
which are augmented to it.
 The JK flip flop is basically a gated SR Flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can
occur when both inputs S and R are equal to logic level “1”.
Flip-flops (cont.)
 Dual JK Flip-flop 74LS73
 Flip-flops (cont.)
(iii) Positive-edge J-K FF

J Q

CLK C
K Q'
 Flip-flops (cont.)
(iv) Positive-edgeT FF

T Q

CLK C
Flip-flops (cont.)
Generally T FFs Ics are not available. It can be
constructed using JK, RS or D FFs.
Above figure shows the relation of T flip flop
using JK FFs.
 Flip-flops (cont.)
A D-flip-flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting Q
back to D as shown.

D Q

For example,if Q is LOW, Q is HIGH CLK CLK

and the flip-flop will toggle on the
next clock edge.Because the flip- Q
flop only changes on the active edge,
the output will only change once for
each clock pulse.
D flip-flop hardwired for
a toggle mode
 Asynchronous preset & clear
 Most integrated circuit FF have asynchronous inputs

 These input change the FF output without clock triggering

 Normally label as preset (PRE) and clear (CLR)

 For example,take theT FF

/PRE /CLR OUTPUT

0 0 Invalid
0 1 Q = 1 (Set)
1 0 Q = 0 (Reset)
1 1 Flip-flop normal
operation
Exercises
Exercise 1: Negative edge S-R flip-flop. Q is initially ‘0’.

CLK

Q
Exercises (cont.)
Answer:

CLK

Q
Exercises (cont.)
Exercise 2: Negative edge D flip-flop. Q is initially ‘0’.

CLK

Q
Exercises (cont.)
Answer:

CLK

Q
Exercises (cont.)
Exercise 3: Negative edgeT flip-flop. Q is initially ‘0’.

CLK

Q
Exercises (cont.)
Answer:

CLK

Q
 Exercises (cont.)
Q
Exercise 4: J

Determine the Q output for the J-K flip- CLK

flop,given the inputs shown.
K Q

Notice that the outputs change on the leading edge of the clock.

Answer:
Set Toggle Set Latch
CLK

Q
 Exercises (cont.) PRE

J Q
Exercise 5:
CLK
Determine the Q output for the J-K flip-flop,
given the inputs shown. K Q

CLR
Answer:
Set Toggle Set Reset Toggle Latch
CLK

K Set
PRE Reset
CLR

Q
Exercises (cont.)
Exercise 6:
For negative edge triggered J-K flip-flop with preset
(/PRE) and (/CLR) inputs,determine the Q output for the input
shown in the timing diagram in the figure below.Assume Q starts
with 1 and the input J and K always 1.

CLK

PRE’

CLR’

Q
Exercises (cont.)
Answer:
/PRE /CLR OUTPUT
0 0 Invalid
0 1 Q = 1 (Set)
1 0 Q = 0 (Reset)
1 1 Flip-flop normal
operation

CLK

PRE’

CLR’

Q
 CHAPTER 1 : FLIP FLOP & COUNTERS

WEEK 1

1.1 : EdgeTriggered Flip-Flops

1.2: Master-Slave Flip-Flops
1.3: Flip-Flop Operating Characteristics
and Application
Master-Slave Flip Flop (Pulse-Triggered)
– It constructed with two latches.
– The master latch is loaded with the condition of the J-K inputs while
the clock is HIGH. When the clock goes LOW, the slave takes on the
state of the master and the master is latched.
– The master-slave is a level-triggered device.
– The master-slave can interpret unwanted signals on the J-K inputs.

*truth table are same with edge trigger except the way it clocked
JK Flip Flop
Basic logic diagram for J-K flip-flop
(Master-Slave FF)

It composed two section; master and slave

Master section : A Gated latch
Slave section :A Gated latch with inverted clock and its control by the
output of master section
– Operation Details:
1. Clock High (Master Active):
1. The Master Flip-Flop takes the J and K inputs and prepares the output.
2. However, the output is not transferred to the final stage yet.
2. Clock Low (Slave Active):
1. The Slave Flip-Flop becomes active.
2. The stored output of the Master Flip-Flop is passed to the output of the
Slave Flip-Flop, finalizing the result.
– Synchronous Operation:
• The Master-Slave configuration ensures that the output changes only
during the falling edge of the clock. This prevents rapid, unwanted
toggling or incorrect behavior caused by glitches in input signals.
WEEK 1

1.1 : EdgeTriggered Flip-Flops

1.2: Master-Slave Flip-Flops
1.3: Flip-Flop Operating Characteristics
and Application
Flip Flop Application

3 general applications of Flip-flop are :

i. Parallel Data Storage

ii. Frequency Division
iii. Counter Application
i. Parallel Data Storage
• Store data from parallel lines in group of FF.(store data in group)
• Operation is illustrated in Figure 8.

OPERATION :
- Using 4 FFs.
- 4 parallel data lines is connected to the D input of FFs.
- Clock inputs connected together. (triggered by a same clock)
- Asynchronous reset inputs connected to a common CLR line.
(initially reset all FFs)
Figure 8
ii. Frequency Division

– Use to reduce the frequency of a periodic waveform

– Pulse apply to clock input, J-K toggle (J=K=1)
– Q output is a square wave with one-half the frequency of clock
input.
– Change state each trigger clock.
– Frequency division,
Example 1 – A single FF
J-K FF as a divide-by-2 device. Q is one-half the frequency of CLK.
Output change on the +ve clock edge.(this is +ve edge trigger)
 Example 2 – Two FFs
– Using 2 FFs.
– QB depends on pulse QA
iii. Counter

– -ve edge trigger J-K FF are used.

– Both FF initially RESET
– FF A toggle when –ve going transition.
– QA clocks for QB
– FF B toggle when QA makes HIGH LOW transition
 EXAMPLE
– Used to generate binary sequence. (00,01,10,11)
– Two repetition are shown in figure below