1-1
Computer System Architecture
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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1-1 Digital Computers
Computer = H/W + S/W
Program(S/W) Application S/W
A sequence of instruction
S/W = Program + Data
The data that are manipulated by the API
program constitute the data base
Application S/W Operating System
DB, word processor, Spread Sheet
System S/W
OS, Firmware, Compiler, Device
Driver ROM BIOS
Computer H/W
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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1-1 Digital Computers continued
Computer Hardware
CPU
Memory
Program Memory(ROM)
Memory
Data Memory(RAM)
I/O Device
Interface: 8251 SIO, 8255 PIO,
6845 CRTC, 8272 FDC, 8237
DMAC, 8279 KDI CPU
Input Device: Keyboard, Mouse,
Scanner
Output Device: Printer, Plotter,
Display
Input Output
Storage Device(I/O): FDD, HDD, Device
Interface Device
MOD
Figure 1-1 Block Diagram of a digital Computer
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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1-1 Digital Computers continued
3 different point of view(Computer Hardware)
Computer Organization
H/W components operation/connection
Computer Design
H/W Design/Implementation
Computer Architecture
Structure and behavior of the computer as seen by the user
Information format, Instruction set, memory addressing, CPU, I/O, Memory
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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1-1 Digital Computers
What is “Computer Architecture”?
Instruction Set Architecture (ISA)
Machine Organization
“ISA”?
Instructions, Addressing modes, Instruction and data formats, Register
“Machine Organization”?
CPU(Control, Data path), Memory, Input, Output
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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1-2 Logic Gates
ADC(Analog to Digital Conversion)
0 : 0.5
Signal Physical Quantity Binary Information
1: 3
V, A, F Discrete Value
Gate
The manipulation of binary information is done by logic circuit called
“gate”.
Fig. 1-2 Digital Logic Gates
AND, OR, INVERTER, BUFFER, NAND, NOR, XOR, XNOR
George Boole
Born: 2 Nov 1815 in Lincoln,
Lincolnshire, England
Died: 8 Dec 1864 in Ballintemple,
County Cork, Ireland
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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1-3 Boolean Algebra
Boolean Algebra
Deals with binary variable(A, B, x, y: T/F or 1/0) + logic
operation(AND, OR, NOT…)
Boolean Function: variable + operation
F(x, y, z) = x + y’z
Truth Table: Relationship Logic Diagram:
between a function and variable
Algebraic Expression
Logic Diagram(gates로 표현)
x y z F
0 0 0 0 x
0 0 1 1
0 1 0 0 y F
2n Combination
0 1 1 0
Variable n = 3 1 0 0 1 z
1 0 1 1
1 1 0 1
1 1 1 1
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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Purpose of Boolean Algebra
To facilitate the analysis and design of digital circuit
Convenient Tools
Truth table : relationship between binary variables
Logic diagram : input-output relationship
Find simpler circuits for the same function
Boolean Algebra Rule : Tab. 1-1
- Operation with 0 and 1: x + 0 = x , x + 1 = 1 , x • 1 = x , x • 0 = 0
- Idempotent Law: x + x =x , x • x = x
- Complementary Law: x + x' = 1 , x • x' = 0
- Commutative Law: x + y = y + x , x • y = y • x
- Associative Law: x + (y + z) = (x + y) + z , x • ( y • z) = (x • y) • z
- Distributive Law: x • ( y+ x) = (x • y) + (x • z) , x + (y • z) = (x + y) • (x + z)
- DeMorgan's Law: (x + y)' = x' • y’ , (x • y )’ = x’ + y’
( A B ) c Ac B c
General Form: (x1 + x2 + x3 + … xn)' = x1' • x2' • x3' • … xn’
(x1 • x2 • x3 • … xn) ' = x1' + x2' + x3' + … xn’
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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F= AB’ + C’D + AB’ + C’D F= ABC + ABC’ + A’C
= x + x (let x= AB’ + C’D) = AB(C + C’) + A’C
=x = AB + A’C
= AB’ + C’D 1 inverter, 1 AND gate
Fig. 1-4 2 graphic symbols for NOR gate
x x
y (x+y+z)’ y x’ y’z’
z z
(a) OR-invert (b) invert-OR
Fig. 1-5 2 graphic symbols for NAND gate
x x
y (xyz)’ y (x’+y’+z’)
z z
(a) NAND-invert (b) invert-NAND
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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1-4 Map Simplification
Karnaugh Map(K-Map)
Map method for simplifying Boolean expressions
Minterm / Maxterm
Minterm : n variables product ( x=1, x’=0)
Maxterm : n variables sum (x=0, x’=1)
2 variables example
x y Minterm Maxterm
0 0 x'y' m0 x +y M0
0 1 x'y m1 x + y' M1
1 0 x y' m2 x'+ y M2
1 1 x y m3 x'+ y' M3
m 0 + m1 + m2 + m3 M0 M1 M2 M3
F = x’y + xy
m1 m3
(1,3) ( m1 + m3 )
(0,2) (Complement = M0 M2 )
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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Map
2 variables 3 variables 4 variables
C
B B
0 1 0 1 3 2
0 1 3 2
A 2 3 A 4 5 7 6 4 5 7 6 B
A
12 13 15 14
C
5 variables C
8 9 11 10
D
0 1 3 2 6 7 5 4
8 9 11 10 14 15 13 12
B
A
24 25 27 26 30 31 29 28
16 17 19 18 22 23 21 20
E D F
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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F= x + y’z
(1) Truth Table (2) F ( x , y , z ) (1,4,5,6,7 )
x y z F Minterm (3)
y
0 0 0 0 m0
0 0 1 1 m1 0 1 3 2
0 1 0 0 m2
4 5 7 6
0 1 1 0 m3 x
1 0 0 1 m4
z
1 0 1 1 m5
1 1 0 1 m6
1 1 1 1 m7 F= x + y’z
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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Adjacent Square
Number of square = 2n (2, 4, 8, ….)
0 1 3 2
The squares at the extreme ends of the 4 5 7 6
same horizontal row are to be
considered adjacent
0 1 3 2
4 5 7 6
The same applies to the top and 12 13 15 14
bottom squares of a column 8 9 11 10
0 1 3 2
The four corner squares of a map must 0 1 3 2
4 5 7 6
be considered to be adjacent 4 5 7 6
12 13 15 14
8 9 11 10
Groups of combined adjacent squares
0 1 3 2
may share one or more squares with
one or more group 4 5 7 6
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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B
F ( A, B, C ) (3,4,6,7)
0 1 3 2
F=AC’ + BC A 4 5 7 6
C B
F ( A, B, C ) (0,2,4,5,6) 0 1 3 2
F=C’ + AB’ A 4 5 7 6
C C
F ( A, B, C , D ) (0,1,2,6,8,9,10)
0 1 3 2
F=C’ + AB’
4 5 7 6 B
A
12 13 15 14
Product-of-Sums Simplification 8 9 11 10
F ( A, B, C , D ) (0,1,2,5,8,9,10) D C
F=B’D’ + B’C’ + A’C’D Sum of product 0 1 3 2
4 5 7 6 B
F’=AB + CD + BD’(square marked 0’s) A
12 13 15 14
F’’(F)=(A’ + B’)(C’ + D’)(B’ + D) 8 9 11 10
Product of Sum
D
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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NAND Implementation
Sum of Product : F=B’D’ + B’C’ + A’C’D
B’
D’
C’
A’
D
NOR Implementation
Product of Sum : F=(A’ + B’)(C’ + D’)(B’ + D)
A’
B’
C’
D’
D’ B
Don’t care conditions 0 1 3 2
X X
F(A,B,C)=(0, 2, 6), d(A,B,C)= (1, 3, 5) 4 5 7 6
A X
F=A’ + BC’= (0, 1, 2, 3, 6) C
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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1-5 Combinational Circuits
Combinational Circuits
A connected arrangement of logic gates with a set of inputs and outputs
Fig. 1-15 Block diagram of a combinational circuit
i0 f0
i1 Combinational f1
...
...
Circuits
(Logic Gates)
in fm
Analysis
Logic circuits diagram Boolean function or Truth table
Design(Analysis의 반대) Experience
1. The Problem is stated
2. I/O variables are assigned
3. Truth table(I/O relation)
4. Simplified Boolean Function(Map 과 Boolean 대수 이용)
5. Logic circuit diagram
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
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Design Example : Full Adder
1. Full adder is a combinational circuits that forms the arithmetic sume
of three input bit(Carry considered)
2. 3 Input(x, y, z), 2 Output(S: sum, C: carry)
3. Truth Table 4. Simplification
y y
Input Output
x y z C S
0 0 0 0 0 0 1 3 2 0 1 3 2
0 0 1 0 1
x x 4 5 7 6
0 1 0 0 1
4 5 7 6
0 1 1 1 0 z
z
1 0 0 0 1 S=xy’z’ + x’y’z + xyz + x’yz’
C= xy’z + x’yz + xy
1 0 1 1 0
1 1 0 1 0 =z(xy’ + x’y) + xy = z’(xy’ + x’y) + z(x’y’ + xy)
1 1 1 1 1 =z(x y) + xy = z’(x y) + z(x y)’
=a’b + ab’ (let a=z, b=x y)
5. Logic circuit diagram =x y z
x
y (x y)’=(xy’+x’y)’
c
=(x’+y)(x+y’)
z =x’x+x’y’+xy+yy’
=x’y’+xy
s
Computer System Architecture Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.
