Technical Manual - Architecture and Principle

HUAWEI UMG8900 Universal Media Gateway Table of Contents

Table of Contents

Chapter 4 Clock System.......................................................................................................... 4-1

4.1 About This Chapter...................................................................................................... 4-1
4.2 Overview of the Clock System..................................................................................4-1
4.2.1 Basic Concepts................................................................................................ 4-1
4.2.2 Technical Features.........................................................................................4-4
4.2.3 Performance Specifications...........................................................................4-5
4.3 Architecture of the Clock System..............................................................................4-7
4.3.1 Fundamentals of the Clock System................................................................4-7
4.3.2 Clock Processing and Driving Modules.........................................................4-10
4.3.3 Line Clock Extracting Module.......................................................................4-11
4.4 Clock Signal Flow.................................................................................................... 4-11
4.4.1 Clock Signal Extracting Flow.......................................................................4-11
4.4.2 Clock Signal Distributing Flow.......................................................................4-12

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Chapter 4 Clock System

4.1 About This Chapter

This chapter describes the technical features, components and module functions of
the UMG8900 clock synchronization system. It also profiles the extraction and
distribution processes of clock signals in different modes.
This chapter covers:
 Overview of the Clock System
 Architecture of the Clock System
 Clock Signal Flow

4.2 Overview of the Clock System

4.2.1 Basic Concepts

I. Synchronization

Synchronization refers to a specific and strict frequency or phase relationship kept

between signals. That is, their corresponding valid instants occur at the same
average speed. In other words, synchronization shall keep all equipment in the
communication network running at the same speed.
Synchronization in the analog communication network refers to the synchronization
between carrier frequencies at both ends of the transmission system. It aims to
restrict the end-to-end frequency offset in the video channel within 2 Hz so that
different services can be transmitted over the analog network.
What is transmitted in the digital communication network is the PCM discrete pulse,
which is encoded information. If the clock frequencies of two digital switching
devices are different from each other, or if phase drift and jitter is overlapped due to
loss of bits during transmission, code elements will be deleted or repeated in the
buffer of the digital switching system. Thus, slips in the bit stream will occur.
To decrease the slip rate and the impact of slips on services, as well as to ensure
that the bit stream to every switching node can be switched and transmitted
effectively, slips should be controlled. Thus, digital devices in the network use a
same primary clock frequency. That is, the synchronization between clocks should
be realized.
Therefore, the synchronization in the digital communication network refers to the
synchronization between clocks embedded in all digital devices in the network.

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Here, synchronization consists of two modes: bit synchronization and frame

synchronization.
Bit synchronization is the most basic synchronization. It means that the clocks at
both the receiving and sending ends should be at the same frequency and phase.
Thus, the receiving end can correctly receive and judge each code element from
the sending end. Usually, the receiving end extracts the clock frequency of the
sending end from the PCM code to realize bit synchronization.
In digital communication, bit streams are processed in frames. In time division
multiplexing or timeslot switching in a digital switch, bit streams need to pass a
frame aligner to achieve frame synchronization.
In the SDH network, poor synchronization does not lead to slips. The reason is that
in the SDH network, payloads are transmitted in the asynchronous mode and
different speeds at the receiving and sending ends do not lead to pointer
adjustment. However, the pointer adjustment causes jitter and drift of output
signals. Too much jitter causes out of frame (loss of frame synchronization) while
too much drift causes slips in terminal devices. In the SDH network, the purpose of
synchronization is to restrict and reduce the times of pointer adjustments.

II. Slip

The rate of an external source signal is determined by the peer end. Therefore, the
rate should be converted to the rate of the clock in the local switching device before
the signal enters the digital switching network. This is called retiming, which is
implemented in the buffer.

The retiming process is as follows:

1) Extract the clock signals from the source signals as the write clock.
2) Write the rate of the extracted source clock into the buffer.
3) Use the local clock in the receiving device as the read clock to read the signal
from the buffer.
In this way, the rate of the source signal is converted to that of the local clock, as
shown in Figure 4-1 .

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Figure 4-1 Retiming process through the buffer

The difference between the frequencies of the write and read clocks leads to
overflow or underflow of the buffer and thus causes a block of bits to be repeated or
deleted. This is called slip. The buffer capacity is usually greater than the data
quantity of one frame and the typical value is of two frames. Therefore, a frame of
data will be deleted or repeated when slip occurs. This slip, which only repeats or
deletes a frame but does not disorder the frame structure, is called controlled slip or
frame slip.

III. Synchronization Modes

 Plesiochronous mode
A high precision clock is configured at each node in the network. These clocks have
the same nominal frequency and frequency tolerance, and run independently of
each other. Although the frequencies of all the clocks are impossible to be
absolutely equal to one another, the slips generated can meet the specifications
due to the high precision of frequencies.
This mode is simple and flexible. However, it requires high performance of clocks
and high cost, and causes periodical slips. The digital network synchronized in this
mode is called the plesiochronous network.
 Master-slave mode
In the master-slave mode, a designated master clock disseminates its frequency
reference to all other slave clocks.
The master-slave mode is classified into direct master-slave mode and hierarchical
master-slave mode. In the hierarchical master-slave mode, the master clock
disseminates the timing signals to slave clocks by level and the slave clocks
receive the timing signals from their upper-level clocks. The timing signals can be
extracted from the digital signals that carry the services, or can be transferred
through private links. The timing output of the slave clock is phase-locked to a
reference timing signal, with the same precision as the reference timing signal.

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In the master-slave mode, no periodical slips occur in normal conditions. In

addition, this mode does not require much high quality of slave clocks and thus the
network construction cost is low. In this mode, however, its unreliable transmission
links affect the transmission of timing signals and timing loop may occur.
 Mutual synchronization mode
There is no primary reference clock (PRC) in the mutual synchronization mode.
Each clock receives the timing signals sent from other node clocks and locks its
frequency to the weighted-average frequency of all received timing signals. All
clocks interact on each other. When the network parameters are selected properly,
all clocks of the whole network will reach a stable system frequency to realize clock
synchronization in the network.
The mutual synchronization mode has higher reliability and does not require much
high clock performance. However, the stability frequency depends on the network
parameters and is hard to be determined in advance. In addition, the whole network
is a complex feedback system. Thus, any change of the network parameters is apt
to cause the change of system performance or even instability.
 Mixed synchronization mode
In the master-slave mode, when the transmission distance for timing signals is very
long, the quality of signals and reliability degrade due to transmission links and
external interference. Thus, the network performance reduces. In the mixed
synchronization mode, the whole network is divided into a number of
synchronization zones. A PRC is set in every zone, with a slave clock at each
synchronization node. The master-slave mode is employed within the zone, while
the plesiochronous mode among zones. In this way, the clock levels and the
transmission distance of timing signals are reduced. Thus, the performance of the
synchronization network is improved. When the PRC in the synchronization zone is
of higher precision, periodical slips of the inter-zone links seldom occur.
The Global Positioning System (GPS) makes it possible to receive high-precision
frequency standard. The GPS has the same long-term frequency accuracy as the
Cesium clock. In the combination of the GPS and the controlled Rubidium clock
with excellent short-term stability, the requirements for the intra-zone reference
clock can be met.

4.2.2 Technical Features

The clock system provides necessary clock signals within the UMG8900. This
system accesses clock signals from external standard reference sources to
synchronize the clock with other network elements in the network.
The clock synchronization system of the UMG8900 has the following technical
features:

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 This system adopts a high-performance central processing unit (CPU) and

highly stable constant-temperature crystal oscillators. With the direct digital
synthesis (DDS) technology, this system outputs clock signals under the
control of programs. The intelligent software phase-lock algorithm and phase
monitoring circuit embedded in the system enable the clock to have anti-
interference abilities against input drift, jitter and phase transient, and to keep
the long time high-precision stability without a primary source. In addition,
multi-reference control on the primary source and flexible configuration for the
levels of input reference sources enable the clock to be stable and reliable.
 This system provides stratum 2 or 3 clock needed by telecommunication
devices, including classes A and B. It supports Building Integrated Timing
Supply System (BITS) at 2048 kHz or 2048 kbit/s, GPS/Global Navigation
Satellite System (GLONASS) and 8 kHz line clock as clock reference sources.
It supports selecting external clock reference sources and output clock levels
through software flexibly.
 The clock system supports synchronization status message (SSM) receiving
and sending. Through the SSM byte (SSMB), it obtains the clock quality of the
upper-level node and selects the clock source of the best quality. In addition, it
outputs the SSM to the lower-level node. Thus, the system improves the
stability and reliability of the synchronization network.
 This system supports the free running, fast tracking, locked and holdover clock
modes. It can provide highly precise and stable clock sources for the
UMG8900.
 The core processing unit of the clock system is the independent CLK board or
the clock sub board attached to the MTNC. If the independent CLK is used, the
clock system can provide stratum 2 or 3 clock. If the clock sub board is used,
the clock system can only provide stratum 3 clock.

 Note:
If the independent CLK is used, the clock system supports 2048 kbit/s, 2048 kHz or
8 kHz line clock and GPS/GLONASS clock. If the clock sub board is used, the clock
system supports 2048 kbit/s, 2048 kHz or 8 kHz line clock. The clock reference
source can be selected flexibly through configuration.

4.2.3 Performance Specifications

The performance of the clock system meets the following specifications:

 BELLCORE GR-1244-CORE 2 and ITU-T G.812 Type I
 BELLCORE GR-1244-CORE 3E

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 BELLCORE GR-1244-CORE 1 and ITU-T G.811 for the GPS/GLONASS clock

source
 ITU-T G.781
 ITU-T G.703 and ITU-T G.704 for external synchronous clocks
The technical specifications of the clock system are shown in Table 4-1 .

Table 4-1 Technical specifications of the clock system

No. Item Index

Minimum Stratum 2 clock: ±4 × 10-7

accuracy Stratum 3 clock: ±4.6 × 10-6

Stratum 2 clock: ±4 × 10-7

Pull-in range
Stratum 3 clock: ±4.6 × 10-6
Network-
Maximum
1 accessed clock Stratum 2 clock: 5 × 10-10 per day
frequency
parameters Stratum 3 clock: 2 × 10-8 per day
offset

Initial Stratum 2 clock: < 5 × 10-10 per

maximum day
frequency Stratum 3 clock: < 1 × 10-8 per
offset day

Ideal status MRTIE = 1 ms

MRTIE (ns) = a × s + (1/2) × b × s 2

+c
Here, S stands for time,
Long-term measured in second, and MRTIE
2 Hold-over
phase status is measured in nanosecond.
status
Stratum 2 clock:
a = 0.5 b = 1.16 × 10-5 c = 1000
Stratum 3 clock:
a = 10 b = 2.3 × 10-4 c = 1000

Clock work The clock work modes can be fast tracking,

3
modes locked, hold-over and free running.

4 Jitter tolerance See Figure 4-2 .

These indexes are explained as follows:

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 Minimum accuracy: the maximum magnitude of the frequency deviation from

the nominal frequency for a specified time period (20 years) in the absence of
an external reference clock, namely, in the free-running state.
 Maximum frequency offset: the maximum magnitude of the fractional
frequency deviation for a specified time period.
 Pull-in range: the largest frequency bandwidth of the input clock signals that
can be locked.
 MRTIE (Maximum Relative Time Interval Error): the largest peak-to-peak delay
deviation of a tested clock against a reference clock within a specified test
period.
The lower limits of maximum jitter and drift allowed are shown in Figure 4-2 .

Figure 4-2 The lower limits of maximum jitter and drift allowed

Suppose that the jitter frequency of an input signal is 1 kHz and its amplitude is
more than 1.5 UI. If the system works properly under this condition, this input signal
meets the requirement.

 Note:
UI refers to the unit interval. The reciprocal of the digital signal frequency is one UI.
For example, for a 2.048 Mbit/s signal, its time unit interval is 488 ns.

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4.3 Architecture of the Clock System

4.3.1 Fundamentals of the Clock System

The clock system differs a little in the SSM-256 and SSM-32 frame applications. In
the SSM-256 self-cascading mode, clock distribution cables are needed to
distribute clock signals between frames.
The architecture of the clock system in the SSM-256 self-cascading mode is shown
in Figure 4-3 .

Figure 4-3 Architecture of the clock system (SSM-256 self-cascading)

The external clock reference sources supported by the clock system include 2048
kbit/s or 2048 kHz BITS clock, 8 kHz line clock and GPS/GLONASS clock. You can
select a clock reference source based on the actual networking.
The clock system also provides interfaces for BITS clock output. It can connect with
lower-level devices through the interfaces to provide the BITS clock reference
source.
The clock system extracts 8 kHz line clock from the external clock reference source
or the E32/T32/S2L/A4L/P4L interface boards of the UMG8900. After internal clock
distribution and clock driving, this system outputs 16 kHz clock signals.
The CLK boards send the 16 kHz clock signals to the NET boards in the main
control frame through the backplane bus and to the NET boards in other frames
through external cables. The NET boards perform frequency division, frequency

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doubling and driving on the clock signals and then distribute them to all service
boards.
When SSM-256 frames are used, the clock system includes the CLK and NET
boards as well as the interface boards that extract line clocks.
When SSM-32 frames are used, the clock system supports the following two
modes:
 Mode 1: The independent CLK is used to provide stratum 2 or 3 clock. The
CLK boards are configured in slots 0 and 1 in the main control frame.
 Mode 2: The clock sub board is used. It is attached to the MTNC board to
provide stratum 3 clock.
The two modes only differ in clock extraction. In both modes, clock signals are
distributed through the TDM cascading channels between frames to provide
necessary clock signals for other frames.
The architecture of the clock system in the SSM-32 self-cascading mode is shown
in Figure 4-4 .

Figure 4-4 Architecture of the clock system (SSM-32 self-cascading)

In Figure 4-4 , the dashed line indicates the clock extraction in the case of the
independent CLK while the real line indicates the clock extraction in the case of the
clock sub board.

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The CLK or the clock sub board is always configured in No. 1 SSM-32 frame. The
CLK supports BITS, GPS/GLONASS and 8 kHz line clocks. The clock sub board
supports BITS and 8 kHz line clocks.

 Note:
Suppose that an SSM-32 frame serves as the main control frame and the
independent CLK is configured at the same time. For cascaded SSM-256 frames,
external clock distribution cables are needed to provide clock signals. For SSM-32
frames, the TDM cascading cables are used to provide clock signals.

4.3.2 Clock Processing and Driving Modules

After accessing clock signals from an external clock reference source, the clock
processing and driving modules conduct frequency doubling, frequency division,
and amplifying and driving on the clock signals. Then the modules output the clock
signals needed by the UMG8900. The clock system supports the independent CLK
mode and the clock sub board mode.

I. Independent CLK Mode

When the independent CLK is used, the CLK implements the clock processing and
the NET implements the clock driving. The clock processing module can access
BITS clock, 8 kHz line clock and GPS/GLONASS clock.
 The interface board extracts line clock and then sends the clock signals to the
CLK in RS-422 differential signals through twisted pairs. By way of cabling, an
interface board and its clock signals are selected. Each CLK board has two
line clock interfaces. The master and slave CLK boards can access four inputs
of line clocks.
 The external synchronous input signals are input from the front panel of the
CLK board through the SMB coaxial interfaces. Each CLK board provides one
external synchronous input interface.
 After GPS/GLONASS clock is accessed through antennas, the signals are
input from the ANT interface on the CLK board. Each CLK board provides one
GPS/GLONASS clock input interface.
The main clock processing module provides two types of output clocks, namely,
external clock and NET clock.
 The external synchronous output signals are output through SMB coaxial
interfaces on the CLK board. Each CLK board provides one external
synchronous output interface.

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 The 16 kHz clock signals in RS-422 differential manners are output to the NET
board through twisted pairs. Each CLK board can output up to 18 channels of
signals and support up to 9-frame cascading.
In the independent CLK mode, clock driving is mainly implemented by the NET
boards. After the NET boards receive the 16 kHz clock signals from the CLK boards
through clock distribution cables or the backplane, the NET boards synthesize the
clock signals necessary for the local frame, including 32.768 MHz, 38.88 MHz and
2 kHz clocks.
If the CLK boards are configured in an SSM-256 frame, the CLK boards send clock
signals to the NET boards in this frame through the backplane and to the NET
boards in other SSM-256 frames through clock distribution cables. If the CLK
boards are configured in an SSM-32 frame, the CLK boards send clock signals to
the NET boards in this frame through the backplane, to the NET boards in other
SSM-256 frames through clock distribution cables and to the NET boards in other
SSM-32 frames through TDM cascading cables.

II. Clock Sub Board Mode

The clock sub board can access the BITS clock and 8 kHz line clock. It does not
support the GPS/GLONASS clock. It is attached to the MTNC board that is
mandatory in an SSM-32 frame.
The clock sub board accesses an external clock in the same way as the
independent CLK.

4.3.3 Line Clock Extracting Module

The line clock extracting module is mainly located in the interface boards such as
the E32, T32, S2L, A4L, P4L and P1H.
After clock signals are extracted over the Synchronous Transport Mode-1 (STM-1)
interfaces or E1/T1 interfaces on interface boards, two channels of 8 kHz clock
signals are output to two CLK boards respectively. The 8 kHz clock signals are
output in the manner of RS-422 differential electrical level. If the interface boards
fail to extract clocks, for example, due to interruption of optical or E1 signals, chip
fault or failure of phase-locked loop, the interface boards will cut off clock signals
that are sent to the CLK boards.
The interface boards support the SSM function. For the STM-N signals, SSMBs are
extracted from S1 bytes. For the E1 signals, SSMBs are extracted from Sa4-Sa8
bits of timeslot 0 in an even-numbered frame. The extracted SSMs are sent to the
CLK boards through the Ethernet. The interface boards receive the SSM level from
the CLK boards and send it out through the STM-N or E1 interfaces. The SSM
handling process complies with ITU-T Recommendations G.703, G.704 and G.781.

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4.4 Clock Signal Flow

The UMG8900 provides high accuracy stratum 2 or 3 clock as the reference clock
of its lower-level devices or other access network devices. The independent CLK or
the clock sub board is used to extract and distribute clock signals and output
various service clock signals needed by the system.

4.4.1 Clock Signal Extracting Flow

The UMG8900 supports the clock reference sources including the GPS/GLONASS,
2048 kHz or 2048 kbit/s BITS clock, and 8 kHz line clock. The independent CLK
mode supports the above three clock reference sources. The clock sub board mode
supports the 2048 kHz or 2048 kbit/s BITS clock and 8 kHz line clock.
 The UMG8900 receives two channels of 8 kHz line clock signals from the
interface boards. The interface boards that provide 8 kHz line clock include the
E32, T32, S2L, P4L and P1H. They can be selected through cable distribution.
Each interface board provides one interface, where two cables are inserted.
The two cables are connected with the master and salve CLK boards
respectively and carry two channels of clock signals.
 One channel of the clock signals is the satellite timing signal input from the
GPS/GLONASS system. A single GPS receiving card or GPS/GLONASS
integrated receiving card can be used to receive the signals.
 Another channel of the signals is the 2048 kbit/s or 2048 kHz clock signals
from the BITS synchronous clock system. The type of input signals can be set
through the software.

4.4.2 Clock Signal Distributing Flow

The clock signal distributing process differs in the independent CLK mode and the
clock sub board mode.

I. Independent CLK Mode

The CLK can output:

 18 channels of 16 kHz line clock signals to the NET boards in the frame where
the CLK boards are located through the backplane and to the NET boards in
other frames through clock distribution cables.
 One channel of 2048 kbit/s or 2048 kHz external synchronous clock signals to
the access network or other devices.

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 Note:
In the SSM-256 single-frame or multi-frame networking, the clock signals are sent
from the CLK boards to the NET boards in the main control frame through the
backplane instead of external cables. In the SSM-32 single-frame or multi-frame
networking, the clock signals are sent from the CLK boards to the MTNC boards in
the main control frame through the backplane.

After the NET receives the 16 kHz line clock signals from the clock distribution
cables, it synthesizes the signals into the following three types of clocks through its
internal clock processing module:
 32.768 MHz clock: the TDM HW synchronous clock signals for the TDM bearer
processing
 38.88 MHz clock: the TDM SDH synchronous clock, including the synchronous
clock required by the Asynchronous Transfer Mode (ATM) and Packet Over
SDH (POS) services in the SDH transmission mode
 2 kHz clock: the TDM SDH frame clock
The NET board drives the three types of synthesized clocks and sends them
respectively to the service boards that use different bearer modes in the UMG8900.
For the NET in the cascading mode, the clock distributing flow is the same as the
above.

II. Clock Sub Board Mode

The clock sub board directly outputs the 32.768 MHz, 38.88 MHz and 2 kHz clock
signals required by the system. The clock sub board sends clock signals to the
boards in the frame where it is located through the backplane. It sends clock
signals to the TNC boards in other frames through TDM cascading cables between
frames. Then the MTNC boards provide clock signals for the service boards in the
local frame.

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