VLSI design
DAY 91 VLSI
Fibonacci Sequence
Generator using FSM
Fibonacci Sequence Generator using FSM
module fibonacci(
input clk, rst,
output reg rd,
output [5:0]value);
reg [6:0]pr,cr;
reg [5:0]counter;
always @(posedge rst)
begin
pr <= 6'd0;
cr <= 6'd1;
counter <= 6'd1;
end
always @(posedge clk)
begin
counter <= counter + 1;
cr <= cr+pr;
pr <= cr;
if (counter == 1)
rd <= 1;
end
assign value = cr;
1
endmodule
Testbench Fibonacci Sequence Generator using FSM
module tb_fibonacci;
reg clk,rst;
#10 seq_in = 0;
wire [5:0]value;
#10 seq_in = 1;
wire rd;
#20 $finish;
fibonacci dut ( end
.clk(clk), initial begin
.rst(rst), $monitor("Time=%0t | seq_in=%b | seq_detected=%b |
.value(value), State=%b", $time, seq_in, seq_detected, uut.current_state);
.rd(rd) end
); endmodule
always begin
#5 clk = ~clk; // 10ns period, 50 MHz clock
end
initial begin
clk =0;rst =1;
#5 rst =0;
2
#200; 1
$monitor("At time %t, Fibonacci Number: %d ", $time, value);
#200 $finish;
RTL design of Fibonacci Sequence Generator using FSM
Output Waveform
Fibonacci Sequence Generator using FSM
Observations:
1️⃣ The Fibonacci sequence is generated correctly based on the previous two values.
2️⃣ The FSM transitions through defined states to produce the Fibonacci numbers.
3️⃣ The done signal is activated after generating 10 Fibonacci numbers.
4️⃣ Reset functionality ensures the circuit initializes properly at the start.
VLS I
DESIGN
THANK YOU!
