MINI PARIHAR
Email Id : [email protected]
Linkedin : https://www.linkedin.com/in/mini-parihar-76072219b/
Contact no. : (+91) 9193777355 / 8171024451
CAREER OBJECTIVE
Passionate Design Verification Engineer having skills in hardware verification. Armed with a solid understanding of hardware design
principles and verification methodologies, I am detail-oriented, analytical, and skilled in troubleshooting. I am driven to ensure the
functionality and reliability of complex designs. My objective is to leverage my expertise in Design Verification to make significant
contributions to the VLSI industry, delivering dependable designs that push the boundaries of innovation.
WORK EXPERIENCE
● 4 months (Nov 2023 – March 2024) experience with Lemon Flip solutions, Hyd as a Junior Verification Engineer.
● 6 months (Sep 2022 – Feb 2023) Training experience with Vlsi for All Pvt. Ltd. as a RTL Design and Verification Trainee.
● 6 months (Jan 2022 – June 2022) experience with Marquistech Pvt. Ltd. Noida as a Quality Test Engineer.
SUMMARY OF QUALIFICATIONS
● Experience in pre-silicon verification with IP level verification.
● Experience in developing Test Cases.
● Experience in writing Test cases in SV and Verification methodology UVM.
● Experience in Designing the SPI Slave IP in Verilog for ADC module.
● Experience in developing SV testbench for different protocols like APB, SPI & Memory.
● Experience in developing UVM testbench for AXI-Lite protocol.
● Knowledge in AMBA APB, AHB, AXI.
EDUCATIONAL QUALIFICATION
Course College CGPA/Percentage Academic Year
Raja Balwant Singh Engineering
B.Tech 78.6% 2018 - 2022
Technical campus, Agra
12th Milton Public School, Agra 69.8% 2017
10th St. SGIC, Agra 90.5% 2015
VERIFICATION SKILLS
HDL Languages : Verilog HDL & System Verilog (SV)
Methodology : Universal Verification Methodology (UVM)
Protocols : SPI, I2C, AMBA (APB, AHB, AXI)
Concept : Digital Logic Design, Static timing analysis (STA), Linux
EDA Tool : Questa Sim, EDA Playground, Gvim
VERIFICATION PROJECTS
Design Verification for AXI-Lite Protocol
Role in the Project :
● Created the test plans for the project specific to AXI protocol Slave.
● Developed the testbench using UVM methodology.
● Done the functional Coverage for the project.
Design and Verification of SPI interface for ADC
Role in the Project :
● Designed a SPI slave for the interfacing to ADC, Added different features like 4 pin, SPI mode and Pin mode, Data Streaming
and many more.
● Synthesized the design using xilinx vivado.
● Verify the design with different Test Cases.
Design and Verification of Synchronous FIFO & Asynchronous FIFO
Implementation :- Verilog & Verification :- Verilog / System Verilog
● Designed both FIFO with Verilog as well as SV .
● Generated a TB using the Verilog / System Verilog Testbench Architecture. And written test cases for the verification of
functionality as expected.
Design and Verification of the APB Protocol
Implementation :- Verilog & Verification :- Verilog / System Verilog
● Design a RAM with APB protocol interfacing and verifying it with SV testbench.
Design an AMBA 3 APB Protocol for 2 slaves using an interface between them and generate the stimulus through the Verilog
testbench.
● Able to transfer the 8-bit of data for an 8-bit address.
● Develop the block to generate the slverr (Slave Error) for different scenarios.
● Transformation of data between the master and slave with the help of system generated signals.
Design and Verification of the I2C Protocol
Implementation :- Verilog & Verification :- System Verilog
● Successfully designed and executed the I2C master and slave and Verification is performed using a System Verilog Testbench.
Design and Verification of the Configurable Memory
Implementation :- Verilog Verification :- Verilog
● Design a memory which can be configured for user provided depth and width.
● Write a test bench which supports the concept of front door and back door access.
● Write or read from different segments for the memory like half read/write, depth/4 read/write.
● Write test cases for the verification of functionality as expected.
LANGUAGE
● Hindi
● English
EXTRA-CURRICULAR ACTIVITIES AND AWARDS
● Compion at Safecity (women safety organization)
● Winner of the Soliloquy Contest, on writing skill with 4 team members and as a teammate from the organization FEA.
● Winner of the SunoGraphy Contest
● Winner of All Ears Contest, on listening skills with 5 team members as a leader.
● 2nd position holder in Speech Contest.
● Attended Training in various Signalling and Telecom Equipments, Agra - North Central Railway
