Chapter V.
Sequential logic systems I
Definitions
• A system is said to be sequential when the output(s) depend on the
combination of input variables and the previous state of the outputs.
Inputs Outputs
Sequential
…. Processing ….
Mrs Tamen 2
Definitions
Notes
ØThe same cause (same combination of inputs) can generate different
outputs;
ØTime may be a trigger;
ØThe output may persist if the cause disappears.
• We have :
𝑺𝒊 = 𝒇(𝒆𝟏, … , 𝒆𝒋, … , 𝒔𝟏, … , 𝒔𝒍, … , 𝒕)
Mrs Tamen 3
Definitions
• Chronogram
ØA timing chart is a representation of the evolution of a signal or the
function of a system as a function of time.
Mrs Tamen 4
Definitions
• Synchronous or asynchronous processing
ØA processing is said to be synchronous to an external event when the
evolution of the inputs is only taken into account at specific times of
the external event.
ØA processing is said to be asynchronous if the evolution of the inputs
is taken into account as soon as it arrives.
ØThis notion of synchronization is mainly used in the operation of flip-
flops and memory components to synchronize several components
between them.
Mrs Tamen 5
Definitions
• Synchronization events
Synchronization Signal (Clock)
Rising edge
(positive)
Falling edge
(negative)
Low level Hign levelt
Symboles
Rising edge High level Falling edge Low level
Mrs Tamen 6
Definitions
• Example: Concept of chronogram
ØConsider a sequential circuit with a single input and a single output. It
will be assumed that the output follows the input at the rising edge of
the clock.
Changes in input not taken in consideration because
they are between two synchronization events
Synchronization Signal
Rising edge
Input
Output
Mrs Tamen 7
Flip flop
• Definitions
üThey are called bistable flip-flops because these flip-flops have two stable
states (‘0’ and ‘1’). This means that if there is no intervention on the flip-flops,
they remain locked in their last state.
üThe role of a flip-flop is to memorize elementary information. It is a 1-bit
memory. It has two complementary outputs 𝑄 and 𝑄. 0
Mrs Tamen 8
Flip flop
• RS flip-flop using NOR gates
R
Q
$
Q
S
Mrs Tamen 9
Flip flop
• Truth Tables
• NOR
X Y 𝑋+𝑌
0 0 1
0 1 0
1 0 0
1 1 0
Mrs Tamen 10
Flip flop
• Truth Tables
• RS S R 𝑄 𝑄0
0 0 𝑄 𝑄0 Memory
0 1 0 1 RTZ = Reset to 0
1 0 1 0 Set= Set to 1
1 1 X X Prohibited
Mrs Tamen 11
Flip flop
• Remarks
ØIf we apply S=1 and R=0, we impose the state of the outputs 𝑄 and
(𝑄0 ) to 1 and 0 respectively. (S = Set = Set to 1, R = Reset = Reset to
zero).
ØThis state is maintained when both inputs return to 0.
ØThe configuration S = 1 and R = 1 should be avoided because here, it
causes the two complementary outputs 𝑄 and (𝑄0 ) to be reset to zero,
which is inconsistent with Boolean algebra.
Mrs Tamen 12
Flip flop
• Symbol
𝑆 𝑄
𝑅 𝑄0
Mrs Tamen 13
Flip flop
• RST, RS-CLOCK or RSH flip-flop
ØThe RST flip-flop is an RS flip-flop for which the S and R inputs are
only taken into account in coincidence with a control signal provided
by a clock. We then have a synchronous RS flip-flop.
𝑆 𝑄
Clk
𝑅 𝑄(
Bascule RS sensible au front montant
Mrs Tamen 14
Flip flop
• JK flip flop
ØIt is an RST flip-flop on which the combination J=K=1 is authorized. It
is carried out by connecting the output 𝑄0 via an AND gate to the
input S and by connecting the output Q via an AND gate to the input
R. (JK= jokey/ king, J=Jokey, K=King).
Mrs Tamen 15
Flip flop
• Circuit with RS flip flop:
J 𝑆 𝑄
𝑄( Clk
K 𝑅 𝑄(
Q
Mrs Tamen 16
Flip flop
• Truth Table
6
𝑺 = 𝑱𝑸
ü4 Jn-1 Kn-1 Qn-1 𝑄0 n-1 S R Qn 𝑄0 n
𝑹 = 𝑲𝑸
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 1 0 1 0 0 0 1
0 1 1 0 0 1 0 1
1 0 0 1 1 0 1 0
1 0 1 0 0 0 1 0
1 1 0 1 1 0 1 0
1 1 1 0 0 1 0 1
Mrs Tamen 17
Flip flop
• Note
ØThe combination S= R= 1 is never encountered.
• Reduced truth table
J K 𝑄 𝑄%
0 0 𝑄 𝑄% Memory
0 1 0 1 RTZ = Reset to 0
1 0 1 0 Set= Set to 1
1 1 𝑄% Q Switching
Mrs Tamen 18
Flip flop
• Symbol
𝐽 𝑄
Clk
𝐾 𝑄(
JK flip-flop sensitive to rising edge
Mrs Tamen 19
Flip flop
• D flip flop
ØA D flip-flop (Delay) is obtained from a JK flip-flop by simultaneously
having data on input J and its inverse on input K.
D 𝐽 𝑄
Clk
𝐾 𝑄%
Mrs Tamen 20
Flip flop
• From the truth table of the JK flip-flop, we can write:
𝐷()* = 1 ⇒ 𝐽()* = 1 ⇒ 𝐾()* = 0 ⇒ 𝑄( = 1
4
𝐷()* = 0 ⇒ 𝐽()* = 0 ⇒ 𝐾()* = 1 ⇒ 𝑄( = 0
⇒ 𝑄@ = 𝐷@AB
Mrs Tamen 21
Flip flop
Symbol Truth Table
𝐷 𝑄
𝐷 𝑄
Clk 𝑄(
D flip-flop sensitive to falling edge 0 0
1 1
Mrs Tamen 22
Flip flop
• T flip flop
ØIn a JK flip-flop, we see that if J=K=1, the state of the output is
inverted every clock cycle. A T (Trigger) flip-flop is obtained from a JK
flip-flop by injecting the same data into inputs J and K.
Symbol Truth Table
T $ "
! "
Clk ! "
% "# Clk "#
0 "
T flip-flop sensitive to rising edge
1 "#
Mrs Tamen 23
Flip flop Transition Tables
• RS
• Flip flop
𝑄A Q R S R S
0 0 0 0 X 0
1 0
0 1 0 1 0 1
1 0 1 0 1 0
1 1 0 0 0 X
0 1
Mrs Tamen 24
Flip flop Transition Tables
• RS flip flop
𝑄A Q R S
0 0 X 0
0 1 0 1
1 0 1 0
1 1 0 X
Mrs Tamen 25
Flip flop Transition Tables
• JK flip flop
𝑄A Q J K J K
0 0 0 0 0 X
0 1
0 1 1 0 1 X
1 1
1 0 0 1 X 1
1 1
1 1 0 0 X 0
1 0
Mrs Tamen 26
Flip flop Transition Tables
• JK flip flop
𝑄A Q J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Mrs Tamen 27
Flip flop Transition Tables
• D flip flop
𝑄A Q D
0 0 0
0 1 1
1 0 0
1 1 1
Mrs Tamen 28
Flip flop Transition Tables
• T flip flop
𝑄A Q T
0 0 0
0 1 1
1 0 1
1 1 0
Mrs Tamen 29
Charging Flip flops
• RS flip flop
A 𝑄A 𝑄 R S
0 0 0 X 0 𝑺=𝑨
0 1 0 1 0 6
𝑹=𝑨
1 0 1 0 1
1 1 1 0 X
Mrs Tamen 30
Charging Flip flops
• JK flip flop
A 𝑄A 𝑄 J K
0 0 0 0 X 𝑱=𝑨
0 1 0 X 1 𝑲=𝑨6
1 0 1 1 X
1 1 1 X 0
Mrs Tamen 31
Charging Flip flops
• D flip flop
A 𝑄A 𝑄 D
0 0 0 0
0 1 0 0
1 0 1 1 𝑫=𝑨
1 1 1 1
Mrs Tamen 32
Charging Flip flops
• T flip flop
A 𝑄A 𝑄 T
0 0 0 0 T= 𝑨 ⊕ 𝑸A
0 1 0 1
1 0 1 1
1 1 1 0
Mrs Tamen 33
Flip flop Chronograms
• Important Information IE : 𝑄 = 1, 𝑄0 = 0.
• RS flip flop
Mrs Tamen 34
Flip flop Chronograms
Bascule JK
Mrs Tamen 35
Flip flop Chronograms
• JK flip flop
• Initial State:
Q=0
Mrs Tamen 36
Flip flop Chronograms
Mrs Tamen 37
Flip flop Chronograms
𝐷 𝑄
• initial state : Q=0 H 𝑄(
Mrs Tamen 38
Asynchronous Clear et Preset inputs
• The asynchronous inputs (they must be used in the absence of a clock
signal) Pr (Preset) and Cr (Clear) make it possible to assign the initial
state of the flip-flop. In normal functioning these two inputs must be
maintained at 1. When the clock signal is inhibited, we have the
following truth table:
Pr Cr Q
1 1 Q
0 1 1
1 0 0
Mrs Tamen 39
