Computer Organization and Architecture
Course Code: E2UC301T
Galgotias University
COA Assignment-1
All questions are mandatory
Deadline: 03.10.24
1. Explain why each of the following microoperations cannot be executed during a single clock pulse in
the system shown in the common BUS system . Specify a sequence of microoperations that will
perform the operation.
2. Draw a timing diagram by assuming that SC is cleared to 0 at time T3 if control signal c7 is active.
C7T3: SC <- 0 .
C7 is activated with the positive clock transition associated with T1.
3. An instruction at address 021 in the basic computer has I = 0, an operation code of the AND
instruction, and an address part equal to 083 (all numbers are in hexadecimal). The memory word at
address 083 contains the operand B8F2 and the content of AC is A937. Go over the instruction
cycle and determine the contents of the following registers at the end of the execute phase: PC, AR,
DR, AC, and lR. Repeat the problem six more times starting with an operation code of another
memory-reference instruction.
4. A computer uses a memory of 65,536 words with eight bits in each word. It has the following
registers: PC, AR, TR (16 bits each), and AC, DR, IR (eight bits each). A memory-reference
instruction consists of three words: an 8-bit operation-code (one word) and a 16-bit address (in the
next two words). All operands are eight bits. There is no indirect bit.
a. Draw a block diagram of the computer showing the memory and registers
b. Draw a diagram showing the placement in memory of a typical three word instruction and the
corresponding 8-bit operand.
c. List the sequence of microoperations for fetching a memory reference instruction and then
placing the operand in DR. Start from timing signal To.
5. Assume that the first six memory-reference instructions in the basic computer are to be changed to
the instructions specified in the following table. EA is the effective address that resides in AR during
time T4. Assume that the adder and logic circuit of basic computer registers connected to common
bus can perform the exclusive-OR operation AC <- AC ⊕ DR. Assume further that the adder and
logic circuit cannot perform subtraction directly. The subtraction must be done using the 2' s
complement of the subtrahend by complementing and incrementing AC. Give the sequence of
register transfer statements needed to execute each of the listed instructions starting from timing T,.
Note that the value in AC should not change unless the instruction specifies a change in its content.
You can use TR to store the content of AC temporary or you can exchange DR and AC.
