LMH34400

SBOSA56B – MARCH 2022 – REVISED MARCH 2023

LMH34400 240-MHz, Single-Ended, Transimpedance Amplifier with Integrated Clamp

1 Features 3 Description
• Integrated gain: 40 kΩ The LMH34400 is the industries' smallest, fixed-
• Performance, CPD = 1 pF: gain, single-ended transimpedance amplifier for light
– Bandwidth: 240 MHz detection and ranging (LIDAR) applications and laser
– Input-referred noise: 50 nARMS distance measurement systems. The LMH34400 can
– Rise, fall time: 1.5 ns produce 1.0 VPP of output swing and has an input
• Integrated ambient light cancellation referred noise of 50 nARMS.
• Integrated 100-mA protection clamp The LMH34400 has an integrated 100-mA clamp
• Quiescent current: 20 mA that protects the amplifier and allows the device to
• Low-power mode current: 1.5 mA recover rapidly from an overloaded input condition.
• Temperature range: –40°C to +125°C The LMH34400 also features an integrated ambient
2 Applications light cancellation (ALC) circuit that can be used
instead of AC coupling between the photodiode and
• Mechanically scanning LIDAR the amplifier to save board space and system cost.
• Solid-state scanning LIDAR The ALC loop should be disabled in cases where
• Laser distance meter frequency signal content less than 400 kHz needs to
• Optical ToF position sensor be measured.
• Drone vision
• Industrial robot LIDAR The LMH34400 can be placed in low-power mode
• Mobile robot LIDAR using the EN pin to conserve power when the
• Vacuum robot LIDAR amplifier is not being used. This feature allows several
LMH34400 amplifiers to be multiplexed to the input of
. the next stage of the receive signal chain with the EN
. control pin serving as the multiplexer select function.
The LMH34400 offers single-ended output and is
. optimized to be used with time-to-digital converter
. (TDC) based LIDAR systems.
. Package Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
.
LMH34400 DRL (SOT563, 6) 1.60 mm × 1.20 mm
.
(1) For all available packages, see the package option
. addendum at the end of the data sheet.

. .
VDD EN .
95

100-mA
92
Transimpedance Gain (dB)

Clamp
12.2 k
IN
89

10 
86
TIA 3.6x OUT

83

VBIAS Ambient Light
Cancellation
80
IDC EN CIN = 1.0 pF
77
1M 10M 100M 1G
Frequency (Hz)
GND
Transimpedance Bandwidth vs Frequency
Simplified Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................13
2 Applications..................................................................... 1 8 Application and Implementation.................................. 15
3 Description.......................................................................1 8.1 Application Information............................................. 15
4 Revision History.............................................................. 2 8.2 Typical Application.................................................... 16
5 Pin Configuration and Functions...................................3 8.3 Typical Application.................................................... 18
6 Specifications.................................................................. 4 8.4 Power Supply Recommendations.............................19
6.1 Absolute Maximum Ratings........................................ 4 8.5 Layout....................................................................... 20
6.2 ESD Ratings............................................................... 4 9 Device and Documentation Support............................21
6.3 Recommended Operating Conditions.........................4 9.1 Device Support......................................................... 21
6.4 Thermal Information....................................................4 9.2 Documentation Support............................................ 21
6.5 Electrical Characteristics.............................................5 9.3 Receiving Notification of Documentation Updates....21
6.6 Electrical Characteristics: Logic Threshold and 9.4 Support Resources................................................... 21
Switching Characteristics.............................................. 6 9.5 Trademarks............................................................... 21
6.7 Typical Characteristics................................................ 7 9.6 Electrostatic Discharge Caution................................21
7 Detailed Description......................................................12 9.7 Glossary....................................................................21
7.1 Overview................................................................... 12 10 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 12 Information.................................................................... 21
7.3 Feature Description...................................................13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (August 2022) to Revision B (March 2023) Page

• Added the Typical Application, Design Requirements, and Detailed Design Procedure sections.................... 18

Changes from Revision * (March 2022) to Revision A (August 2022) Page

• Changed the status of the data sheet from: Advanced Information to: Production Data ...................................1

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5 Pin Configuration and Functions

IN 1 6 IDC_EN

VDD 2 5 GND

EN 3 4 OUT

Figure 5-1. DRL Package,

6-Pin SOT563
(Top View)

Table 5-1. Pin Functions

PIN
TYPE(2) DESCRIPTION
NAME NO.
EN 3 I Device enable pin. EN = logic low = normal operation (default)(1); EN = logic high = low-power mode.
GND 5 I Amplifier ground.
Ambient light cancellation loop enable. IDC_EN = logic low = enable DC cancellation (default)(1);
IDC_EN 6 I
IDC_EN = logic high = disable DC cancellation.
IN 1 I Transimpedance amplifier input.
OUT 4 O Amplifier output.
VDD 2 I Positive power supply.

(1) TI recommends driving a digital pin with a low-impedance source rather than leaving the pin floating because fast-moving transients
can couple into the pin and inadvertently change the logic level.
(2) I = input, O = output

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Total supply voltage 3.65 V
Voltage at output pin 0 VDD V
Voltage at logic pins –0.25 VDD V
IIN Continuous current into IN 25 mA
IOUT Continuous output current 35 mA
TJ Junction temperature 150 °C
TA Operating free-air temperature –40 125 °C
Tstg Storage temperature –65 150 °C

(1) If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±1000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per ANSI/ESDA/
±250
JEDEC JS-002, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Total supply voltage 3 3.3 3.45 V
TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

LMH34400
THERMAL METRIC(1) DRL (SOT-563) UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 201.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 101.5 °C/W
RθJB Junction-to-board thermal resistance 83.2 °C/W
ΨJT Junction-to-top characterization parameter 5.4 °C/W
ΨJB Junction-to-board characterization parameter 82.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

VDD = 3.3 V, CPD (1) = 1 pF, EN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω (Output is AC-coupled for AC performance parameters;
for DC performance parameters load is referenced to 1V), and TA = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 100 mVPP 240 MHz
LSBW Large-signal bandwidth VOUT = 1 VPP 240 MHz
tR, tF Rise and fall time VOUT = 100 mVPP, pulse width = 10 ns 1.5 ns
Slew rate (2) VOUT = 1 VPP, pulse width = 10 ns 470 V/µs
Overload recovery time (1% settling) IIN = 10 mA, pulse width = 10 ns 18 ns
Overload pulse extension (3) IIN = 10 mA, pulse width = 10 ns 3 ns
eN Output noise density f = 10 MHz 94 nV/√Hz
iN Integrated input-referred noise f = DC to 250 MHz 50 nARMS
ZOUT Closed-loop output impedance f = 50 MHz 10 Ω
DC PERFORMANCE
Z21 Small-signal transimpedance gain (4) 33 40 46 kΩ
VO Default output voltage IIN = 0 µA 0.93 1 1.07 V
ΔVO/ΔTA Output voltage drift ±20 µV/°C
INPUT PERFORMANCE
RIN Input Resistance 50 100 150 Ω
VIN Default input bias voltage Input pin floating 2.44 2.5 2.55 V
ΔVIN/ΔTA Default input bias voltage drift Input pin floating 1.1 mV/°C
Z21 < 3-dB degradation from
IIN DC input current range 27 34 µA
IIN = 5 µA
OUTPUT PERFORMANCE
2.05 2.3 V
VOH Output voltage swing (high) (5)
TA = –40°C to 125°C 2.3 V
0.4 0.6 V
VOL Output voltage swing (low) (6)
TA = –40°C to 125°C 0.45 V
IIN = 15 µA, RL = 25 Ω 16 19 22
IOUT Linear output drive (source) TA = –40°C, IIN = 15 µA, RL = 25 Ω 19 mA
TA = 125°C, IIN = 15 µA, RL = 25 Ω 19
ISC Output short-circuit current (7) 85 mA
ZOUT DC output impedance (amplifier enabled) 7 10 13 Ω
AMBIENT LIGHT CANCELLATION PERFORMANCE (IDC_EN = 0 V) (8)

IIN = 0 µA → 100 µA 6 µs
Settling time
IIN = 100 µA → 0 µA 35 µs
Ambient light current cancellation range Output offset shift from IDC = 5 µA < ±10 mV 2 3 mA
POWER SUPPLY
16 20 24
IQ Quiescent current TA = 125°C 22.5 mA
TA = –40°C 18

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6.5 Electrical Characteristics (continued)

VDD = 3.3 V, CPD (1) = 1 pF, EN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω (Output is AC-coupled for AC performance parameters;
for DC performance parameters load is referenced to 1V), and TA = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SHUTDOWN
1.2 1.5 1.7
IQ Disabled quiescent current (EN = VDD) TA = –40°C 1.4 mA
TA = 125°C 1.6
EN and IDC_EN pins input bias current 65 90 µA

(1) Input capacitance of photodiode.

(2) Average of rising and falling slew rate.
(3) Pulse width extension measured at 50% of pulse height of square wave.
(4) Gain measured at the amplifier output pin when driving a 100-Ω resistive load. At higher resistor loads the gain increases.
(5) Photodiode anode biased to a negative voltage
(6) Photodiode cathode biased to a positive voltage
(7) Device cannot withstand continuous short-circuit.
(8) Enabling the ambient light cancellation loop adds noise to the system.

6.6 Electrical Characteristics: Logic Threshold and Switching Characteristics

VDD = 3.3 V, CPD (1) = 1 pF, EN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω (Output is AC-coupled for AC performance parameters;
for DC performance parameters load is referenced to 1V), and TA = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC THRESHOLD PERFORMANCE
Amplifier disabled above this voltage 1.6 2 V
EN control threshold voltage
Amplifier enabled below this voltage 0.8 1.2 V
Ambient light cancellation loop disabled
1.6 2 V
above this voltage
IDC_EN control threshold voltage
Ambient light cancellation loop enabled
0.8 1.2 V
below this voltage
EN CONTROL TRANSIENT PERFORMANCE
Ambient loop disabled, fIN = 25 MHz, VOUT
Enable transition-time (1% settling) 200 ns
= 1 VPP, IDC = 0 µA
Ambient loop disabled, fIN = 25 MHz, VOUT
Disable transition-time (1% settling) 3.5 ns
= 1 VPP, IDC = 0 µA
Ambient loop enabled, fIN = 25 MHz, VOUT =
Enable transition-time (1% settling) 10 µs
1 VPP, IDC = 100 µA
Ambient loop enabled, fIN = 25 MHz, VOUT =
Disable transition-time (1% settling) 3.5 ns
1 VPP, IDC = 100 µA

(1) Input capacitance of photodiode.

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6.7 Typical Characteristics

At VDD = 3.3 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω, and TA = 25°C (unless otherwise
noted)

95 95

92 92
Transimpedance Gain (dB)

Transimpedance Gain (dB)

89 89

86 86

83 CIN = PCB Only 83 CIN = PCB Only

CIN = 0.5 pF CIN = 0.5 pF
CIN = 1.0 pF CIN = 1.0 pF
80 CIN = 2.2 pF 80 CIN = 2.2 pF
CIN = 4.7 pF CIN = 4.7 pF
CIN = 10 pF CIN = 10 pF
77 77
1M 10M 100M 1G 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
VOUT = 100 mVPP VOUT = 1 VPP
Figure 6-1. Small-Signal Response vs Input Capacitance Figure 6-2. Large-Signal Response vs Input Capacitance
95

92
Transimpedance Gain (dB)

89

86

83
TA = -40 C
80 TA = 25 C
TA = 85 C
TA = 125 C
77
1M 10M 100M 1G
Frequency (Hz)
VOUT = 100 mVPP VOUT = 1 VPP
Figure 6-3. Small-Signal Response vs Ambient Temperature Figure 6-4. Large-Signal Response vs Ambient Temperature
1
Amplifier Enabled
Amplifier Disabled
Normalized Transimpedance (dB)

0 10k
Output Impedance ()

-1

-2 1k

-3
100
-4

-5 ALC Disabled
10
ALC Enabled
-6
1M 10M 1M 10M 100M
Frequency (Hz) Frequency (Hz)

IDC_IN = 100 μA .

Figure 6-5. Low-side Frequency Response vs Ambient Light Figure 6-6. Closed-Loop Output Impedance vs Frequency
Cancellation

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6.7 Typical Characteristics (continued)

At VDD = 3.3 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω, and TA = 25°C (unless otherwise
noted)

10 10
Input Noise (pA/Hz)

Input Noise (pA/Hz)

CPD = none
CPD = 0.5 pF
TA = -40 C CPD = 1 pF
TA = 25 C CPD = 2 pF
TA = 85 C CPD = 4.7 pF
TA = 125 C CPD = 10 pF
1 1
10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
. .
Figure 6-7. Input Noise Density vs Ambient Temperature Figure 6-8. Input Noise Density vs Input Capacitance
2.5
IDC = 0 A 0.1 VPP
IDC = 10 A 1.0 VPP
2.25
IDC = 100 A 1.2Vpp
IDC = 1 mA
Input Noise (pA/Hz)

2
Output Voltage (V)

10
1.75

1.5

1.25

1 0.75
10k 100k 1M 10M 100M 1G Time (5 ns/div)
Frequency (Hz) .
IDC_EN = 0 V
Figure 6-10. Pulse Response vs Output Swing
Figure 6-9. Input Noise Density vs Ambient Light DC Current
2.5 3.5
IIN = 25 A EN
2.25 IIN = 1 mA 3 Output

2 2.5
Output Voltage (V)

1.75 2
Voltage (V)

1.5 1.5

1.25 1

1 0.5

0.75 0

0.5 -0.5
Time (5 ns/div) Time (50 ns/div)
. .
Figure 6-11. Overloaded Pulse Response Figure 6-12. Turn-On Time

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6.7 Typical Characteristics (continued)

At VDD = 3.3 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω, and TA = 25°C (unless otherwise
noted)

3.5 2.5

3 2.25

2.5 2

Output Voltage (V)

2 1.75
Voltage (V)

EN 1.5
1.5
Output
1 1.25

0.5 1

0 0.75

-0.5 0.5
Time (50 ns/div) Time (1 s/div)

. IDC_IN = 0 µA → 100 µA
Figure 6-13. Turn-Off Time Figure 6-14. Ambient Loop Cancellation Settling Time
1.5

1.25
Output Voltage (V)

0.75

0.5

0.25

0
Time (1 s/div)
IDC_IN = 100 µA → 0 µA
positive current is sinking current into the photodiode's
Figure 6-15. Ambient Loop Cancellation Settling Time cathode
Figure 6-16. Transimpedance Gain vs Input Current
2.7 2.65

2.4
2.6
2.1
Input Bias Voltage (V)
Input Bias Voltage (V)

1.8 2.55

1.5
2.5
1.2

0.9
2.45 Unit 1
0.6 Unit 2
Unit 3
0.3 2.4
0 0.5 1 1.5 2 2.5 3 3.5 -40 -20 0 20 40 60 80 100 120 140
Supply Voltage (V) Temperature (C)

. .

Figure 6-17. Input Bias Voltage vs Supply Voltage Figure 6-18. Input Bias Voltage vs Ambient Temperature

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6.7 Typical Characteristics (continued)

At VDD = 3.3 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω, and TA = 25°C (unless otherwise
noted)

25 30

24
25
23
Quiescent Current (mA)

Quiescent Current (mA)

20
22

21 15

20
10
19
Unit 1 5 TA = -40 C
18 Unit 2 TA = 25 C
Unit 3 TA = 125 C
17 0
-40 -20 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5
Temperature (C) Supply Voltage (V)
. .
Figure 6-19. Quiescent Current vs Ambient Temperature Figure 6-20. Quiescent Current vs Supply Voltage
2.5 25
TA = -40 C
TA = 25 C
2.25 TA = 125 C
20
Quiescent Current (mA)
Output Voltage (V)

2
15
1.75

10
1.5

1.25 5

1 0
0 10 20 30 40 50 60 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3
Input Current (A) Enable Voltage (EN) (V)
. .
Figure 6-21. Output Voltage vs Input Current Figure 6-22. Logic Threshold vs Ambient Temperature
1750

1500

1250
Device Count

1000

750

500

250

0
16 17 18 19 20 21 22 23 24
Quiescent Current (mA)
μ = 21.1 mA, σ = 0.38 mA μ = 38.5 kΩ, σ = 1.2 kΩ
Figure 6-23. Quiescent Current Distribution Figure 6-24. Transimpedance Gain Distribution

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6.7 Typical Characteristics (continued)

At VDD = 3.3 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω, and TA = 25°C (unless otherwise
noted)

1500 1250

1250
1000

1000
Device Count

Device Count
750
750

500
500

250 250

0 0
0.93 0.95 0.97 0.99 1.01 1.03 1.05 1.07 9 9.5 10 10.5 11 11.5 12 12.5 13
Default Output Voltage (V) Output Impedance ()
μ = 0.99 V, σ = 0.0073 V μ = 11 Ω, σ = 0.38 Ω, Device Enabled
Figure 6-25. Default Output Voltage Distribution Figure 6-26. Output Impedance (ZOUT) Distribution

μ = 1.6 kΩ, σ = 0.013 kΩ, Device Disabled

Figure 6-27. Output Impedance (ZOUT) Distribution

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7 Detailed Description
7.1 Overview
The LMH34400 is a single-channel, single-ended output, high-speed transimpedance amplifier (TIA) and
features several integrated functions geared towards light detection and ranging (LIDAR) and pulsed time-of-
flight (ToF) systems. The LMH34400 is designed to work with photodiodes (PDs) whose anodes are biased
to a negative voltage and cathodes tied to the amplifier input so that the amplifier sources the photocurrent.
The LMH34400 is offered in a space-saving 1.60 mm × 1.20 mm, 6-pin SOT563 package and is rated over a
temperature range from –40°C to +125°C.
7.2 Functional Block Diagram
VDD

100-mA RT
Clamp Difference Amplifier (3.6x)
Mid-scale
buffer RG RF VDC = 1.0 V
IN
TIA
Photodiode

+
Ambient Light
Cancella
on OUT
IDC EN - 10
-VBIAS

RG
TIA
Mid-scale RF
buffer
RT

GND EN

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7.3 Feature Description

7.3.1 Clamping and Input Protection
The LMH34400 is designed to work with photodiode (PD) configurations that can source or sink current; the
LMH34400, however, is optimized for a sinking current configuration. It is assumed that the LMH34400 device
is being used with a PD that is configured with its cathode tied to the amplifier input and the anode tied to a
negative supply voltage, unless stated otherwise.
The LMH34400 features two internal clamps, a fast recovery clamp and a soft clamp. The fast recovery clamp
is the active clamp when the photodiode is sinking a photocurrent. The soft clamp is the active clamp when the
photodiode is sourcing a photocurrent.
Stray reflections from nearby objects with high reflectivity can produce large output current pulses from the
PD. The linear input range of the LMH34400 is approximately 30 µA. Input currents in excess of the linear
current range cause the internal nodes of the amplifier to saturate, which increases the amplifier recovery time.
The end result is a broadening of the output pulse leading to blind zones in the system. To protect against
this condition, the LMH34400 features an integrated clamp that absorbs and diverts the excess current to the
positive supply (VDD) when the amplifier detects its nodes entering a saturated condition. The integrated clamp
minimizes the pulse extension to less than a few nanoseconds for input pulses up to 100 mA. When the amplifier
is in low-power mode, the clamp circuitry is still active, thereby protecting the TIA input.
7.3.2 ESD Protection
All LMH34400 IO pins excluding (VDD and GND) have an internal electrostatic discharge (ESD) protection diode
to the positive and negative supply rails to protect the amplifier from ESD events.
7.3.3 Single-Ended Output Stage
The output stage of the LMH34400 has a 10-Ω series resistor on its output to isolate the amplifier output stage
transistors from the package bond-wire inductance and printed circuit board (PCB) capacitance. The net gain of
the LMH34400 (TIA + output stage) is 40 kΩ when driving an external 100-Ω resistor. When the external load
resistor is increased above 100 Ω, the effective gain from the IN pin to the output pin increases. Consequently,
when the external load resistor is decreased to less than 100 Ω, the effective gain from the IN pin to the output
pin decreases as a result of the larger voltage drop across the internal 10-Ω resistor. When there is no load
resistor connected to the output pin, the effective TIA gain is 44 kΩ. The output voltage of the LMH34400 is set
to a fixed value of 1.0 V when there is no current flowing into the amplifier. The output swings above and below
1.0 V when the photodiode sinks and sources current, respectively.
7.4 Device Functional Modes
7.4.1 Ambient Light Cancellation Mode
The LMH34400 has an integrated DC cancellation loop that can used to cancel any voltage offsets resulting
from ambient light. The DC cancellation loop is enabled by setting IDC_EN low. Incident ambient light on a
photodiode produces a DC current resulting in an offset voltage at the output of the TIA stage. If the photodiode
produces a DC output current resulting from ambient light, then the output of the level-shift buffer stage is offset
from the reference voltage VREF. The ALC loop detects this offset and produces an opposing DC current to
compensate for the differential offset voltage at its input. The loop has a high-pass cutoff frequency of 400 kHz.
The ambient light cancellation loop is disabled when the amplifier is placed in low-power mode.
The shot noise current introduced by the DC cancellation loop increases the overall amplifier noise. So, if the
ambient light level is negligible, then disable the loop to improve SNR. The cancellation loop helps save PCB
space and system costs by eliminating the need for external AC coupling passive components. Additionally, the
extra trace inductance and PCB capacitance introduced by using external AC coupling components degrades
the LMH34400 dynamic performance.

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7.4.2 Power-Down Mode (Multiplexer Mode)

The LMH34400 can be placed in low-power mode by setting EN high, which helps in saving system power.
Enabling low-power mode puts the outputs of the internal amplifiers in the LMH34400 in a high-impedance state.
Figure 7-1 shows how this device feature can further save board space and cost by eliminating the need for a
discrete high-speed multiplexer, if a system consists of several photodiode and amplifier channels multiplexed to
single time-of-flight detector circuit. The disabled channel outputs are not an ideal open circuit so as the number
of multiplexed channels increases, the disabled channels begin to load the enabled channel. An additional
isolation resistor can help reduce the impact of reflections from disabled channels. Multiplexing more than four
channels in parallel will degrade the performance of the enabled channel.
When the amplifier is in its low-power mode, the clamp circuitry is still active thereby protecting the TIA input.
The ambient light cancellation loop is disabled when the amplifier is placed in power-down mode. When the
LMH34400 device is brought out of power-down operation, the ambient light cancellation loop requires several
time constants to settle. The time constant is based on the 400-kHz cutoff frequency of the loop.
EN = 3.3 V

DISABLED AMPLIFIER
100-mA
Clamp
12.2 k
IN

10  RISO
TIA 3.6x

VBIAS Ambient Light

Cancellation

+ TDC
or
– FPGA
EN = 0V TLV3801

100-mA
ENABLED AMPLIFER VREF

Clamp
12.2 k
IN

10  RISO
TIA 3.6x

 VBIAS Ambient Light

Cancellation

Figure 7-1. Configuring Two LMH34400 Devices in Multiplexer Mode

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

The high gain and single-ended output of the LMH34400 is well suited to be used in connection with a time-to-
digital converter (TDC) for a time-of-flight (ToF) based receiver in a LIDAR system. The TDC function can be
implemented using a stand-alone TDC or using a FPGA. ToF receive circuits that use TDC are significantly
less expensive and consume considerably less power when compared to an Analog-to-Digital Converter (ADC)
based solution. The output of the LMH34400 presents an analog representation of the returned light pulse. It
is common practice to use a time-discriminator circuit before the TDC to precisely use a deterministic part of
the returned waveform to stop the TDC. The most straightforward method to accomplish this action is called
leading-edge discrimination. This method uses a high-speed comparator with a low propagation delay to stop the
TDC when the waveform crosses a chosen incoming light amplitude value.
In many applications, the amplitude of the returned pulse can vary considerably due to the difference in target
reflectivity or simply the light source spreading out to a target moving to longer distances. For this reason, it is it
is also important to choose a compartor with low dispersion. If the dispersion is high, then the amplitude variation
in the returned signal will be converted to a variation in the timing signal presented to the TDC. This behavior
is known as a walk error. Figure 8-1 shows the LMH34400 connected to the TLV3801 high speed comparator.
In this configuration, an incoming optical pulse will source current out of the amplifier’s input pin and deliver a
proportional voltage pulse to the comparator input. As the amplifier’s output has 1.0 V DC with no input current,
the reference voltage of the comparator should be set to a level above 1.0 V. For example, if the desire is to
have the comparator to change states when the input rises above 10 μA of current, then the VREF voltage should
be set to 1.0 V + (40 kΩ ×10 μA) = 1.4 V.
VDD EN

100-mA
Clamp
12.2 k
IN

10  OUT
TIA 3.6x + TDC
or
– FPGA

VBIAS Ambient Light TLV3801
Cancellation

VREF

GND

Figure 8-1. LMH34400 to Interface to Comparator and TDC

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8.2 Typical Application

Figure 8-2 shows the circuit used to test the LMH34400 with a voltage source.
VDD EN

100-mA
Clamp
50  4 k 12.2 k

10 OUT 50  50 
TIA 3.6x Instrument

CPD
1 μF

Ambient Light
50

Source Bias-T Cancellation

1 μF

+
VBIAS –

GND

Figure 8-2. LMH34400 Test Circuit

8.2.1 Design Requirements

The objective is to design a low-noise, wideband output transimpedance amplifier. The design requirements are
as follows:
• Amplifier supply voltage: 3.3 V
• Transimpedance gain: 40 kΩ
• Photodiode capacitance: CPD = 1 pF
• Target bandwidth: 240 MHz
• Integrated input-referred noise: 50 nARMS (noise bandwidth = 250 MHz)
8.2.2 Detailed Design Procedure
Figure 8-2 shows the LMH34400 test circuit used to evaluate various bandwidth without using an optical input
signal. The voltage source is DC biased close to the input bias voltage of the LMH34400 (approximately 2.5 V).
The LMH34400 internal design is optimized to only source current out of the input pin (pin 1). When testing the
LMH34400 with a network analyzer or other AC source, the DC bias should be controlled such that the sum of
the input AC and DC components does not result in a sourcing current into the amplifier input.
In the configuration shown in Figure 8-2, there is a 50 Ω series resistor that helps with any reflection into
the observing instrument. The instrument could be any 50 Ω impedance input device such as vector network
analyzer (VNA) or oscilloscope. This setup creates a voltage divider on the output and reduces the TIA's
amplitude by a factor of two. This factor must be considered when interpreting the measured results.
The bandwidth of a transimpedance amplifier strongly depends on the capacitance of the photodiode (CPD) that
is connected to the input pin of the amplifier. The larger the capacitance, the lower the closed loop bandwidth.
Figure 8-3 shows when the CPD connected to the LMH34400 is between 0 pF – 10 pF.
While bandwidth is inversely proportional to the photodiode capacitance, the input-referred current noise and
photodiode capacitance are directly proportional. To measure the output noise, the same circuit in Figure 8-2 can
be used with a simple modification. In this case, all components on the input pin should be removed except CPD.
Figure 8-4 shows the impact of the input-referred noise density as the CPD is varied from 0 pF to 10 pF. As the
capacitance increases, the amplitude and breadth of the high frequency noise increases significantly.
Figure 8-5 shows the impact of an increasing photodiode capacitance on these two parameters in one
plot. In this plot, the integrated input-referred noise is calcuated over a fixed range of DC to 250 MHz.
Both the small-signal bandwidth and integrated input-referred noise trend toward poorer performance as the
capacitance increases. For the highest level of performance, the photodiode capacitance should be minimized.

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As the photodiode capacitance is proportional to its light capturing area, the optimum value chosen will be a
compromise of several system variables and will differ between applications.
8.2.3 Application Curves

95 10

92
Transimpedance Gain (dB)

Input Noise (pA/Hz)

89

86

83 CIN = PCB Only CPD = none

CIN = 0.5 pF
CPD = 0.5 pF
CIN = 1.0 pF
CPD = 1 pF
80 CIN = 2.2 pF
CPD = 2 pF
CIN = 4.7 pF
CIN = 10 pF
CPD = 4.7 pF
77 CPD = 10 pF
1M 10M 100M 1G 1
Frequency (Hz) 10k 100k 1M 10M 100M 1G
Frequency (Hz)
Figure 8-3. Small-Signal Response vs Input
Figure 8-4. Input Noise Density vs Input
Capacitance
Capacitance
300 165
Bandwidth

Integrated Input-Referred Noise (nARMS)

280 Noise (DC to 250 MHz) 150
Small-Signal Bandwidth (MHz)

260 135

240 120

220 105

200 90

180 75

160 60

140 45

120 30
0 1 2 3 4 5 6 7 8 9 10
Photodiode Capacitance (pF)

Figure 8-5. Bandwidth and Noise vs Input Capacitance

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8.3 Typical Application

A common application for the LMH34400 is as a transimpedance front-end driving a comparator, which can
then connect to a time-to-digital converter to calculate distances from pulse-based time-of-flight measurements.
Figure 8-6 shows the test circuit with a Hamamatsu™ GN8195-12 photodiode input connected to the LMH34400,
which is then driving TI’s TLV3601 comparator.

TLV3601

G8195
Optical Pulse Oscilloscope
Generator
LMH34400
-12 V Vref = 1.65 V

Figure 8-6. LMH34400 Signal Chain With Comparator

8.3.1 Design Requirements

The objective is to design a transimpedance front-end that can receive a 10 ns wide pulse, amplify the pulse
through the LMH34400, and then drive the output through a comparator. The design requirements are as
follows:
• Supply voltage 3.3 V
• Photodiode capacitance 1 pF
• Pulse width 10 ns
• Input current pulse edge rate 1 ns
• Input peak current 25 µA
8.3.2 Detailed Design Procedure
The circuit in Figure 8-6 shows a photodiode anode connected to the LMH34400 which is followed by a
comparator. To create the 10 ns, 25 µA input current pulses, the GN8195 photodiode is chosen because it
provides low input capacitance with minimal biasing requirements and allows for easy optical coupling through
fiber. Given the 40 kΩ gain from the LMH34400, the expected output voltage with 25 µA input current would be a
1 V peak signal. With input pulse edge rates of 1 ns, it was expected that the LMH34400 would produce slower
pulse edges because the input slew rate is higher than the capabilities of the device. To increase the edge rates
of the LMH34400 output signal, the TLV3601 comparator is added after the LMH34400 because it has a rise and
fall time of 750 ps.
For a simple time-of-flight application, the output of the comparator could be connected to a time-to-digital
converter (TDC) to perform a simple distance calculation. Using this method, the distance is calculated by
measuring the time between outgoing and incoming pulse edges and multiplying by two. In the signal chain,
the LMH34400 provides the initial signal amplification and conversion to a voltage, then the TLV3601 further
increases the output amplitude as well as provides a clean, fast edge to a following time-to-digital converter.
In the circuit design, the interface between the LMH34400 and the TLV3601 does not require any additional
biasing or level shifting, because the LMH34400 default output bias interfaces easily with the comparator.
Additionally, this 1 V bias level allows for a setting the threshold voltage of half the supply voltage which keeps
it close to the center of the comparator’s bias range as possible. However, this threshold can be set at any
value above 1 V to adjust for the application’s dynamic range requirements. In this realization, the output of
the TLV3601 was connected to a 50 Ω series output resistance to properly interface with 50 Ω terminated test
equipment.

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8.3.3 Application Curves

Figure 8-7 through Figure 8-9 show the control signal input, LMH34400 output, and TLV3601 output,
respectively, with a 10 ns wide, 1 ns edge rate input current pulse. The figures show the ability of the LMH34400
to convert a small 25 µA input signal to a 1-V output and then use the TLV3601 to increase the edge rate and
amplitude of the received pulse. Also, the shape of this output pulse stays approximately constant over a large
range of optical input power levels. In this specific case, note the output swing of the TLV3601 is limited because
it is driving a matched 100 Ω load to interface with the test equipment.

30 2.2
27
2
24
Equivalent Input Current (uA)

21 1.8

LMH3400 Output (V)

18 1.6
15
1.4
12
9 1.2

6 1
3
0.8
0
-3 0.6
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
Time (ns) Time (ns)

Figure 8-7. Equivalent Input Current Signal to Figure 8-8. LMH34400 Output Voltage
LMH34400
2.5
2.25
2
1.75
TLV3601 Output (V)

1.5
1.25
1
0.75
0.5
0.25
0
-0.25
0 5 10 15 20 25 30 35 40 45 50
Time (ns)

Figure 8-9. TLV3601 Output Voltage Driving 100 Ω Load

8.4 Power Supply Recommendations

The LMH34400 operates on a single 3.3-V power supply. As a low power-supply source impedance must be
maintained across frequency, use multiple bypass capacitors in parallel. Place the bypass capacitors as close
to the supply pin as possible and place the smallest capacitor on the same side of the PCB as the LMH34400.
Preferably, the larger valued bypass capacitors should be places on the same side of the PCB as well. However,
the capacitors can be positioned on the opposite side of the PCB using multiple vias if layout space is overly
constrained.

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8.5 Layout
8.5.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the LMH34400 requires careful
attention to board layout parasitics and external component types. Recommendations that optimize performance
include:
• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output pins can cause instability whereas parasitic capacitance on the input pin reduces the amplifier
bandwidth. To reduce unwanted capacitance, cut out the power and ground traces under the signal input
and output pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
• Minimize the distance from the power-supply pins to high-frequency bypass capacitors. Use high
quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times
greater than the amplifiers maximum power supplies. Place the smallest value capacitors on the same side
as the DUT. If possible, use low equivalent series impedance capacitors to further reduce the parasitic
impedance. If space constraints force the larger value bypass capacitors to be placed on the opposite side
of the PCB, then use multiple vias on the supply and ground side of the capacitors. This configuration
ensures that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain
bandwidth specification. Avoid narrow power and ground traces to minimize inductance between the pins
and the decoupling capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower
frequency must be used on the supply pins. Place these decoupling capacitors further from the device.
8.5.2 Layout Example

Optional isolation resistor to

Remove GND and power plane dampen resonance due to bond
between IN and APD to minimize wire inductances and component
parasitic capacitance capacitances.

IN IDC_EN

1 6

− VBIAS
VDD GND
Route ground plane as
close as possible to GND
2 5
pin with multiple VIAs to
reduce inductance.

EN OUT

3 4

Place multiple bypass capacitors in low

ESR packages close to VDD pin as
possible. Use multiple VIAs to connect to Remove GND and power plane
power plane. near output pin to minimize
parasitic PCB capacitance.
Optional isolation resistor can be
used to further isolate parasitics.

Figure 8-10. Layout Recommendation

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9 Device and Documentation Support

9.1 Device Support
9.1.1 Development Support
• Texas Instruments, LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
design guide
• Texas Instruments, LIDAR Pulsed Time of Flight Reference Design design guide
• Texas Instruments, Optical Front-End System Reference Design design guide
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, LMH34400DRL Evaluation Module user's guide
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers – Part 1 blog
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers – Part 2 blog
• Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits
• Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow
• Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
Hamamatsu™ is a trademark of Hamamatsu Photonics K.K.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 3-Feb-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LMH34400IDRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1M5 Samples

XLMH34400IDRLR ACTIVE SOT-5X3 DRL 6 4000 TBD Call TI Call TI -40 to 125 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 3-Feb-2023

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Feb-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH34400IDRLR SOT-5X3 DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Feb-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH34400IDRLR SOT-5X3 DRL 6 4000 202.0 201.0 28.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DRL0006A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
6

4X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 6X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
6X 0.05 C
0.08 SYMM

SYMM

0.27
6X
0.15
0.1 C A B
0.4
6X 0.05
0.2
4223266/C 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4223266/C 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0006A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

6X (0.67)
SYMM
1

6X (0.3) 6

SYMM

4X (0.5)

4
3

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4223266/C 12/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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