Module-

X Registeas
A colleeiion cl lip-flops in cascade is called a 1eq7ste
Shif t
Rcqisiens a e used to sioe daiain a digiial system
siored
Tegisde2S ae capable_of mavinq 0Shiiiing the olata
inAhei7 flip-flops ineither direcdioo Shidt cgisieas which
canshiHL dala in büBh directions are_calledbi-dizectional
dada in anly dizecdion ae
while those_whichc a n shidt ane

heir shilj
called
called unidivediona Shift egistens are classikied by
disecdion capabiittes We have Serial in -seridl outSerial in
pardllel ouE_parallel to -5eridloud 2 para llel in -parallel out
egisters

*SeialLin, sezial-out uni directional shikt 3cgistey Sertal

data ouAt
Sial
D D
dado in 0
clock

Saial-ioseaial-out unidinectianal shift eqi siey constuctea

out put of
Hiom positive-edge-Higqened D fhp-ilops. The
d

each fip-4lop_is Lonnecded to he D iaput o4 the 4ip

flop to its iqht The condzol inpuis of all Ahe flip-4lops_
are cOnnecde d togeihey to a tomman_synchronizinqsignal
called the clock, Thus upon the OccuTIence of a _po siiive edge
o the clock signa the _cont end of each tp-flop is shiited
One poSidion do 4he ight The_conent of the leftnmost
value
lip-lo p_aiteyHht_cloc signa_depends upon he stgna
O
On theseial-ddta-inl i a e the_content of the 9ht
oktpdL
p-+lp_ pyio7 Ho the clock signal is los4The
htmast fipflop
Yom 4he shift 2egistey occurs ot t h e g
OA the_seial-datd-0ut ine-
 TAHhnidial (onten o Ahe fouy
Ap-lops is loll La logic 'o is applied +o he Seial-
dada-in line hen conitni o he 2eqi stey bt (omes
olol
The loqic 0 became available as an oupu
on he seaial - dad
Ou tinne adder Aour clock_pulses Jn someapphLalionsàhe
ndomoadioo uiAhio a cgistey mus be _pY
thr
est)ved.4hen efoe
seial -daBa- Ou line is conn ecAdt o dhe senial- data-io line

*Serial-in_paallel-out unidizecdional
ParalleloutT
shift zcgis ter
Seaial
dada fn o D D
clocK_ C
C

The seial -in parallel .out unidredioma shidt egist ev

isshowD The oudpud 0Ye movi dedl irom
each lip-4lo pp
Once ioiox matioo is shided .inho dhe
çqist ey ie senial in
4he indo1matioo is avai lable as a
sinqle entity ie
paalle
outaAhe {lplop_oudpud Aominals since
Hanste red iodo his eaisien inionmadiaa i
Seiially 4 adter an app0piate
number o shiKLS. made availahle in
parallel this Ay pe of
reqishe movides do 4he seaial-to -pavallel
conversion ad iofomation
Parallel-inunidinecdiona shift zegisey 0
hed Paallcl-in-Seial
outlpovallel-out shidt egister
The openadioo oi the registez
oe. h.en Lo41C0 Siqnal appear
is_(ont2olled by shiH|laaa
so0 Ahis iaethe Signal
Jhe natallel-daia-in ines P. D.D
Po are Aransdered init
he OltuYEne
the 19i Ster_up.an a posixe-edae clock sigr
 Theo when a logic1 sinal appea? s
O dhe shidt Load tiae the D lp-lopsbetome a cascada
Connecdinn thad Aunctions as a unidinecdional shft regiulea
poViding Ahe seial oudpuA.In this way the aegisde
provides0Y the parallel-to-senial conv ersioo of ioio zmadion
B Hakinq the oudpuds drom dhe individual Alip-Alaps
Aheyegistey iunctions asd pardllel-iopaallel -oui
unidiiecdional shidiegister The aeaishe can also dunttion
asaseial-in parallel-oui unidiecdiona shidd zegisten 4
CS C Senial-insenial-aut undiaediomad shidt egisde
* Oniversal Shidt xeqistez oz Bidizectiona shift regBsier
Universal shidt neqisteY depends upon Hhe sianal values
On the Selec lines odhe mulLiplexers e the madt (ont20
ineshe 1egister _can 4eedta 1edain Hs (uIet stade shrdt
ightshidt leit o7 be loaded io _parallel Each o these aperali
ons is dhe nesult oi he _occu7ence_o a positive edgt a0
he clok tine_Ia addidion4he registe is dlecared asynchr0 nouly
a logic-o is applied o the line labeled cLE AR
AccOrcln9 othe dable_he regisdey petormsh e
Shiit-ight oprnali09 uuheo dhf lagit Naluu ao Ahe _Seleca_
ines S S, o dhe multiplezs_ai o1 Uadei dhi s condiiion
Hhe T iopui oi each multiplexev is Lonne pded to iHs foutpu4
The inpud do Ahe ledt mosi D Aip-{lop is the signal_00 Ahe scial
inpu f07 shiiiighi liae the iapud to ihe second le mosd D
lp-4lop is the oudput of he leimasd D flp -4lap the iopu
4ohehiad ltiA mosd D AWp Alop is dhe Outpud_o4 the second
tehmosd D Alp-4 lop 4 Ahe inpu o 4he ipes foundh leddmos
D D-Alop is Ahe ouipud oi dhe hird ledtmosd D4p4lop. Upon
he ocunne oahe posiixe_edge signal on the clock lint.dhe
hts s ca0i end onE posidion to he zight. Theemaining
P0 sHe7 operaions vevHied in a similar manne
 Paxalleloutpurts
A Qc

9 -

CLROP CLR SP CLRP

CLRP
CLEAR
Clock

4-to-1 4 -to-1
Mode 4-101 4-to-1
MUX MUX S MUX
Control MUX
T
Serial input
Serial input
for shift
foTshifL
Tight (5TR)
left(S11)
T
Panllel inpurts

Select lines Register operation

So
Hold
Shitt right
O Shidt le4 t
Parallel load
Xx Cuntezs
A cOunter is a cascade of 4ip-flopsTAS_primany
Aunclioo is io pmocluce_a specified culput padiern sequence
Fo his rason is also called padiezn genenatoz

Binaxy Ripple Countez

T
Count
pulses C
Qb-

0 0 0 0
0 0 0 1
0
0 1
Q2 0 1 0 0
0
0 1 1

0 0 0

0
1
0 1
ep
Count enable 0 0 0 0
etc.
(a)
(c)
Count
pulses

LUTTLUUUUUTULUN
UL

T:..
Tme
(b)
Figure 6.31 Four-bit binary ripple
counter. (a) Logic
(c) Counting sequence diagram. (b) Timing diagram.
 Ho tha o
whose cOuningseguence coiesponds
Cownters
LOunier5. The modulus
n u m b e r s a r e called binary
the bioary number _oi flip -dlops
is2wheze_nisdhe
O a binany tauntez is implemended with
-c0undeY
tour-bid binary up
inthe Laund er A7ansiion
e
-4lop. Each posiHive
positive edge trigoezed T 4lp ccauses dhe 4lip
om logic0 to logic1L
on the C Eeminal
lop to ogale to each fKp-lop
is input
the
lhecouot tnable signdl flop change
is logic-1 the , ilip
wheo count enable signal
edge od a count pulse, The L0ntYol input
Sdade on each posidive comected du tht Oud put
le c o f the vemaininq itp-Alops s
o i t spevious-0rder flip-Alop
is assumeol to be iotially in its Ooo0 siate
he Louater
enablc siqnal is logic-1 Upan the occunrence of the
4the Count changes to_
posidive edge adHhe firstCount Dulse the ,4tp-4lop
Output ierminal gaes 1om logici do logic-o
ids1-state.Since G
nat afected by ihe input pulse The state of
Hhe lip-flop Q,is coun t
is aow O0ol when the p0Sitive edge of the
the (ountey
+he Q, ilip-{lop is again toggled. This time it
pulse ariyes, Ho
0-stateSince d, outpui goes fom logïc.o
edurns Ho its
ecge occUTs at the (onirol inpud of the
ogic-1 a positive
p4causes i to toggle lhe chang in state o the G_
4ip-flo
not affect Hhe Q, {lip -flop_Since a negadiveedg
p-lop does is oolo
Now the state of the Lountez
Octus at ids coatrol input.
countpulse ccugS only Ahe Q, Alip-Alap do change
Ihe third posidive edge of
coun to become ooll, when the
Statethe
Ap-flop eBusns do iis 0-sate
HheHourih pulse _occuYSthe G. termina
positive edge to OCcuy dt the G,_
hiS_Causes a
ids 0-siate I o
i t o g g l e d e d u n i a g id to
Thus 4p-4lop
p-flop chanqes
ids siadethe 9,lip.
addtion when dhe
 Tug o.
lop is t0ggled by dhe logi.c-0 do logic-1 Dale
Hransii on appeainq a thc -Oudpuli
terminalThe countey
nou stores +he hinagy numbey
0100. The binay oundinq
Sequeace cominueS uoiil the count l ' s 1eached, Ths
A that 4imea count pulse (aus es
dhe {p-flop to veiun
o is 0-state This i0 tua, ccuses
he 4li p -4lop do_
edun 4o ids 0-stateA Conseguence o this
ch ange tauses_
the ip-4lop to 7ehuno to ids 0-sAate
4Ainally Hhi s
Change redUTaS the QAp-4lop do its0-state. Thus
ht
SAate o the LOunteY bt(omts 0000I
Urth ey_ Count
pulsesaT applied to Ahe cauoter.then it epea4s itS
LCoundiaq SeOtn ce

*Synchronaus Binazy Counters

Count
enable - o

EDHT C

Count pulses

Figure 6.32 Four-bit synchronous binary counter.

 Fo Synch onousCOuniers,
4he (ount pulse s
contol iopuds ,C, of all 4h locred
ae applied direcdly 4o he
Ahe flip 4 lops o change simul lancouwly
lp-ftops This causes a420all
cssociaied wdh a single 4lip-flop
aier the propogalion delay
As lonq as -Jhe (ounie is enabled, i.C the CCun-enable
binary counding
follows he
Siqnal is logic 1,4he (ound e
s29uence lo pedicular the lowesi- 0vder i p - flop G 4094le
Ondhe posidive edge cf each dock pulse The and-gad preceding
e

each T iopud teamioal ol the emaining p-lops detecis

14 all

Ti 4bis
4he louwey -0ide lip- lops_ave in thei 1 sdades
LOndidioo sadisieSthen dhe fip-4lop i09gles upon the
OCCUTTence

theposidive edqe o 4he count puls, Since he Ccunt pulse

s

incunned
re applied d'nectly Ao each Altp-Alop the only delay
bed he_applicadioa a count gulse & the availabili4 o he nte
Lount oudpud i sthe pyapoqadion_delay fime of a Alip Alop
Counters Based on Shift registers
The couoters based on dhc siudure of Ahe shiit eqiste

are inq Louner A inq counier Shift 7egisieyis a ioular

which isinidialized so tha only one_cf ids flip-ilopsis the

io

Staewhile Ahe otbe1s are iodheiy 0-Staes Then upon the

occumence of e cch(ouot_pulse_the single IisShidtedt o

HS adiactat fip -{lops_ The below diqure shows mod-4 7inq
COuniey I i s assumed dhad he counter is initialized ta
HS GAG 9 Gp looo sBade

Qc OD

Count
D 10 0 0
01 0 0
pulses 0 0 0
0 0 0 1
10 0 0
etc.
(a) (b)
Figure 6.37 Mod-4 ring counter. (a) Logic diagram. (b) Counting sequence.

AHhaughAhe inq coundes is nod efficied in thenumbcy

o lp 4laps used proxides a decoded cuttput Thatis do detecd
any pedicular siaie in dhe cOundinq Sequence ii is only necessar y
Hoiadenoqale Ahe cutpui ci aSingle Alp-lop
A variadion o he ing counde isthe Swiich Aail caunte?,
also kocwn as dhe duisied-ing counie ov Johnson (ouoter
Assume the cOunter sdarls in the 0000 sdate o this ounder
40
he Dmpltmeni of the iohim0st flip-{lop senves_as Ahe iopud
he leftmusi liplop ia the shift-ghl negiser configunaion
 n Oc p
0 0
L0 0 0
ec 1 10. 0

D 1
Count C 0 0 1 1
>C
pulses
ep 00 0 0
etc.

(b)
(a)
sequence.
Figure 6.38 Mod-8 twisted-ring counter. (a) Logic diagram. (6) Counting

above tudune aluoyr

A twisted-iing caumer having the
basan eveo numbe s t a t e s io iHs Couning
Seguence A_
having an cdd numbey od Siades is shown
Huisded-ing couoter
hom the
below. The stadeconsistinqo all 's iseliminated
counting se2uence. This is achieved by connecding 9p do he
npu oi Ahe leitmas D fip-floP
And-gate
inputs

Qc 00 90
1 0
0
QpQc
D
QceD
D
Count
C C C 0 01 Qplc
pulses QceD
0 0 0 0
etc.

(a) (b)

Figure 6.39 Mod-7 twisted-ring counter. (a) Logic diagram. (b) Counting sequence.

*Flip-Flop Exitadion Tables

S-Rflip-4lop
R
O

O 1
 KAip-flcp
00 X
X

*D Aip-Alap
D

TAp-4lop

*Desion oia
Synchyonous counters
Destgn o a
Synchronous Mod-6 counte
using clocKed JK
SHep 1 Number
d Atp-ilops
Fip-lops acguio ed tguioeddo build 4he tounde
Here N: Gac22>N
0c2' N
2 ,6
.e thee fip-lops 0:3E
ae
coui ed
stcp2 ExiHatton 4able dor JK 4lip 4lop

XO

Sep3 Thansi4ioo 4able.

esent staBe Next state Flip-lop inputs

X
X
O X
X X

X x
xX X
X

Step R-map simplificalion foz fip-4 lop topuds

Fo JA Fo RA

9A000 1 10 o 1 10
O
xX
For Ja Fo Kp
A00 ol 10
o X|x o
0xx

fo Oc Fo K
O0oLI10 g00_ol 10
Xx
XXX

5tep . mplemem thecoumer

S c
BA

clock
Design_oi a Synchronous Mod-6 oLunie
Usingclocked D-{lip-flopP

SHep1 Numbey of {tp-4lops_1eguired :2

6
2 6
:3 e dhee lip-4lops ae cquined.

sAep2 ExGHadion able forD-4lip-flop

g D
O

Step3 T7an sition Aable

Present sdate Next sdade Flp-4lop inpuls

DA D8 De
A 8
0 0 o
0

O
O

StepK-map simplicadiaoio flip-4lop iopuAS-

 For DA Foy De
O0 00 0

DA A gc

Fov Dc

Gn000 l0
D O

Step 5 mplemen the counder

clocK

* Design of a Synchronous Mod-6 Counder ustng

clacKed
Ilip-ilop
SAeP1 Numbey o fip-{lops equre o
N
26
n 3 i cthvee 4lip floPS are eguird
 Siep 2 Eiiation Hable tc T.ftp-{lop

Step3 Tansition Acble

Present staie Nex Stat e Fp-{lops iopuHS

A B SA TA TB T
O o

1 0
o
O

X X X

Sep4 R-map simplificadioo dor fi 4lop inpuds

For tA Fo7 TB

A 00 0 I lo 00 o 10
oo Do
xX

ForcG T1
 step5Smplemeo dhe (oumder

A- 0gict

TA A

clocK

Design ofa Synchvonous Mod-6 (Oune Using clocked

SR Ap-{lop
step1: 2 Number of Plip-flops nequised
2 N
N 6 2°, 6.
3Le thee flip flops are regui red

Step 2 Exidadicg Hable

asR
oo o
o

x |o
Step 3 I7ansition 4able

Presen state Neat sAade Fip-4lop inpuS

A S9 SARa Sa RsSe
0 0 0 0A10
0 0 o 0 X

x c
9Aa SA RA SRaSR
O X
X
X X X X X XX

Hep K-map simplicadico foz flp-flops

For Sa Foy A

O0 0l 00 0 10
o0To ox Xo x
X oX|X|
SA g c RA 9
Fo SB Fo7 K
A oo o 1 10
oOC|o X OX
x
Re s c

Foy Sc Fo Re
B
OO
Do

Step 5 Jmplement the (ountey ,

G6 SB

clocK
 R a c e _ a o u n d _ ( o n d i i o n

fhen the
Io a JK laBch_when J 4R are both high
toggles_(oiinuouslyThis
condidiaa is cclled_a ace

oudput hal{ ycle_of

COndiionDue to Hhiso
the posidive
daunc
J4K bodh aze high, jhen
the
Enable),IL
_pulse
Hhe_clock
Cpuogglescondinuodsty
race arcund eondidion . an ed9e trigqeztd
To avoid
liplop is_(2eated. In this fRp -4lop
oY pulse triggened Jk edge o a neqatire
changes only dd dhe pasidive
he oudpud
edge ad dhe cloct
EN

J-

Propagation delay

Fig. 5.17 Input and output waveforms for

clocked JK flip-flop

sequential_cirruits
*Comparison between combinaitonal&

Combina1ional circuits Sequeniial ciauits

To sequendial_cizuils+he
To combinadiona ciruits, the
Outpud variables_dependent no
cutput vaTiables are at all 4imes
dependen co he combinadion of only_an the present input
inpui vaTiables Vaviables_bui they _also_depend
upon +he past his tory oB dhese
inpu variables

2Memo7y unit iS nat reguired 22Memoy unit is veguized t0.

in(Ombinationas iruits store the_past history of input
Vaabl S_jo
the_segueniial
Circuit
 3 (ombinational dcits are 4aster32
Seguendial cinuits ae
in speed because the clelay betucen slowey than the combinaticna
inpu ouipuis due_to ciuits
propcqaticodelay o gales
4 Tis casy to design 4 I t is ccmparatively hazdez
to design
5 Panallel_adde isa Combinational 5 Serial addez is a sequential
CITCuiL Cizuit

Camparison between Synchronous asynchronous seguen tial

cixcuits
Synchronous segueniialdruit Asynchxous segutntial circuit
I o synchxoncus cintuitmemozy In asynchonous iruits,mtmory
eltmentsare docked Alip-{lops elemeaic e either _unclacked
ip-flops 07 time delay elemends
22 Jn synchronous iruiis. the 2 Ta asynchronous ciouits change
change ia ioput signals_can i oopud sionals can aliecd
adfecd mtmor y element upon mtmoy eltmeni ad any iostant
ackivadion_of clock signal of 4ime
3 The mazimum optratinqspeed Becuse ad absence_oi clock
f clock depends _oo 4ime csynchxonous druits coan
delay s involved. opezate astey than synchronou
dyuits
42 Easier to deSign More d?lticult to design
Design a synchronous countey +0 Seguence
0 467 50 using posidive edge tiggend
JKp Alops uidh minicna ombinaiona gading
Thtre a1e sil_distinc sHate htnte i s o mod-6
COuote whith e9 uinesthTee Jk Alip-Alop
SHohe diagYam
o0
(1o
Exialion 4abe
Cell Preser siateNext state Flip flop inpus
No.g, X
0
X X
XX X X
2 X X
XXX
3 X XOX
X
X
5
6
7
 For J2 FOr K
,9,9
00 ol lt lo
xX x
x X XX

For U For K

00 0
ox x13
x i|o
K:SS
For Jo
For Ko

00o 10 00 0l_

K
JmplemeHation
 Design a synchr0nous cauotey o s9uence
024 2 6 0 uinq posidivc edge igcred S p 40ps
sol Thtre are fixe distinci states hence thite Alip-4lops
aye ne9ired.
000
(Tto (l00)

Enilation Hable
Cellno eseni sdad e Ne SdadeFip-ilop iauds

00X
2 X 0 X
3 0 X_X XX XX
00 0
XX_X

6 O 0 0 O X
7 XA x XX X

R-maps
Fo7

ox
S4,
FoyL fo R
O0 ol,110 , a0 oL 1,

R,
For Ro

ox1x

Implememation

UL So