Unit-V HARDWARE DESCRIPTION LANGUAGE

Two Marks

1. Define HDL.
A hardware description language(HDL) describes the hardware of digital system
in a textual form. It is used to represent logic diagrams, Boolean expression and
other digital circuits.

2. What is meant by simulation?

It is the representation of the structure and behavior of a digital logic system
through the use of a computer.
A simulator interprets the HDL description and produce readable output such as a
timing diagram, that predicts how the hardware will behave before it is fabricated.
Simulation allows the detection of functional errors in a design without having to
physically create the circuit.

3. Give the format of module in Verilog.

The Module is the building block in Verilog. It is declared by the keyword and is
always terminated by the keyword endmodule.

4. What are the symbols used for AND,OR, and NOT gate?
& -AND operation
! – OR operation
~ - NOT operation

5. Give the types of modeling.

Gate Level Modeling
Data Level Modeling
Behavioral Level Modeling

6. Define Behavioral Modeling.

Behavioral Modeling represents digital circuits at a functional algorithmic level.
It is used to sequential circuits. There are two kinds of behavioral statements in
Verilog HDL initial and always.

7. Define Initial Statement.

An Initial Statement executes only once. It begins its execution at the start of
simulation and ends after all the statements have completed execution. It is useful
for generating input signals to simulate a design.

8. Define Always statement.

The always statement can be controlled by delays that wait for a contain time or
by certain conditions to become true to by events to occur.
The format is always @ (event control expression)
Procedural assignment statements.
9. What are the types of Procedural Assignment?
1. Blocking assignment
2. Non-blocking assignment.

10. Give the types of operator in Verilog HDL

1 .Boolean logical operators
2. Unary reduction logical operators
3. Bitwise logical operators
4. Relational operators
5. .Binary arithmetic operators
6. Unary arithmetic operators

11. Define Wire and Port.

Wire:
Wire elements are used to connect input and output ports of a module
instantiation together with some other element in your design.
Wire elements are a stateless way of connecting two pieces in a Verilog-based
design
Port:
Ports are a set of signals that act as inputs and outputs to a particular
module and are the primary way of communicating with it.
 UNIT 5

HARDWARE DESCRIPTION LANGUAGE

Introduction to Hardware Description Language (HDL):

– HDL describes the hardware of digital systems.

– This description is in textual form.

– The Boolean expressions, logic diagrams and digital circuits can be represented
using HDL.

– The HDL makes it easy to exchange the ideas between the designers.

– HDL are used to describe hardware for the purpose of simulation, modeling,
testing, design and documentation.

Applications of HDL:

Synthesis:

 In synthesis, HDL model is used as the first step to generate a physical design.

Simulation:

 In simulation, HDL model is used to study the properties of the digital circuit.

TYPES OF HDL:

 VERILOG HDL

 Verilog HDL allows a hardware designer to describe designs at a high level of

abstraction such as at the architectural or behavioral level as well as the lower
implementation levels leading to Very Large Scale Integration (VLSI) Integrated
circuits (IC) layouts and chip fabrication.

 Verilog is case sensitive (Keywords are in lower case)

 Verilog HDL is similar to C-Language

 VHDL
OPERATORS:

 Logical Operators
 Bitwise Operators
 Shift Operator
LOGICAL OPERATORS :

BITWISE OPERATORS:
SHIFT OPERATORS:

STRUCTURE OF VERILOG MODULE:

module <module name> <port list>;

<declares>

<module items>

end module

 Verilog HDL describes a digital system as a set of modules.

 Each of these modules has an interface to other modules to describe how they are
interconnected.

 Each module consists of a declaration and a body

 In the declaration, Name, Inputs and Outputs of the module are listed.

 The body shows the relationship between the inputs and the outputs.

 A module is a basic building block of Verilog HDL

MODELING TECHNIQUES:

 Gate-Level Modeling

 Dataflow Modeling

 Behavioral Modeling

A. Gate-Level Modeling

• Interconnection of simple components

• Purely Structural

B. Dataflow Modeling

• Specifies transfer of data between registers.

• Structural information is available.

C. Behavioral Modeling

• Procedural code

• Little structural detail (except module interconnect)

HDL PROGRAM

1. For the circuit diagram given below write HDL program using data flow modeling.
 Program:

2. Write the HDL program to compute Half Adder using Gate Level Modeling and Data
Flow Modeling Techniques.

Program:

GATE LEVEL MODELING:

module HA(A,B,S,C);
input A,B;
output S,C;
xor(S,A,B);
and(C,A,B);
end module
 DATA FLOW MODELING:
module HA(A,B,S,C);
input A,B;
output S,C;
assign S = A^B;
assign C =A&B;
end module

3. Write the HDL program to compute Full Adder using Gate Level Modeling and Data
Flow Modeling Techniques.

GATE LEVEL MODELING:

module FA(A,B,Cin,Sum,Cout);
input A,B;
output Sum,Cout;
wire S0,C0,C1;
xor1(S0,A,B);
xor2(Sum,S0,Cin);
and1(C0,A,B);
and2(C1,S0,Cin);
or(Cout,C1,C0);
end module
 DATA FLOW MODELING:
module FA(A,B,Cin,Sum,Cout);
input A,B;
output Sum,Cout;
wire S0,C0,C1;
assign S0= A^B;
assign Sum= S0^Cin;
assign C0=A&B;
assign C1=S0&Cin;
assign Cout=C0|C1;
end module

4. Write the HDL program to compute 2:1 MUX using Gate Level Modeling and Data Flow
Modeling Techniques.

I0
G1

G2
I1
S BAR
GATE LEVEL MODELING:
module 2:1 Mux (D1,D2,S,Y);
input D1,D2,S;
output Y;
wire S BAR, I0, I1;
not(SBAR,S);
and G1(I0,D1,S);
and G2(I1,D0,S BAR);
or (Y,I0,I1);
end module
DATA FLOW MODELING:
module 2:1 Mux (D1,D2,S,Y);
input D1,D2,S;
output Y;
wire S BAR, I0, I1;
assign SBAR = ~ S;
assign I0= D1&S;
assign I1= D0&S BAR;
assign Y=I0|I1;
end module
4:1 MUX GATE LEVEL MODELING

module Mux 4:1(S0,S1,D0,D1,D2,D3,Y);

input S0,S1,D0,D1,D2,D3;

output Y;

wire I1,I2,I3,I4,I5,I6,I7,I8;

not 1(I1,S0);

not 2(I2,S1);

and g1(I3,D0,I1,I2);

and g2(I4,D1,I1,S1);

and g3(I5,D2,S0.I2);

and g4(I6,D3,S0,S1);

or g5(I7,I3,I4);

or g6(I8,I5,I6);

or g7(Y,I7,I8);

end module

5. Write the HDL program of 1:2 Demux using Gate level Modeling and Data flow
Modeling.
 GATE LEVEL MODELING:

module 1:2 Demux (D,S,I0,I1);

input D,S;
output I0,I1 ;
wire S bar;
not(S bar,S);
and A1(I0,S bar,D);
and A2(I1,S,D);
end module

DATA FLOW MODELING:

module 1:2 Demux (D,S,I0,I1);

input D,S;
output I0,I1 ;
wire S bar;
assign S bar = ~S;
assign I0 = S bar&D;
assign I1 = S&D;
end module
6. Write the HDL program of 1:4 Demux using Gate level Modeling and Data flow
Modeling.
GATE LEVEL MODELING:

module Demux(a,s0,s1, mux_firstout, mux_secondout, mux_thirdout, mux_fourthout);

input a, s0, s1;

output mux_firstout, mux_secondout, mux_thirdout, mux_fourthout;

wire s1bar, s0bar; \\ s1 bar = s1 , s0 bar = s0

not 1(s1bar,s1);

not 2(s0bar,s0);

and 1(mux_firstout,s1bar,s0bar,a);

and 2(mux_secondout,s1bar,s0,a);

and 3(mux_thirdout,s1, s0bar,a);

and 4(mux_fourthout,s1,s0,a);

end module

DATA FLOW MODELING:

module Demux(a,s0,s1, mux_firstout, mux_secondout, mux_thirdout, mux_fourthout);

input a, s0, s1;

output mux_firstout, mux_secondout, mux_thirdout, mux_fourthout;

wire s1bar, s0bar; \\ s1 bar = s1 , s0 bar = s0

assign mux_firstout = (a & ~s1 & ~s0) ;

assign mux_secondout = (a & ~s1 & s0) ;

assign mux_thirdout = (a & s1 & ~s0) ;

assign mux_fourthout = (a & s1 & s0) ;

end module
 HDL FOR SEQUENTIAL CIRCUITS

Blocking Operator:

‘=’  Blocking assignment executes the set of sentence sequentially

Nonblocking operator:

<=  Non blocking assignment executes the set of sentence in parallel.

1. Write the HDL program of SR Flipflop using Behavioral Modeling Technique.

Symbol:

Truth Table:
 Program:

module SRFlipflop (S,R,Clock,reset,Q);

input S,R,Clock,reset;
output Q;
reg Q;
always @(posedge Clock)
begin
if (reset)
Q < = 1’b 0;
else if (S= = 0 && R = = 0)
Q < = Q;
else if (S= = 0 && R = = 1)
Q < = 1’b 0;
else
Q < = 1’b 1;
end
end module

2. Write the HDL program of D Flipflop using Behavioral Modeling Technique.

Symbol:

Truth Table:
 Program:

module Dflipflop (D,clk,reset,Q);

input D,clk,reset;

output Q;

reg Q;

always @ (posedge clk)

begin

if(reset)

Q<=1’b0; //when reset

else

Q<=D; //when clk

end

end module

3. Write the HDL program of JK Flipflop using Behavioral Modeling Technique.

Symbol:

Truth Table:
 Program:

module JKFlipflop (J,K,Clk,reset,Q);

input J,K,Clk,reset;
output Q;
reg Q;
always @(posedge Clk)
begin
if (reset)
Q < = 1’b 0; //when reset
else if (J= = 0 && K = = 0)
Q < = Q;
else if (J= = 0 && K = = 1)
Q < = 1’b 0;
else if (J= = 1 && K = = 0)
Q < = 1’b 1;
else
Q < = ~Q;
end
end module
4. Write the HDL program of T Flipflop using Behavioral Modeling Technique.

Symbol:
Truth Table:

Program:

module T flipflop (D,clk,reset,Q);

input T,clk,reset;

output Q;

reg Q;

always @ (posedge clk)

begin

if(reset)

Q < =1’b0; //when reset

else if (T)

Q < = ~Q; //when Toggle

else

Q < = Q;

end

end module
5. Write the HDL program of Synchronous Counter and Asynchronous Counter using
Behavioral Module.

Truth Table

q[1] q[0]

0 0

0 1

1 0

1 1

Program:

module sync counter (clk, reset,q);

input clk,reset;
output [0:1]q;
reg [0:1]q;
always @(posedge clk)
begin
if(reset)
q = 2’b00;
else
 q = q + 2’b01;
end
end module
--------------------------------------------------------------------------------------

Truth Table

q[1] q[0]

1 1

1 0

0 1

0 0

Program:

module sync counter (clk, reset,q);

input clk,reset;
output [0:1]q;
reg [0:1]q;
always @(negedge reset)
begin
if(reset)
 q = 2’b00;
else
q = q - 2’b01;
end
end module

6. Write the HDL program of Serial In Serial Out Shift Register using Behavioral modeling
technique.

Program:
module SISO (din,clk,reset,q,dout);
input din,clk,reset;
output dout,[3:0]q;
reg dout,[3:0]q
always@(posedge clk)
begin
if(reset)
q< = 4’b0000;
else
q[2] < = din;
q[1] < = q[2];
q[0] < = q[1];
dout < = q[0];
end
end module
7. Write the HDL program of Serial In Parallel Out Shift Register using Behavioral
modeling technique.

Program:
module SIPO (din,clk,reset,q);
input din,clk,reset;
output [3:0]q;
reg [3:0]q
always@(posedge clk)
begin
if(reset)
q< = 4’b0000;
else
q[3] < = din;
q[2] < = q[3];
q[1] < = q[2];
q[0] < = q[1];
end
end module
8. Write the HDL program of Parallel In Parallel Out Shift Register using Behavioral
modeling technique.

Program:
module PIPO (A,B,C,D,clk,reset,Q);
input A,B,C,D,clk,reset;
output [A:D]Q;
reg [A:D] Q;
always@(posedge clk)
begin
if(reset)
Q< = 4’b0000;
else
QA < = A;
QB < = B;
QC < = C;
QD < = D;
end
end module