Verilog Control Structures and Operators
1. If-Else Statement
Description: Used for conditional execution of statements. It executes one block if the condition is true, and another if it
is false.
Syntax:
if (condition)
statement1;
else
statement2;
Example:
always @(*) begin
if (a > b)
result = a;
else
result = b;
end
Explanation: If 'a' is greater than 'b', 'result' is assigned 'a'; otherwise, 'result' is 'b'.
2. Case Statement
Description: Used for multi-way branching based on the value of an expression. It's more efficient than multiple if-else
statements.
Syntax:
case (expression)
value1: statement1;
value2: statement2;
default: statement_default;
endcase
Example:
always @(*) begin
case (opcode)
4'b0000: operation = "ADD";
4'b0001: operation = "SUB";
4'b0010: operation = "MUL";
default: operation = "NOP"; // No operation
endcase
Explanation: The 'operation' is set based on the 'opcode' value.
3. Casex and Casez Statements
Casex: Treats 'x' and 'z' as don't-care conditions in the case expression and case items.
Casez: Treats only 'z' (high-impedance) bits as don't-care conditions.
Syntax:
casex (expression)
4'b1xx0: action1; // 'x' bits are don't-care
default: action_default;
endcase
casez (expression)
4'b1z00: action2; // 'z' bits are don't-care
default: action_default;
endcase
Example for Casex:
casex (input_signal)
4'b1xx1: result = 1; // Matches 1001, 1011, 1101, 1111
default: result = 0;
endcase
Example for Casez:
casez (input_signal)
4'b1z01: result = 1; // Matches 1001, 1z01, 1Z01
default: result = 0;
endcase
Explanation: 'casex' and 'casez' are used for pattern matching where some bits can be ignored.
4. For Loop
Description: Used for iterative tasks, like generating repeated structures or performing operations a fixed number of
times.
Syntax:
for (initialization; condition; increment) begin
// Statements to execute
end
Example:
always @(*) begin
for (i = 0; i < 8; i = i + 1) begin
result[i] = a[i] & b[i]; // Perform bitwise AND for each bit
end
end
Explanation: This loop performs a bitwise AND operation on each bit of two 8-bit vectors.
5. Verilog Operators
Types of Operators:
- Arithmetic Operators: +, -, *, /, % (addition, subtraction, multiplication, division, modulus)
- Logical Operators: &&, ||, ! (logical AND, OR, NOT)
- Bitwise Operators: &, |, ^, ~, ^~ or ~^ (bitwise AND, OR, XOR, NOT, XNOR)
- Relational Operators: ==, !=, <, <=, >, >= (comparison)
- Shift Operators: <<, >> (left shift, right shift)
- Reduction Operators: &, |, ^, ~&, ~|, ~^ or ^~ (reduces a vector to a single bit using bitwise operations)
- Concatenation Operator: {} (combines multiple bits or vectors into one)
- Conditional Operator: ? : (ternary operator, used for conditional assignments)
Examples:
- Arithmetic: result = a + b; // Addition
- Logical: if (a && b) out = 1;
- Bitwise: result = a & b; // Bitwise AND
- Relational: if (a == b) equal_flag = 1;
- Shift: result = a << 2; // Left shift by 2 bits
- Conditional: max = (a > b) ? a : b; // If a > b, max = a; else max = b
Explanation: Verilog operators perform various operations, from arithmetic to bitwise manipulation. The conditional
operator (? :) is useful for compact conditional expressions.
