Detailed Explanation of Verilog Code Files
File: dsd code lab 1a.txt
Module: part1_1a
Purpose: Implements an 8-bit 2-to-1 multiplexer.
Inputs: s (selection input), x and y (8-bit data inputs).
Output: m (8-bit output based on s).
Logic: If s = 0, m is taken from x; if s = 1, m is taken from y.
Module: part2_1a
Purpose: Implements a 5-input multiplexer.
Inputs: u, v, w, x, y (1-bit inputs), s (3-bit selection input).
Output: m (selected 1-bit output).
Logic: Uses an array to select the input based on s.
File: dsd code lab 1b.txt
Module: part1_1b
Purpose: Implements a 7-segment decoder for a 3-bit input.
Inputs: c (3-bit input representing a number).
Output: s (7-bit output for 7-segment display).
Logic: Uses a case statement to map c to 7-segment encoding.
Module: part2_1b
Purpose: Implements a 6-input multiplexer.
Inputs: a, b, c, d, e, f (1-bit inputs), s (3-bit selection input).
Output: m (selected 1-bit output).
Logic: Uses an array to select the input based on s.
File: lab2a dsd code.txt
Module: part1
Purpose: Main module that integrates components for 7-segment display output.
Inputs: v (4-bit binary input), b (4-bit input for comparison).
Outputs: d1 (tens digit), d0 (units digit).
Components: Includes comparator, circuitA, circuitB, genericmux, and 7-segment decoder (d0).
Module: comparator
Purpose: Compares two 4-bit numbers and outputs zout.
Module: circuitA
Purpose: Maps a 3-bit input to another 3-bit output using a case statement.
Module: circuitB
Purpose: Outputs a 7-segment display value based on a 1-bit input.
Module: genericmux
Purpose: Multiplexer to select between two 1-bit inputs.
Module: d0
Purpose: 7-segment decoder for a 4-bit input.
File: lab2b dsd code.txt
Module: lab2bmain
Purpose: Main module for arithmetic operations and 7-segment display.
Inputs: A0-A3, B0-B3 (4-bit inputs), cin (carry-in).
Outputs: disp1, disp0 (7-segment display outputs).
Components: Includes adders, comparator, circuitA, Zeddo, genericmux, and display modules.
Module: lab2b_adder
Purpose: Implements a single-bit full adder.
Logic: Sum and carry-out are calculated using XOR, AND, and OR operations.
Module: comparator
Purpose: Compares two 4-bit numbers and outputs gr.
Module: circuitA
Purpose: Generates a 4-bit output based on cout and Sin using a case statement.
Module: Zeddo
Purpose: Combines compOUT and coutlast using OR operation.
Module: genericmux
Purpose: Multiplexer that selects between two inputs.
Module: circuitB
Purpose: Outputs a 7-segment display value based on a 1-bit input.
Module: d0
Purpose: Maps a 4-bit input to a 7-segment display output.
