Course: VLSI Layout Design (21EC7E13)

Module 2
Course Instructor:
Deepthi M S
Layers used to form NMOS & PMOS
✓Active layer → to fabricate MOSFETs (in bulk or p-substrate)

✓n-select layer → dopes the semiconductor n-type

✓p-select layer → dopes the semiconductor p-type

✓Poly layer → forms the MOSFETs

✓Metal 1 layer →

Course Instructor: Mrs Deepthi M S

2
VLSI Layout Design
Active layer
✓It is the opening in the field oxide (FOX).

✓The MOSFETs are fabricated in this active area.

✓The area that is not active is called the field area.

✓The active areas are isolated by FOX.

✓FOX keeps interaction between areas minimum.

Course Instructor: Mrs Deepthi M S

3
VLSI Layout Design
Active layer

Course Instructor: Mrs Deepthi M S

4
VLSI Layout Design
N-select and P-select layers
▪ N-select or p-select layer surrounding active area → dopes the active area.
▪ n-select or p-select layers dopes the semiconductor n- or p-type.
▪ N-select/ p-select mask → larger than the active mask → avoid misalignment.
▪ If the select layer bombard FOX, the implanted atoms are prevented from reaching
substrate.

Course Instructor: Mrs Deepthi M S

5
VLSI Layout Design
N-select and P-select layers

Course Instructor: Mrs Deepthi M S

6
VLSI Layout Design
N-select and P-select layers

Course Instructor: Mrs Deepthi M S

7
VLSI Layout Design
Poly layer
• Drawing poly over active produces a MOSFET layout.
• Number of poly crossing active area → gives number of MOSFETs.

Course Instructor: Mrs Deepthi M S

8
VLSI Layout Design
Poly layer

Course Instructor: Mrs Deepthi M S

9
VLSI Layout Design
Layout of NMOS device
• Poly over active → forms
MOSFETs.
• MOSFETs has → four terminals.
• The bulk is tied to ground.
• Source and Drain of the
MOSFET are interchangeable.

Course Instructor: Mrs Deepthi M S

10
VLSI Layout Design
Layout of PMOS device
• Lay the device in n-well.
• Source and Drain of the
MOSFET are interchangeable.
• N-well tied to the highest
potential.

Course Instructor: Mrs Deepthi M S

11
VLSI Layout Design
Why multiple contacts or single contacts???

1. parasitic resistances at source and drain

must be kept as low as possible Course Instructor: Mrs Deepthi M S
12
VLSI Layout Design
Why multiple contacts or single contacts???

➢Drain and source diffusions give sheet resistance.

➢Many contacts make surface of metal connections smoother than when using only
one contact.
✓microcracks in the metal that can be a source of failure.
➢ avoid parasitic transversal drop voltages
Course Instructor: Mrs Deepthi M S
13
VLSI Layout Design
Why multiple contacts or single contacts???

➢Current from source to drain is distributed over entire width of the of MOS.
➢Electrical width of the MOS is same as geometrical width of the device.

Course Instructor: Mrs Deepthi M S

14
VLSI Layout Design
Parasitics in transistors

Course Instructor: Mrs Deepthi M S

15
VLSI Layout Design
Multifinger transistors
• Wide transistors are usually “folded” so as to reduce both the S/D junction area
and the gate resistance.

Example: Folding reduces

the gate resistance by a factor of four.

Course Instructor: Mrs Deepthi M S

16
VLSI Layout Design
(a) Simple folding of a MOSFET; (b) use of
multiple fingers.

Course Instructor: Mrs Deepthi M S

17
VLSI Layout Design
Latch-up in CMOS
• Occurs in CMOS technology.

• The CMOS chip in this state → draws huge current from power supply.

• Does not respond to input stimuli.

• Chip operating normal may go into latch-up condition.

• Removing – reconnecting the supply may restore the operations.

Course Instructor: Mrs Deepthi M S

18
VLSI Layout Design
Latch-up in CMOS
• In turn latch-up creates low impedance path between power supply rails.

• It is due to triggering of parasitic bipolar transistor structures within the IC, when
applying stimulus on input/output.

Course Instructor: Mrs Deepthi M S

19
VLSI Layout Design
Course Instructor: Mrs Deepthi M S
20
VLSI Layout Design
Latch-up in CMOS Inverter

Course Instructor: Mrs Deepthi M S

21
VLSI Layout Design
Latch-up in CMOS
• Emitter, base, and collector of transistor Ql are the source of the
PMOS, n-well, and substrate, respectively.
• Collector, base, and emitter are the n-well, substrate, and source of
the NMOS transistor Q2.
• Resistors RW1 and RW2 → the resistance of the n-well
• RS1 and RS2 → resistance of the substrate.
• C1 → drain implant depletion capacitance between drain of PMOS &
n-well.
• C2 → drain implant depletion capacitance between drain of NMOS &
substrate.
Course Instructor: Mrs Deepthi M S
22
VLSI Layout Design
Parasitic circuit due to latch-up in CMOS
Inverter

Course Instructor: Mrs Deepthi M S

23
VLSI Layout Design
Latch-up prevention
• Slow the rise and fall times of the logic gates, reducing the amount of signal fed
through Cl and C2.
• Reducing the areas of Ml and M2's drains lowers the size of the depletion
capacitance and the amount of signal fed through.
• Best method of reducing latch-up effects is to reduce the parasitic resistances RW1
and RS2.
• the closer these contacts are to the MOSFETs used in the inverter, the less
likely it is that the inverter will latch up
• Placing guard rings around the PMOS & NMOS devices.
• Increase well and substrate doping concentrations to reduce Rwell and Rsub.

Course Instructor: Mrs Deepthi M S

24
VLSI Layout Design
Metal Layers
• Metal layers in a CMOS integrated circuit connect circuit elements,

✓MOSFETs, capacitors, and resistors

• Metal in a CMOS process is either aluminum or copper.

• Levels of METAL → metal1 & metal2

Course Instructor: Mrs Deepthi M S

25
VLSI Layout Design
 Bonding Pads
• Connects the circuit on a die to
a pin on a packaged chip.
• Electrical connection between
chip & package is provided by
“bonding wires”.

Course Instructor: Mrs Deepthi M S

26
VLSI Layout Design
Bonding Pads
• The layout of a pad that uses metal2 is shown below,

Course Instructor: Mrs Deepthi M S

27
VLSI Layout Design
Metal l and Via l:
• Metal l is a layer of metal found directly below metal2.
• The vial layer connects metal l and metal 2.
• The via layer specifies that the insulator be removed in the location indicated.
• A “tungsten plug” is fabricated in the insulator’s opening.
• When Metal 2 layer is laid down, “plug” provides contact between metal 1 &
metal 2.

Course Instructor: Mrs Deepthi M S

28
VLSI Layout Design
Course Instructor: Mrs Deepthi M S
29
VLSI Layout Design
IR drop
• Also called “voltage drop”.
• Voltage drop → reduction in voltage in an electrical circuit between the source and
load.
• IR drop → Across the power distribution network of an integrated circuit due to
resistive losses and current flow.
• Power supply in the chip is distributed uniformly through metal layers (VDD &
VSS).
• The metal layers have finite amount of resistance → 𝟎. 𝟏 Ω 𝒑𝒆𝒓 𝒔𝒒𝒖𝒂𝒓𝒆 𝒖𝒏𝒊𝒕.
• As the current flows through the metal layer there will be considerable
voltage drop.

Course Instructor: Mrs Deepthi M S

30
VLSI Layout Design
IR drop
• IR drop becomes significant in High-Speed circuits.
• Because of skin effect, as frequency of signal increases resistivity of metal layers
increases.

Course Instructor: Mrs Deepthi M S

31
VLSI Layout Design
IR drop issues
➢The Voltage drop in “reference” and “Power supply (𝑉𝐷𝐷 )” lines
affect
> voltage reference circuits.
➢IR drop on Power Supply Line:
Small voltage drops → mirror current error

Course Instructor: Mrs Deepthi M S

32
VLSI Layout Design
IR drop issues

Course Instructor: Mrs Deepthi M S

33
VLSI Layout Design
IR drop issues

Course Instructor: Mrs Deepthi M S

34
VLSI Layout Design
Guard Rings
What are Guard Rings?
• Guard rings are used to collect carriers flowing in the silicon.
• Each type of transistor can be surrounded by a protection ring:
✓NMOS transistors by a P+ ring
✓ PMOS transistors by a N+ one.
• Gain of NPN transistor is reduced by P+ guard ring
• Gain of PNP transistor is reduced by N+ guard ring

The role of the guard ring is to provide electrical isolation between the pnp and
the npn structure !!!!
Course Instructor: Mrs Deepthi M S
35
VLSI Layout Design
Guard Rings
• Guard rings within the pnp-npn structures lowers the parasitic bipolar gain by the
following means:

✓Increases the base width of the parasitic pnp or npn structure.

✓Provides a region of heavy doping concentration to increase the recombination

within the parasitic, ‘‘capturing’’

Course Instructor: Mrs Deepthi M S

36
VLSI Layout Design
Guard Rings
• Design-related issues with the use of guard ring structures:

• Guard rings require chip area.

• Some semiconductor computer aided design (CAD) methodologies can not

check and verify guard ring placement and its correct type.

Course Instructor: Mrs Deepthi M S

37
VLSI Layout Design
Guard Rings

Course Instructor: Mrs Deepthi M S

38
VLSI Layout Design
Pad Rings
• Pads are placed next to
each other, with the
corresponding bond pads
lined up against each
other having a small gap
in between.
• Pad ring consists off →
scribe streets, pads, ESD
structures, and guard
rings.

Course Instructor: Mrs Deepthi M S

39
VLSI Layout Design
Scribe Streets
• Surrounds the die, provides passage
for saw blade to separate the die.
• Saw consumes 25 µm wide strip of
silicon,
• Scribe street must be 3 or 4 times the
wider.

Course Instructor: Mrs Deepthi M S

40
VLSI Layout Design
ESD Structures

Course Instructor: Mrs Deepthi M S

41
VLSI Layout Design
Phenomenon of ESD

Course Instructor: Mrs Deepthi M S

42
VLSI Layout Design
ESD threats on IC products

Course Instructor: Mrs Deepthi M S

43
VLSI Layout Design
Types of ESD Stress Models
• ESD may occur in various situations.
• Three specific types of ESD models.
• Human body model (HBM)
• Machine Model
• Charged Device Model

Course Instructor: Mrs Deepthi M S

44
VLSI Layout Design
Types of ESD Stress Models
➢Human body model (HBM)
• ESD stress caused by the ESD phenomenon that occurs when an
electrostatically charged human body contacts a chip and forms a discharge
path.

➢ Machine Model (MM)

• charged machine or tool with a static charge contacts the chip and forms a
discharge path to the ground while on the production line.

➢ Charged Device Model (CDM)

• IC (integrated chip) is charged during fabrication, production or
transportation

Course Instructor: Mrs Deepthi M S

45
VLSI Layout Design
Course Instructor: Mrs Deepthi M S
46
VLSI Layout Design
ESD models

Course Instructor: Mrs Deepthi M S

47
VLSI Layout Design
Course Instructor: Mrs Deepthi M S
48
VLSI Layout Design
Course Instructor: Mrs Deepthi M S
49
VLSI Layout Design
ESD structures
• ESD structures resides near to bondpads.
• ESD structures must have low-impedance path to substrate.
• ESD structures protects the remainder of the IC.
• ESD device must conduct large peak currents without failure.

Course Instructor: Mrs Deepthi M S

50
VLSI Layout Design
Zener Clamp

• Zener diode impose a positive clamp voltage equal to its

reverse breakdown voltage.
• Negative clamp equal to its forward drop.
• Internal series resistance of Zener, increases the clamp
voltage above the ideal values,
• makes it robust and spreads the ESD energy
• Drawback: bondpad voltage rise above theoretical clamp voltage

Course Instructor: Mrs Deepthi M S

51
VLSI Layout Design
Two Zener Clamp
• Zener diode has series internal resistance. (>
10 Ω)
• The 2kV HBM strike → produces peak
current of 1.3 A.
• Produces sufficient voltage drop across Zener
series resistance → ruptures → gate
dielectric.
• Additional clamping by 2nd ESD structure.

Course Instructor: Mrs Deepthi M S

52
VLSI Layout Design
Two Zener Clamp
• Diode D1 clamps the ESD voltage to 100 V.
• The resistance R1 limits the current through
the Zener diode D2.
• The diode D2 further clamps the voltage to
lower level, protecting the gate dielectric.
• The value of R1 should be several times of
series resistance of D2.

Course Instructor: Mrs Deepthi M S

53
VLSI Layout Design
Two Zener Clamp
• Suitable for high impedance input terminals,
• Because of high series resistance.

Course Instructor: Mrs Deepthi M S

54
VLSI Layout Design
Buffered Zener Clamp
➢Uses NPN transistor to reduce the effective
series resistance of Zener diode.
➢Zener diode provides base drive to NPN
transistor.
➢Transistor multiplies the current through the
Zener diode by its “beta” value.

Course Instructor: Mrs Deepthi M S

55
VLSI Layout Design
Buffered Zener Clamp
➢Positive clamp voltage is 𝑉𝑧 + 𝑉𝐵𝐸 .
➢Maximum clamp voltage provided by the
structure is 𝑉𝐶𝐸𝑂(𝑠𝑢𝑠) .
➢𝑉𝐶𝐸𝑂(𝑠𝑢𝑠) → Collector-Emitter Sustaining
Voltage.
➢Collector-emitter breakdown voltage with the
base open circuit

Course Instructor: Mrs Deepthi M S

56
VLSI Layout Design
Buffered Zener Clamp
➢Structure dissipates most of the energy in
large collector-base depletion region.
➢Larger the NPN → higher ESD voltage
protection.

Course Instructor: Mrs Deepthi M S

57
VLSI Layout Design
Thick field device NMOS
• nMOS is used as ESD protection
device.
• Gate is grounded to ensure the
device is off under normal
operation.
• Under normal operation, 𝐼 𝑠𝑢𝑏 =
0,−→ 𝑉 𝐵 = 0
• Drain-substrate/source-substrate
are reverse biased.

Course Instructor: Mrs Deepthi M S

58
VLSI Layout Design
Thick field device NMOS
• When 𝑉𝐷 ↑, drain-substrate undergo
avalanche breakdown.
• Electrons → drain, holes → substrate ,
hence 𝐼𝑠𝑢𝑏
• The base potential 𝑉𝐵 ↑, parasitic BJT
is ON
• Static charge on PADs is discharged
via BJT to the ground.
• Base width of parasitic BJT equals to
channel length of MOS.

Course Instructor: Mrs Deepthi M S

59
VLSI Layout Design
Gate coupled nMOS transistors
• In the previous ESD structure, the
gate of nMOS → grounded.

• This ensure no extra leakage at the

pin during normal operation.

• But biasing the gate of nMOS will

reduce the avalanche breakdown
voltage of nMOS.

Course Instructor: Mrs Deepthi M S

60
VLSI Layout Design
Gate coupled nMOS transistors
• Values of C1 and R1 does not have
any effect during normal operation.

• During ESD strike they couple

sufficient voltage to gate, so that
avalanche breakdown voltage is
reduced.

Course Instructor: Mrs Deepthi M S

61
VLSI Layout Design
Course Instructor: Mrs Deepthi M S
62
VLSI Layout Design
Gate coupled nMOS transistors
• C1 behaves as short during ESD
strike (high frequencies).

Course Instructor: Mrs Deepthi M S

63
VLSI Layout Design
Decoupling Capacitors
• Decoupling capacitor is a capacitor, decouples the critical cells from main power supply , to
protect them incase of disturbance in power distribution lines.

• Capacitors → like batteries → stores energy.

• If the input voltage suddenly drops, the capacitor provides the energy to keep the voltage
stable

Course Instructor: Mrs Deepthi M S

64
VLSI Layout Design
Why Decoupling Capacitors??

'ground bounce'.

Course Instructor: Mrs Deepthi M S

65
VLSI Layout Design
Decoupling Capacitors
• The average current supplied by VDD may be well under a microamp;

• the occasional need for 50 uA still creates or causes problems.

• To overcome this, we use decoupling capacitor between Vdd and gnd.

Course Instructor: Mrs Deepthi M S

66
VLSI Layout Design
Course Instructor: Mrs Deepthi M S
67
VLSI Layout Design
Types of DeCap

Course Instructor: Mrs Deepthi M S

68
VLSI Layout Design
nMOS Decap
• Thin-oxide capacitance of the transistor gate provides a higher capacitance than
any other oxide capacitance available in a standard CMOS fabrication process.

• At the 90nm → oxide thickness → 2.00 nm

• The thin oxide causes two new problems

• oxide breakdown (ESD event)

• gate tunnelling leakage

nMOS decap rather inappropriate for 90nm and below

Course Instructor: Mrs Deepthi M S
69
VLSI Layout Design
Cross coupled Decap
• Compared to nMOS decap only metal wires are
modified.
• Both transistors in this design are still in the linear
region.
• In the standard decap design, the gates of the
transistors are directly connected to either VDD or
VSS.
• In this case, the gate of the NMOS device is
connected to VDD through the channel resistance
of the PMOS device.
• the gate of the PMOS device is tied the channel
resistance of the NMOS device and then
connected to VSS.
Course Instructor: Mrs Deepthi M S
70
VLSI Layout Design
Cross coupled Decap
• The added channel resistance to the gate provides
the input resistance Rin for ESD protection.

Course Instructor: Mrs Deepthi M S

71
VLSI Layout Design
Design Rule Check(DRC)
• DRC (Design Rule Check) is a program, that check the layout laid out by layout
engineer.
• Good design rule control files → finds tiniest mistake in the layout.
• DRC program → asserts bunch of error markers in layout → locates errors.
• DRC process → iterative
• DRC → first level of checking → DRC clean → need not mean layout is wired
correctly.

• Layout versus schematic → second level of checking of layout

Course Instructor: Mrs Deepthi M S

72
VLSI Layout Design
How DRC program identifies components
&check layout ?
• DRC uses sequence of commands that contains
Boolean operators.

• Simple Boolean operations → ‘AND’ ‘OR’

• DRC → takes two layers → output is third layer

based on Boolean function.

Course Instructor: Mrs Deepthi M S

73
VLSI Layout Design
How DRC program identifies components
&check layout ?
AND function:
• Output layer present in the area, where both layer A
& B are present.

• This information kept temporarily or in memory.

Course Instructor: Mrs Deepthi M S

74
VLSI Layout Design
How DRC program identifies components
&check layout ?
AND function:
• The AND function is good in finding CMOS
transistors.

• In CMOS → a poly runs on top of active layer.

Course Instructor: Mrs Deepthi M S

75
VLSI Layout Design
How DRC program identifies components
&check layout ?
AND function:
• Output layers assigned to temporary layers.

• Temporary layers can be used in future to

check another layout.

TMP1 = POLY AND ACTIVE

This line is written in control files!!!

Course Instructor: Mrs Deepthi M S

76
VLSI Layout Design
How DRC program identifies components
&check layout ?
AND function:

• TMP1 can be used in a Boolean operation

with another layer.

• Output of that call it as → TMP2

• TMP2 = TMP1 AND NWELL

• AND of CMOS with NWELL → finds TMP2 contains location of all PMOS
transistors!!!!!
PMOS
Course Instructor: Mrs Deepthi M S
77
VLSI Layout Design
How DRC program identifies components
&check layout ?
OR function:

• The output of OR on our sample layers

would look like a larger polygon than
either of the originals.

• OR function merges two polygons into

one.

• TMP3 = TMP2 OR PPLUS

Course Instructor: Mrs Deepthi M S
78
VLSI Layout Design
How DRC program identifies components
&check layout ?
OR function:

• Example: bunch of transistors & bunch of

resistors.

• They share common design rules.

• So merge both layers into one & check

design rules.

Course Instructor: Mrs Deepthi M S

79
VLSI Layout Design
How DRC program identifies components
&check layout ?
NOT function:

• The NOT function, particularly in DRC’s,

can be described as an AND NOT function.

• TMP4 = A NOT B

• TMP4 = A AND NOT B

Course Instructor: Mrs Deepthi M S

80
VLSI Layout Design
How DRC program identifies components
&check layout ?
NOT function:

Example:

• Resistor layer in conjunction with another

layer to change the doping of resistor layer.

• Both layers → different design rules.

• NOT function will throw away , doped

portions of resistor layer.
Course Instructor: Mrs Deepthi M S
81
VLSI Layout Design
How DRC program identifies components
&check layout ?

Course Instructor: Mrs Deepthi M S

82
VLSI Layout Design
How DRC program identifies components
&check layout ?
• NOT function is order-sensitive
• A NOT B will give you different output than B NOT A.

Course Instructor: Mrs Deepthi M S

83
VLSI Layout Design
How DRC program identifies components
&check layout ?

Course Instructor: Mrs Deepthi M S

84
VLSI Layout Design
Design Rules:
• Several design rules will be checked on
device layers.
• First check is an external check.

• This line of code checks the external edges

of your polygons against each other.

Course Instructor: Mrs Deepthi M S

85
VLSI Layout Design
Design Rules:

Course Instructor: Mrs Deepthi M S

86
VLSI Layout Design
DRC rules control file

Course Instructor: Mrs Deepthi M S

87
VLSI Layout Design
Layout Versus Schematic (LVS)
• LVS generates netlist of layout.
• LVS checking compares extracted netlist from layout & original schematic netlist to
determine they match.
• All devices & nets of layout matches with that of schematic → LVS clean.

Sample netlist generated by LVS

program

Course Instructor: Mrs Deepthi M S

88
VLSI Layout Design
LVS : Problem solving
1. Check Number of Devices
• LVS first checks if there are same number of devices in layout & schematic.

• One extra resistor in the layout!!!!!

Course Instructor: Mrs Deepthi M S

89
VLSI Layout Design
LVS : Problem solving
2. Check Types of Devices
LVS checks for correct type of devices.

• One resistor built from the wrong material.!!!!!

Course Instructor: Mrs Deepthi M S

90
VLSI Layout Design
LVS : Problem solving
3. Check Number of Nets
• Each contiguous group of wires is a net.
• There are 5 nets in the schematic.

• Example: layout have 6 nets → there is discrepancy

!!!

Course Instructor: Mrs Deepthi M S

91
VLSI Layout Design
LVS : Problem solving

• More nets in layout than in schematic.

• Means → open circuit in layout.
• Example for open circuit → missing via
between M1 & M2.

Course Instructor: Mrs Deepthi M S

92
VLSI Layout Design
LVS : Problem solving

• Less nets in layout than in schematic.

• Means → short circuit in layout.
• Example for short circuit → extra wire shorts
two net2 & net3.

Course Instructor: Mrs Deepthi M S

93
VLSI Layout Design
LVS : Problem solving
4. Solving Complex Net Problems
LVS also gives number components on the nets.
• Example : VCC1 → net1; VCC2 → net2

Course Instructor: Mrs Deepthi M S

94
VLSI Layout Design
LVS : Problem solving
5. Named Nets
LVS may show problem in named nets.
• That’s good!!!!

• Because we know where they are!!!!!

Course Instructor: Mrs Deepthi M S

95
VLSI Layout Design
LVS : Problem solving
5. Named Nets
Work on smaller named nets first.

Course Instructor: Mrs Deepthi M S

96
VLSI Layout Design
LVS : Problem solving
6.

Course Instructor: Mrs Deepthi M S

97
VLSI Layout Design
LVS inputs

Course Instructor: Mrs Deepthi M S

98
VLSI Layout Design
LVS inputs

Course Instructor: Mrs Deepthi M S

99
VLSI Layout Design
Parasitic Extraction
• Parasitic extraction, in EDA is calculation of the parasitic effects in,
• Designed devices
• Interconnects
• Parasitic capacitance, parasitic resistance & parasitic inductance→ parasitic
components.

• PEX → provides link between → physical & electrical domain

• Major goal of PEX → to provide analog model of the design → allows detailed
simulation of the design
• Timing analysis
• Power analysis
• Signal integrity analysis

Course Instructor: Mrs Deepthi M S

100
VLSI Layout Design
 Effects of Parasitic devices on circuit design:
• Extra power consumption
✓Violation of power specification
✓Extra power dissipation leads to increase in local temperature
• Effect on the delay of the circuit
✓Timing violation
✓Impact on IR drop
• Reduce the noise margin
✓Logic failure
• Increase signal noise
✓Logic failure
✓Unwanted delay and thus effects the timing
Course Instructor: Mrs Deepthi M S
101
VLSI Layout Design
Use of Parasitic Extraction
• Static timing analysis
✓Helps to find the RC delay of the network & hence helps to perform STA.
• Noise analysis, crosstalk analysis, signal integrity check
✓to perform noise & crosstalk analysis, it is important to understand the relationship
between two wires.
✓Finding coupling capacitors between two wires, helps to perform SI(noise &
crosstalk).
• IR analysis
✓Helps to find the parasitic resistance, which is used analyse IR drop
✓Extra power dissipation leads to increase in local temperature
• Substrate noise analysis
✓PEX helps to find the substrate resistance.
✓Noise is passed through the substrate because of its finite resistance.

Course Instructor: Mrs Deepthi M S

102
VLSI Layout Design
Parasitic capacitance modelling for MOS
transistor

Course Instructor: Mrs Deepthi M S

103
VLSI Layout Design
Interconnect parasitic capacitance

Course Instructor: Mrs Deepthi M S

104
VLSI Layout Design
Interconnect parasitic capacitance

• Rate at which thickness of METAL decreases is less

than decrease in the spacing between the METAL
layers.
• Hence, as technology ↓ , area capacitance ↓ and
coupling capacitor ↑.
• Hence designer ignore coupling capacitors in higher
technology & ignore area capacitors in lower
technology
Course Instructor: Mrs Deepthi M S
105
VLSI Layout Design
 Interconnect parasitic resistance
• Every material used in CMOS design has → different resistivity

Course Instructor: Mrs Deepthi M S

106
VLSI Layout Design
Interconnect parasitic resistance

• As technology goes down, resistance of the interconnects increases.

During stepping into 180 nm technology the Aluminum interconnects were replaced by Copper.

Course Instructor: Mrs Deepthi M S

107
VLSI Layout Design
Field Solver Based PEX
• PEX engine solves Maxwell’s equations to calculate the parasitic R, C, L.
• Field solvers calculate the strength of electromagnetic field lines by solving
Maxwell’s equations.

• It is a higher accuracy method.

• Compute intensive method.
• Takes more processing power and is not used for full-chip extraction.

• Can handle complex 3 dimensional geometries, also not restricted to pre-

conceived model of parasitics effects.

Course Instructor: Mrs Deepthi M S

108
VLSI Layout Design
Field Solver Based PEX

Course Instructor: Mrs Deepthi M S

109
VLSI Layout Design
Rule Based PEX
• PEX engine uses a look up table to calculate the parasitic R or C.
• Measures the dimensions of the wires in the design and the separation (distance)
from neighboring wires,
✓then plugs these values into an internal model to calculate the parasitic values.
• Rule-based extraction tools use a set of multi-dimensional tables or equations
derived from the process specifications to generate the correct variables for the
tools’ internal parasitic equations.
• rule-based extraction offers fast processing with reasonable accuracy when
interconnect delay is the dominant effect.

Course Instructor: Mrs Deepthi M S

110
VLSI Layout Design
Rule Based PEX

Course Instructor: Mrs Deepthi M S

111
VLSI Layout Design
Poly-Poly Capacitors
• In CMOS process there can be a
added layer of polysilicon called
poly2.
• Poly-poly capacitor
formation
• MOSFET formation
Layout of poly-poly capacitor
• Layout and cross-sectional
views of a capacitor using the
polyl and poly2 layers is shown
below

Course Instructor: Mrs Deepthi M S

112
VLSI Layout Design
Poly-Poly Capacitors
• The value of the capacitance is
calculated as below,

• where ‘A’ represents area of

intersection of poly1 & poly2

Course Instructor: Mrs Deepthi M S

113
VLSI Layout Design
Metal Capacitors
• One method of forming capacitors in a
single-poly CMOS process.
• Capacitance between the metal 1 and
metal 2 dominates because the metals
have a large layout area (fringe
capacitance becomes negligible).

• If the capacitance per area is 50 aF/um2,

then it would take an area of 100 um by
200 um to implement a 1 pF capacitor

Course Instructor: Mrs Deepthi M S

114
VLSI Layout Design
Metal Capacitors
• The main problem occurs from the
extremely large bottom plate parasitic
capacitance,
✓the capacitance from metal 1 to
substrate
✓This can be anywhere between 80 %
to 100 % of desired capacitance value.
✓it usually slows the circuit response
and results in a waste of power

Course Instructor: Mrs Deepthi M S

115
VLSI Layout Design
Metal Capacitors
• Four layers of metal used for
implementation of a capacitor, to help
decrease the bottom plate's percentage of
the desired capacitor value.

• If plate capacitance between each metal

layer is, again, 50 aF/um2, then the area
required to implement a 1 pF capacitor is
100 um by 66 um.

Course Instructor: Mrs Deepthi M S

116
VLSI Layout Design
Metal Capacitors
• The area needed is reduced by one-third
of the area used in the metal l/metal2-only
capacitor.
• While we used the same plate capacitance
value in between each level the actual
value will vary because of the differing
thickness in between the metals.

Course Instructor: Mrs Deepthi M S

117
VLSI Layout Design
 Metal Capacitors: Metal 2 & via
• It is sometimes called a lateral capacitor.

• To avoid coupling noise into the relatively

large area occupied by the capacitor, a
ground plate is placed above the
capacitor.
• This would allow noisy digital signals to
be routed above the capacitor

Course Instructor: Mrs Deepthi M S

118
VLSI Layout Design