Course: VLSI Layout Design (21EC7E13)

Module 4:
Layout Failure Mechanisms
Course Instructor:
Deepthi M S
IC Failure Mechanisms
• Integrated circuit reliability is represented in the figure
(bathtub curve).
• ICs are subjected to failure eventually due to various
conditions.
• The ICs are not susceptible to wear-out mechanisms.
• Early life failure → defects & contamination introduced
during IC manufacturing.
• Due to well documented process, early life failure
rarely occurs.
• Failure mechanisms are caused by heat, current, voltage,
humidity & temperature.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Electrical Overstress
• Electrical overstress (EOS): failures caused by
application of excessive voltage or current to the
component.
• The SOA of a semiconductor device shows → voltage
& current limit.
• Electrical over-voltage (EOV)
• Electric over-current (EOC)
• Electrical over-power (EOP)
• EOS leads to
❖melted packages
❖blown single component capacitors and resistors
❖ruptured packages
❖blown bond wires
❖cracked dielectrics
❖fused and melted metal layers
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design
Electromigration
• EM is a slow wear-out mechanism caused by hig current densities.
• Definition: gradual displacement of metal atoms in metal interconnects.
• It happens when current density is high and it causes metal atoms to drift in the
directions of electron flow.
• Transport of material by gradual movement of ions in a conductor due to momentum
transfer between electrons and metal atoms.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Electromigration
• EM is a slow wear-out mechanism of metal wires.
• Metal atoms migrate over a period of time, causing open circuits, short circuits, or
unacceptable increase in resistance.
• There are two main causes of electromigration failure:
• High DC current densities.
• Joule heating

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Electromigration Damages:

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Reasons for Electromigration:

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Prevention Techniques for Electromigration:
✓ Process improvements: Aluminum metallization is doped with 0.5 to 4% of Copper to
improve electromigration resistance.
✓ Cu increases the activation energy required to dislodge the metal atoms to create
voids.
✓ Increase the width of the wire.
✓ Decrease the drive strength.
✓ Use Gold bondwires rather than Aluminum wires

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Antenna Effect:
✓ Gate oxide is the most sensitive component of MOS device.
✓ Antenna effect → is a layout failure mechanism → cause damage to gate oxide.
✓ Due to plasma etching process (dry etching).

✓ Plasma etching used in fabrication of metal interconnects.

✓ Metal interconnects collects high energetic charges during etching process.
✓ Amount of charge collect is proportional to surface area of the interconnect.
✓ Metal interconnect is connected to poly → hence potential of poly also increases.
✓ This causes current to pass through the gate oxide.(degrades the dielectric strength)
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design
Antenna Effect:
✓ Damage of gate oxide due to charge collected by large geometry-based poly is defined
as “antenna effect”.

✓ Effects:
✓ gate oxide breakdown,
✓ mobility degradation and
✓ threshold voltage shift.

• Magnitude of “antenna effect” is proportional to ratio between exposed conductor

area and gate oxide area.
• Hence large conductor/gate area ratios required to produce significant damage.
• “Antenna effect” is limited to few locations on the die.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Example of Layout Susceptible to Antenna Effect

• Metal jumper tremendously reduce the poly geometry connected to the gate oxide of
NMOS “M1” → reduces conductor/gate area ratio.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Course Instructor: Mrs Deepthi M S
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Surface Effects:
✓ Surface regions exposed to high electric field will inject hot
carriers into the overlying oxide → surface effects.

Hot carrier injection

What are hot carriers???

• Electric field → drift velocity in electrons

• Normally drift velocity is smaller than instantaneous
velocities of electrons.
• High electric field intensity
• Drift velocity > instantaneous velocity of electrons
• The carriers with extreme high speed → hot electrons.
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design
Hot Electron Injection in NMOS transistor:
•MOS transistor operated in saturation
region with → high 𝑉𝐷𝑆 , creates
pinched region near drain end.
•As 𝑉𝐷𝑆 ↑, pinched region → wider.
•Electric field near drain end →
intensifies.
•Hot carriers are generated near drain.

•Hot carriers → electrons(NMOS).

•Hot carriers → holes(PMOS).

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Hot Electron Injection: NMOS
•The hot electrons collides with the
lattice atoms near drain end,
•Produces electron-hole pair.
• The charges travel through the
overlying oxide layer.
• Some charges trap in the oxide layer
in defective sites.
• This oxide charge increases, causing
drifting in the threshold voltage of
the device.
• Increases the 𝑉𝑇 of NMOS.
• Decreases the 𝑉𝑇 of PMOS

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Hot Electron Injection: Zener walk out
•Avalanching junction also produces →
hot carriers.

•Avalanche occurs near surface in most

diffused junctions.

•Hot carriers produced by the surface

travel through the overlying oxide.

•Example for avalanche junction: base-

emitter junction of BJT

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Hot Electron Injection: Zener walk out
•Hot holes are injected to the overlying
oxide.

•The depletion region near the surface

widens.
•Avalanche voltage increases gradually
→ termed as “Zener walk-out”.

•The knee voltage of the base-emitter

junction will move to higher values.
•Due to widening of the depletion
region.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Hot Electron Injection: Preventive measures
• Usage of lightly doped drain (LDD)
structures in MOS transistors.
• Transistors used as switches,
generate few hot carriers.
• Device in either ON/OFF.
• No current flow across large
source-drain differential voltage.
• Hot carriers are generated only
during brief switching period.
• Long channel devices
• Hot carries only near the drain,
rest of the channel not affected.
• Usage of buried Zener diodes.
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design
Parasitic Channels:
• Any conductor placed above silicon
surface induces parasitic channel.

Types of parasitic channels:

• A PMOS parasitic channel can form

across any lightly doped-N type
region, such as N-tank in bipolar
Figure: Parasitic PMOS in a standard bipolar
process or N-well in a CMOS process.
process.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Parasitic Channels:
• Any conductor placed above silicon
surface induces parasitic channel.

Types of parasitic channels:

• A NMOS parasitic channel can form

across any lightly doped-P type
region, such as P-epi of CMOS
Figure: Parasitic NMOS in a N-well process
process or lightly doped P-type
isolation in bipolar process

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
PMOS Parasitic Channels:
• Lead acts as gate.
• Base region forms source.
• Isolation serves as drain.
• A parasitic channel is formed of the
voltage difference between the lead
& base region exceed threshold
voltage of the parasitic PMOS.
• The threshold voltage is called
Figure: Parasitic PMOS in a standard bipolar
PMOS- thick field threshold. process.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Parasitic Channels:
• The lead acts as gate.
• Two adjacent wells serves as source
& drain.
• A parasitic channel is formed when
the voltage difference between the
lead & source exceed the NMOS-
thick field threshold.

Figure: Parasitic NMOS in a N-well process

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Charge spreading:
• Parasitic channel can also form without the presence of the conductor that acts as
gate.

• Only the presence of suitable source & drain regions required.

• The mechanism underlying the formation of such channel is called charge

spreading.

• The charge spreading mechanism is because of “static electrical charges”

present at insulating surface.

• Primarily they are electrons.

• Source of these charges → Course

not Instructor:
fully Mrs understood.
Deepthi M S
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VLSI Layout Design
Charge spreading:
• The base region in the N-tank is biased above P-thick field threshold.
• Electrons in the overlying insulating layer will tend to move towards positively
charged tank.
• Electrons accumulate over the tank and induces the channel.
• The static charge generated by charge spreading behaves as the gate electrode of a
MOS transistor.

Figure: Cross section of a standard bipolar structure susceptible to charge spreading

(A) before (B) after an extended period of operation under bias.
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design
Charge spreading:

• Charge spreading produces parasitic PMOS transistors because there is

accumulation of negative charges.

Figure: Cross section of a standard bipolar structure susceptible to charge spreading

(A) before (B) after an extended period of operation under bias.
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design
Preventive measures (CMOS)
• The poly lead running over N-well containing P-diffusion biased region forms
parasitic channels.
• Solution: pull the poly lead inside the N-well.
• Parasitic channel forms only under the poly, the complete channel is not formed if
the lead does not bridge the gap between source & drain.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Contamination
• ICs are vulnerable to certain types of “contaminants”.
• Plastic encapsulation is formulated to provide higher degree of resistance to
penetration by external contaminants.

• Two major contamination issues

✓Dry corrosion
✓Mobile ion contamination

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Contamination: Dry Corrosion
• The aluminum metal → subjected to corrosion if exposed to ionic contaminants in
presence of moisture.
• Only trace of water is enough to initiate the corrosion process→ dry corrosion.

• The corrosion prevented by → secondary moisture barrier in moder ICs.

• Not enough, to prevent moisture entering through the openings made for bond
wires , fuse trims etc.,

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Contamination: Dry Corrosion
Effects:
• Phosphosilicate glass: amount of phosphorus > 5% is at corrosion risk, because
moisture leaches phosphorus from the glass forming phosphoric acid.
• This acid attacks the aluminium and dissolves it → causing open circuit failures.

• Solution: nitride protective layer to prevent moisture reaching phosphosilicate glass.

• The halogen ions in water → sodium chloride in the moisture can seep in to the die,
and corrode the aluminium metal system.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Contamination: Dry Corrosion
Preventive measures:
• Designer should minimize the size of the openings provided for the pads.
• Metal should overlap bondpad opening on all sides by a sufficient amount.
• Openings for metal fuses should be as small as possible, no other circuitry in that
opening.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Mobile Ion contamination:
• Many potential contaminants dissolve in the silicon dioxide at elevated temperatures.

• Normally at room temperature, contaminant ions become immobile → bounded to

oxide macromolecule.

• Exception: alkali metal ions → like sodium ions → remain mobile at room
temperature → mobile ions

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Mobile Ion contamination:
Effects:
• Parametric shift in the MOS transistor threshold voltage → mobile ion
contamination.
• Positively charged “Na” ions are distributed uniformly throughout the oxide initially.
• Application of positive gate bias → “Na” ions are pulled downwards.
• Result → net separation of charges within oxide.
• More “+” charges near the channel decreases the “threshold voltage”.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Mobile Ion contamination:
Preventive measures:
• Introduction of “Phosphorous” → immobilizes the alkali ions.
• Drawback: electrical charged “phosphorous” → causes dielectric polarization

• Protective overcoat (silicon nitride)→ prevents “Na” ions seeping into IC through
moisture.
• Scribe seals → around periphery of die -→ prevents ingress of ions

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Substrate Debiasing:
• The substrate of a device is usually connected
to the ground potential.
• In case of bipolar devices, the potential of the
substrate deviates from intended bias level.
• Due to injection of the carriers to the
substrate.
Current Injection into the Substrate:
• The collector injects the carriers into the
substrate.
• Due to substrate resistance 𝑹𝑺 , there is a
finite voltage drop across the substrate.
• This affects the biasing of the substrate → it
will forward bias the collector-substrate
junction of NPN transistor.
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design
Substrate Debiasing:
• Voltage required to forward bias the collector-substrate junction depends on current and
temperature.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Substrate Debiasing:
• Cross section of the standard bipolar wafer containing single substrate injector and single
substrate contact.
• 𝑹𝟏 model’s lateral resistance of the substrate & 𝑹𝟐 vertical resistance of the diffusion
(beneath the substrate contact).
• Total substrate resistance 𝑹𝑺 = 𝑹𝟏 + 𝑹𝟐
• Both the resistance values depends on process.
• Substrate lightly doped and diffusion heavily doped → 𝑹𝟏 > 𝑹𝟐

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Substrate Debiasing: Preventive measures
Heavily doped substrates:
• The contacts can extract a current 5 to 10 mA without causing debiasing.
• If the higher substrate current is anticipated total area of the contact is

𝜌𝑡𝑒𝑝𝑖 𝐼𝑆
𝐴𝑐 = 10
𝑉𝑑

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Substrate Debiasing: Preventive measures
Lightly doped substrates with heavily doped isolation:
• No simple formula to estimate the area of the contact to protect lightly doped substrate
from debiasing.
• Any device injecting current 100 µA or more, substrate contact near to the injector.
• Device with 1 mA or above, as many substrate contacts as possible.

• Large number of small substrate contact throughout the layout required.

• Move sensitive circuits away from substrate injectors.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Minority carrier injection
• Transient disturbances on the
external pin connected to the
collector of NPN Q1.
• If Q1 is “off”, this external
disturbance will pull the
substrate below ground level.
• Collector-substrate junction of
Q1 will get forward biased.
• Injects minority (electrons)
carriers into substrate.
• The carriers are collected by
other tank T1.
• A parasitic transistor Qp is
formed.
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design
Minority carrier injection
• The beta values of parasitic
transistor will be low,
because most of the minority
carriers recombine during
transit.
• But even such low beta
value can cause malfunction
of the circuit.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Minority carrier injection: Preventive measures
1. Eliminate forward bias junction that cause the problem
• Tank must not go below the substrate voltage level by 0.3V or they
will inject the minority carriers into the substrate.

2. Increase the spacing between the components

• Place sensitive circuitry far away from the injectors.
• Example: power transistors causes minority carrier injection; they are
usually part of output circuit.
• Hence placed away from sensitive input circuitry.

Course Instructor: Mrs Deepthi M S

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VLSI Layout Design
Minority carrier injection: Preventive measures
3. Increase the doping concentration
• Additional doping of the isolated regions which acts as the base of the
parasitic transistor, will reduce gain of the lateral parasitic transistor.

4. Provide alternate collectors

• The minority carriers are collected by alternate reverse biased
junctions placed near the injection point.
• Nearer junctions will block the carriers.
• Placed reverse biased junction between injection points & vulnerable
diffusions.
• Minority carrier guard ring.
Course Instructor: Mrs Deepthi M S
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VLSI Layout Design