MCP6041/2/3/4

600 nA, Rail-to-Rail Input/Output Op Amps

Features Description
• Low Quiescent Current: 600 nA/amplifier (typical) The MCP6041/2/3/4 family of operational amplifiers
• Rail-to-Rail Input/Output (op amps) from Microchip Technology Inc. operate with
• Gain Bandwidth Product: 14 kHz (typical) a single supply voltage as low as 1.4V, while drawing
less than 1 µA (maximum) of quiescent current per
• Wide Supply Voltage Range: 1.4V to 6.0V
amplifier. These devices are also designed to support
• Unity Gain Stable rail-to-rail input and output operation. This combination
• Available in Single, Dual, and Quad of features supports battery-powered and portable
• Chip Select (CS) with MCP6043 applications.
• Available in 5-lead and 6-lead SOT-23 Packages The MCP6041/2/3/4 amplifiers have a gain-bandwidth
• Temperature Ranges: product of 14 kHz (typical) and are unity gain stable.
- Industrial: -40°C to +85°C These specifications make these op amps appropriate
for low frequency applications, such as battery current
- Extended: -40°C to +125°C
monitoring and sensor conditioning.

Applications The MCP6041/2/3/4 family operational amplifiers are

offered in single (MCP6041), single with Chip Select
• Toll Booth Tags (CS) (MCP6043), dual (MCP6042), and quad
• Wearable Products (MCP6044) configurations. The MCP6041 device is
• Temperature Measurement available in the 5-lead SOT-23 package, and the
MCP6043 device is available in the 6-lead SOT-23
• Battery Powered
package.

Design Aids
Package Types
• SPICE Macro Models
MCP6041 MCP6043
• FilterLab® Software PDIP, SOIC, MSOP PDIP, SOIC, MSOP
• MAPS (Microchip Advanced Part Selector)
NC 1 8 NC NC 1 8 CS
• Analog Demonstration and Evaluation Boards
VIN– 2 7 VDD VIN– 2 7 VDD
• Application Notes
VIN+ 3 6 VOUT VIN+ 3 6 VOUT
VSS 4 5 NC VSS 4 5 NC
Related Devices
• MCP6141/2/3/4: G = +10 Stable Op Amps MCP6041 MCP6043
SOT-23-5 SOT-23-6
Typical Application VOUT 1 5 VDD VOUT 1 6 VDD
VSS 2 VSS 2 5 CS
IDD VDD VIN+ 3 4 VIN– VIN+ 3 4 VIN–
1.4V
10 MCP6042 MCP6044
to
6.0V
+ VOUT
PDIP, SOIC, MSOP PDIP, SOIC, TSSOP
100 k MCP604X
VOUTA 1 8 VDD VOUTA 1 14 VOUTD
–
VINA– 2 7 VOUTB VINA– 2 13 VIND–
1 M
VINA+ 3 6 VINB– VINA+ 3 12 VIND+
VSS 4 5 VINB+ VDD 4 11 VSS
V DD – V OUT
I DD = ------------------------------------------ VINB+ 5 10 VINC+
 10 V/V    10  
VINB– 6 9 VINC–
High Side Battery Current Sensor VOUTB 7 8 VOUTC

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MCP6041/2/3/4
1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
CHARACTERISTICS device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings † indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
VDD – VSS ........................................................................7.0V periods may affect device reliability.
Current at Input Pins .....................................................±2 mA †† See Section 4.1 “Rail-to-Rail Input”
Analog Inputs (VIN+, VIN–) ............. VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V
Difference Input voltage ...................................... |VDD – VSS|
Output Short Circuit Current ..................................continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Junction Temperature.................................................. +150°C
ESD protection on all pins (HBM; MM)  4 kV; 200V

DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, and RL = 1 Mto VL (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -3 — +3 mV VCM = VSS
Drift with Temperature VOS/TA — ±2 — µV/°C VCM = VSS, TA= -40°C to +85°C
VOS/TA — ±15 — µV/°C VCM = VSS,
TA= +85°C to +125°C
Power Supply Rejection PSRR 70 85 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB — 1 — pA
Industrial Temperature IB — 20 100 pA TA = +85°
Extended Temperature IB — 1200 5000 pA TA = +125°
Input Offset Current IOS — 1 — pA
Common-mode Input Impedance ZCM — 1013||6 — ||pF
Differential Input Impedance ZDIFF — 1013||6 — ||pF
Common-mode
Common-mode Input Range VCMR VSS0.3 — VDD+0.3 V
Common-mode Rejection Ratio CMRR 62 80 — dB VDD = 5V, VCM = -0.3V to 5.3V
CMRR 60 75 — dB VDD = 5V, VCM = 2.5V to 5.3V
CMRR 60 80 — dB VDD = 5V, VCM = -0.3V to 2.5V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 95 115 — dB RL = 50 k to VL,
VOUT = 0.1V to VDD0.1V
Output
Maximum Output Voltage Swing VOL, VOH VSS + 10 — VDD  10 mV RL = 50 k to VL,
0.5V input overdrive
Linear Region Output Voltage Swing VOVR VSS + 100 — VDD  100 mV RL = 50 k to VL,
AOL 95 dB
Output Short Circuit Current ISC — 2 — mA VDD = 1.4V
ISC — 20 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.4 — 6.0 V (Note 1)
Quiescent Current per Amplifier IQ 0.3 0.6 1.0 µA IO = 0
Note 1: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 1.4V and/or 5.5V.

DS20001669E-page 2  2019 Microchip Technology Inc.

 MCP6041/2/3/4
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, and CL = 60 pF (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 14 — kHz
Slew Rate SR — 3.0 — V/ms
Phase Margin PM — 65 — ° G = +1 V/V
Noise
Input Voltage Noise Eni — 5.0 — µVP-P f = 0.1 Hz to 10 Hz
Input Voltage Noise Density eni — 170 — nV/Hz f = 1 kHz
Input Current Noise Density ini — 0.6 — fA/Hz f = 1 kHz

MCP6043 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, and CL = 60 pF (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS — VSS+0.3 V
CS Input Current, Low ICSL — 5 — pA CS = VSS
CS High Specifications
CS Logic Threshold, High VIH VDD–0.3 — VDD V
CS Input Current, High ICSH — 5 — pA CS = VDD
CS Input High, GND Current ISS — -20 — pA CS = VDD
Amplifier Output Leakage, CS High IOLEAK — 20 — pA CS = VDD
Dynamic Specifications
CS Low to Amplifier Output Turn-on Time tON — 2 50 ms G = +1V/V, CS = 0.3V to
VOUT = 0.9VDD/2
CS High to Amplifier Output High-Z tOFF — 10 — µs G = +1V/V, CS = VDD–0.3V to
VOUT = 0.1VDD/2
Hysteresis VHYST — 0.6 — V VDD = 5.0V

CS VIL VIH

tOFF
tON

VOUT High-Z High-Z

-0.6 µA
ISS -20 pA (typical) -20 pA
(typical) (typical)

ICS 5 pA
(typical)

FIGURE 1-1: Chip Select (CS) Timing

Diagram (MCP6043 only).

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MCP6041/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +85 °C Industrial Temperature parts
TA -40 — +125 °C Extended Temperature parts
Operating Temperature Range TA -40 — +125 °C (Note 1)
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 JA — 256 — °C/W
Thermal Resistance, 6L-SOT-23 JA — 230 — °C/W
Thermal Resistance, 8L-PDIP JA — 85 — °C/W
Thermal Resistance, 8L-SOIC JA — 163 — °C/W
Thermal Resistance, 8L-MSOP JA — 206 — °C/W
Thermal Resistance, 14L-PDIP JA — 70 — °C/W
Thermal Resistance, 14L-SOIC JA — 120 — °C/W
Thermal Resistance, 14L-TSSOP JA — 100 — °C/W
Note 1: The MCP6041/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with reduced
performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification
of +150°C.

1.1 Test Circuits

The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “Supply Bypass”.

VDD
VIN 0.1 µF 1 µF

RN VOUT
MCP604X
CL RL
VDD/2 RG RF
VL

FIGURE 1-2: AC and DC Test Circuit for

Most Non-Inverting Gain Conditions.

VDD
VDD/2 0.1 µF 1 µF

RN VOUT
MCP604X
CL RL
VIN RG RF
VL

FIGURE 1-3: AC and DC Test Circuit for

Most Inverting Gain Conditions.

DS20001669E-page 4  2019 Microchip Technology Inc.

 MCP6041/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.

10% 18%
245 Samples
1124 Samples
16%

Percentage of Occurrences
9% 1 Representative Lot
Percentage of Occurrences

VDD = 1.4V and 5.5V

TA = +85°C to +125°C
8% VCM = VSS 14%
VDD = 1.4V
7% 12% VCM = VSS
6%
10%
5%
8%
4%
3% 6%
2% 4%
1% 2%
0% 0%
-3 -2 -1 0 1 2 3 -32 -28 -24 -20 -16 -12 -8 -4 0 4
Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C)

FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift
with TA = +85°C to +125°C and VDD = 1.4V.

12% 24%
1124 Samples 239 Samples
11% 22%
Percentage of Occurrences
Percentage of Occurrences

TA = -40°C to +85°C 1 Representative Lot

10% 20% TA = +85°C to +125°C
VDD = 1.4V
9% VCM = VSS 18% VDD = 5.5V
8% 16% VCM = VSS
7% 14%
6% 12%
5% 10%
4% 8%
3% 6%
2% 4%
1% 2%
0%
0%
-10 -8 -6 -4 -2 0 2 4 6 8 10
-32 -28 -24 -20 -16 -12 -8 -4 0 4
Input Offset Voltage Drift (µV/°C)
Input Offset Voltage Drift (µV/°C)

FIGURE 2-2: Input Offset Voltage Drift FIGURE 2-5: Input Offset Voltage Drift
with TA = -40°C to +85°C. with TA = +25°C to +125°C and VDD = 5.5V.

2000 2000
VDD = 1.4V VDD = 5.5V
Input Offset Voltage (µV)

1500 Representative Part 1500

Input Offset Voltage (µV)

Representative Part
1000 1000
500 500
0 0
TA = +125°C TA = +125°C
-500 -500 TA = +85°C
TA = +85°C
-1000 TA = +25°C
TA = +25°C -1000
TA = -40°C TA = -40°C
-1500 -1500
-2000 -2000
-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0

Common Mode Input Voltage (V) Common Mode Input Voltage (V)

FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs.
Common-mode Input Voltage with VDD = 1.4V. Common-mode Input Voltage with VDD = 5.5V.

 2019 Microchip Technology Inc. DS20001669E-page 5

MCP6041/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.

500 6
Input Offset Voltage (µV)

Input, Output Voltages (V)

450
4
VDD = 1.4V VIN VOUT
400
3
350 2
VDD = 5.5V
300 1

0 VDD = 5.0V
250 G = +2 V/V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -1
Output Voltage (V) 0 5 Time
10 (5 ms/div)
15 20 25

FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: The MCP6041/2/3/4 family
Output Voltage. shows no phase reversal.

1000 300

Input Noise Voltage Density

f = 1 kHz
Input Noise Voltage Density

VDD = 5.0V
250

200

(nV/—Hz)
(nV/¥Hz)

150

100

50

100 0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.1 1 10 100 1000
Frequency (Hz) Common Mode Input Voltage (V)

FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density
vs. Frequency. vs. Common-mode Input Voltage.

90 100
Referred to Input
80 95
CMRR, PSRR (dB)

PSRR, CMRR (dB)

70 PSRR
90 (VCM = VSS)
60
85
50
PSRR–
PSRR+ 80
40 CMRR
CMRR (VDD = 5.0V, VCM = -0.3V to +5.3V)
30 75

20 70
0.1 1 10 100 1000 -50 -25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (°C)

FIGURE 2-9: CMRR, PSRR vs. FIGURE 2-12: CMRR, PSRR vs. Ambient
Frequency. Temperature.

DS20001669E-page 6  2019 Microchip Technology Inc.

 MCP6041/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.

10k
10000 10000
10k

Input Bias and Offset Currents

Input Bias and Offset Currents

VDD = 5.5V VDD = 5.5V

VCM = VDD
1k
1000 1k
1000
TA = +125°C IB
100 100
100

(pA)
(pA)

IB

10 10
10 TA = +85°C | IOS |
| IOS |
1 11

0.1
0.1 0.1
0.1
45 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Ambient Temperature (°C) Common Mode Input Voltage (V)

FIGURE 2-13: Input Bias, Offset Currents FIGURE 2-16: Input Bias, Offset Currents
vs. Ambient Temperature. vs. Common-mode Input Voltage.

120 0 130
Gain
100 -30

DC Open-Loop Gain (dB)

120
Open-Loop Gain (dB)

Open-Loop Phase (°)

80 -60 110 VDD = 5.5V

Phase
60 -90 100
VDD = 1.4V
40 -120 90
20 -150 80
0 -180 70
VOUT = 0.1V to VDD – 0.1V
-20 -210 60
0.001
1.E- 0.01 0.1 1.E+
1.E- 1.E- 1 1.E+
10 1.E+
100 1.E+
1k 10k
1.E+ 100k
1.E+ 100 1k 10k 100k
1.E+02 1.E+03 1.E+04 1.E+05
03 02 01 Frequency
00 01 (Hz)
02 03 04 05 Load Resistance (:)

FIGURE 2-14: Open-Loop Gain, Phase vs. FIGURE 2-17: DC Open-Loop Gain vs.
Frequency. Load Resistance.

140 140
RL = 50 kȍ
DC Open-Loop Gain (dB)
DC Open-Loop Gain (dB)

130 130

120
120 VDD = 5.5V
110
110 VDD = 1.4V
100
100
RL = 50 kΩ 90
90 VDD = 5.0V
VOUT = 0.1V to VDD - 0.1V 80
80 0.00 0.05 0.10 0.15 0.20 0.25
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage Headroom;
Power Supply Voltage (V) VDD – VOH or VOL – VSS (V)

FIGURE 2-15: DC Open-Loop Gain vs. FIGURE 2-18: DC Open-Loop Gain vs.
Power Supply Voltage. Output Voltage Headroom.

 2019 Microchip Technology Inc. DS20001669E-page 7

MCP6041/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.

130 20 100
18 90

Gain Bandwidth Product

120 PM
16 (G = +1) 80
Channel to Channel

Phase Margin (°)

110 14 70
Separation (dB)

12 60
100

(kHz)
10 GBWP 50
90 8 40
6 30
80
4 20
VDD = 5.0V
70 2 RL = 100 kΩ 10
Input Referred
0 0
60

-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
100
1.E+02 1k
1.E+03 10k
1.E+04
Frequency (Hz) Common Mode Input Voltage

FIGURE 2-19: Channel-to-Channel FIGURE 2-22: Gain Bandwidth Product,

Separation vs. Frequency (MCP6042 and Phase Margin vs. Common-mode Input Voltage.
MCP6044 only).

18 90 18 90
16 80 16 PM 80

Gain Bandwidth Product

PM
Gain Bandwidth Product

(G = +1) (G = +1)
14 70 14 70
Phase Margin (°)

Phase Margin (°)

12 60 12 60
10 50 10 50
(kHz)
GBWP
(kHz)

GBWP
8 40 8 40
6 30 6 30
4 20 4 20
2 VDD = 1.4V 10 2 VDD = 5.5V 10
0 0 0 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)

FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with Phase Margin vs. Ambient Temperature with
VDD = 1.4V. VDD = 5.5V.

0.8 35
TA = -40°C
Output Short Circuit Current

0.7 30 TA = +25°C
TA = +85°C
0.6
Quiescent Current

Magnitude (mA)

25 TA = +125°C
(µA/Amplifier)

0.5
20
0.4
15
0.3
TA = +125°C
10
0.2 TA = +85°C
TA = +25°C 5
0.1 TA = -40°C
0.0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V) Power Supply Voltage (V)

FIGURE 2-21: Quiescent Current vs. FIGURE 2-24: Output Short Circuit Current
Power Supply Voltage. vs. Power Supply Voltage.

DS20001669E-page 8  2019 Microchip Technology Inc.

 MCP6041/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.

1000 5.0
VDD = 5.5V

VDD – V OH or V OL – V SS (mV)
VDD – V OH or V OL – V SS (mV)

4.5
Output Voltage Headroom;

Output Voltage Headroom,

RL = 50 kΩ
4.0
100 3.5 VOL – VSS
3.0
VDD – VOH
2.5
VOL – VSS 2.0 VDD – VOH
10
1.5
1.0
0.5
1 0.0
0.01 0.1 1 10 -50 -25 0 25 50 75 100 125
Output Current Magnitude (mA) Ambient Temperature (°C)

FIGURE 2-25: Output Voltage Headroom FIGURE 2-28: Output Voltage Headroom
vs. Output Current Magnitude. vs. Ambient Temperature.

5.5 10
5.0 VDD = 5.5V

Maximum Output Voltage

4.5 VDD = 5.5V
Slew Rate (V/ms)

4.0 High-to-Low

Swing (V P-P )
3.5
3.0
VDD = 1.4V
2.5 1
2.0 Low-to-High
1.5 VDD = 1.4V
1.0
0.5
0.0
0.1
-50 -25 0 25 50 75 100 125 10 100 1k 10k
1.E+01 1.E+02 1.E+03 1.E+04
Ambient Temperature (°C) Frequency (Hz)

FIGURE 2-26: Slew Rate vs. Ambient FIGURE 2-29: Maximum Output Voltage
Temperature. Swing vs. Frequency.

25 25
G = +1 V/V G = -1 V/V
20 RL = 50 kΩ 20 RL = 50 kΩ
Output Voltage (5mV/div)

15 15
Voltage (5 mV/div)

10 10
5 5
0 0
-5 -5
-10 -10
-15 -15
-20 -20
-25 -25
0.0 0.1 0.2 0.3 Time
0.4 (100
0.5 µs/div)
0.6 0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3 Time
0.4 (100
0.5 µs/div)
0.6 0.7 0.8 0.9 1.0

FIGURE 2-27: Small Signal Non-inverting FIGURE 2-30: Small Signal Inverting Pulse
Pulse Response. Response.

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MCP6041/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 1 M to VL, and CL = 60 pF.

5.0 5.0
VDD = 5.0V VDD = 5.0V
4.5 G = +1 V/V 4.5 G = -1 V/V
4.0 RL = 50 kΩ 4.0 RL = 50 kΩ

Output Voltage (V)

Output Voltage (V)

3.5 3.5
3.0 3.0
2.5 2.5
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0.0 0.0
0 1 2 3 Time
4 (15ms/div)
6 7 8 9 10 0 1 2 3 Time
4 (15ms/div)
6 7 8 9 10

FIGURE 2-31: Large Signal Non-inverting FIGURE 2-34: Large Signal Inverting Pulse
Pulse Response. Response.

7.5 5.0 3.0

CS Voltage (V)

Internal CS Switch Output (V)

VOUT Active VDD = 5.0V
5.0 4.5
2.5
2.5 CS 4.0
Output Voltage (V)

0.0 3.5 2.0

-2.5 VDD = 5.0V 3.0 CS CS
1.5 Low-to-High
-5.0 2.5 High-to-Low

-7.5 Output On
2.0 1.0
-10.0 VOUT 1.5 0.5 Hysteresis
-12.5 1.0
0.0
-15.0 High-Z High-Z 0.5 VOUT High-Z
-17.5 0.0 -0.5
-20.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0 1 2 3 Time
4 (15 ms/div)
6 7 8 9 10 CS Input Voltage (V)

FIGURE 2-32: Chip Select (CS) to FIGURE 2-35: Chip Select (CS) Hysteresis
Amplifier Output Response Time (MCP6043 (MCP6043 only).
only).

1.E-02
10m
Input Current Magnitude (A)

1m
1.E-03
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n +125°C
1.E-09
+85°C
100p
1.E-10 +25°C
10p
1.E-11 -40°C
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)

FIGURE 2-33: Input Current vs. Input

Voltage (below VSS).

DS20001669E-page 10  2019 Microchip Technology Inc.

 MCP6041/2/3/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6041 MCP6042 MCP6043 MCP6044

PDIP, PDIP, PDIP, PDIP, Symbol Description

SOIC, SOT-23-5 SOIC, SOIC, SOT-23-6 SOIC,
MSOP MSOP MSOP TSSOP
6 1 1 6 1 1 VOUT, VOUTA Analog Output (op amp A)
2 4 2 2 4 2 VIN–, VINA– Inverting Input (op amp A)
3 3 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A)
7 5 8 7 6 4 VDD Positive Power Supply
— — 5 — — 5 VINB+ Non-inverting Input (op amp B)
— — 6 — — 6 VINB– Inverting Input (op amp B)
— — 7 — — 7 VOUTB Analog Output (op amp B)
— — — — — 8 VOUTC Analog Output (op amp C)
— — — — — 9 VINC– Inverting Input (op amp C)
— — — — — 10 VINC+ Non-inverting Input (op amp C)
4 2 4 4 2 11 VSS Negative Power Supply
— — — — — 12 VIND+ Non-inverting Input (op amp D)
— — — — — 13 VIND– Inverting Input (op amp D)
— — — — — 14 VOUTD Analog Output (op amp D)
— — — 8 5 — CS Chip Select
1, 5, 8 — — 1, 5 — — NC No Internal Connection

3.1 Analog Outputs 3.4 Power Supply Pins

The output pins are low-impedance voltage sources. The positive power supply pin (VDD) is 1.4V to 6.0V
higher than the negative power supply pin (VSS). For
3.2 Analog Inputs normal operation, the other pins are at voltages
between VSS and VDD.
The non-inverting and inverting inputs are high-imped-
Typically, these parts are used in a single (positive)
ance CMOS inputs with low bias currents.
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
3.3 Chip Select Digital Input need bypass capacitors.
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.

 2019 Microchip Technology Inc. DS20001669E-page 11

MCP6041/2/3/4
NOTES:

DS20001669E-page 12  2019 Microchip Technology Inc.

 MCP6041/2/3/4
4.0 APPLICATIONS INFORMATION dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
The MCP6041/2/3/4 family of op amps is manufactured through D1 and D2.
using Microchip’s state of the art CMOS process.
These op amps are unity gain stable and suitable for a
VDD
wide range of general purpose, low-power applica-
tions.
See Microchip’s related MCP6141/2/3/4 family of op D1
amps for applications, at a gain of 10 V/V or higher,
V1 +
needing greater bandwidth.
R1 D2 MCP604X VOUT
4.1 Rail-to-Rail Input V2 –
R2
4.1.1 PHASE REVERSAL
The MCP6041/2/3/4 op amps are designed to not
R3
exhibit phase inversion when the input pins exceed the
supply voltages. Figure 2-10 shows an input voltage VSS – (minimum expected V1)
exceeding both supplies with no phase inversion. R1 >
2 mA
VSS – (minimum expected V2)
4.1.2 INPUT VOLTAGE AND CURRENT R2 >
2 mA
LIMITS
The ESD protection on the inputs can be depicted as FIGURE 4-2: Protecting the Analog
shown in Figure 4-1. This structure was chosen to Inputs.
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs It is also possible to connect the diodes to the left of the
when they try to go more than one diode drop below resistor R1 and R2. In this case, the currents through
VSS. They also clamp any voltages that go too far the diodes D1 and D2 need to be limited by some other
above VDD; their breakdown voltage is high enough to mechanism. The resistors then serve as in-rush current
allow normal operation, and low enough to bypass limiters; the DC current into the input pins (VIN+ and
quick ESD events within the specified limits. VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common-
VDD Bond mode voltage (VCM) is below ground (VSS); see
Pad Figure 2-33. Applications that are high impedance may
need to limit the useable voltage range.

4.1.3 NORMAL OPERATION

VIN+ Bond Input Bond V –
IN
Pad Stage Pad The input stage of the MCP6041/2/3/4 op amps uses
two differential input stages in parallel. One operates at
a low Common-mode input voltage (VCM), while the
other operates at a high VCM. With this topology, the
VSS Bond device operates with a VCM up to 300 mV above VDD
Pad
and 300 mV below VSS. The input offset voltage is
measured at VCM = VSS – 0.3V and VDD + 0.3V to
FIGURE 4-1: Simplified Analog Input ESD
ensure proper operation.
Structures.
There are two transitions in input behavior as VCM is
In order to prevent damage and/or improper operation changed. The first occurs, when VCM is near
of these amplifiers, the circuit must limit the currents VSS + 0.4V, and the second occurs when VCM is near
(and voltages) at the input pins (see Absolute Maxi- VDD – 0.5V (see Figure 2-3 and Figure 2-6). For the
mum Ratings † at the beginning of Section 1.0 “Elec- best distortion performance with non-inverting gains,
trical Characteristics”). Figure 4-2 shows the avoid these regions of operation.
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and

 2019 Microchip Technology Inc. DS20001669E-page 13

MCP6041/2/3/4
4.2 Rail-to-Rail Output 4.4 Capacitive Loads
There are two specifications that describe the output Driving large capacitive loads can cause stability
swing capability of the MCP6041/2/3/4 family of op problems for voltage feedback op amps. As the load
amps. The first specification (Maximum Output Voltage capacitance increases, the feedback loop’s phase
Swing) defines the absolute maximum swing that can margin decreases and the closed-loop bandwidth is
be achieved under the specified load condition. Thus, reduced. This produces gain peaking in the frequency
the output voltage swings to within 10 mV of either sup- response, with overshoot and ringing in the step
ply rail with a 50 k load to VDD/2. Figure 2-10 shows response. A unity gain buffer (G = +1) is the most
how the output voltage is limited when the input goes sensitive to capacitive loads, although all gains show
beyond the linear region of operation. the same general behavior.
The second specification that describes the output When driving large capacitive loads with these op
swing capability of these amplifiers is the Linear Output amps (e.g., > 60 pF when G = +1), a small series
Voltage Range. This specification defines the maxi- resistor at the output (RISO in Figure 4-3) improves the
mum output swing that can be achieved while the feedback loop’s phase margin (stability) by making the
amplifier still operates in its linear region. To verify output load resistive at higher frequencies. The
linear operation in this range, the large signal DC bandwidth will be generally lower than the bandwidth
Open-Loop Gain (AOL) is measured at points inside the with no capacitive load.
supply rails. The measurement must meet the specified
AOL condition in the specification table.
– RISO
4.3 Output Loads and Battery Life MCP604X VOUT
The MCP6041/2/3/4 op amp family has outstanding VIN + CL
quiescent current, which supports battery-powered
applications. There is minimal quiescent current
glitching when Chip Select (CS) is raised or lowered.
FIGURE 4-3: Output Resistor, RISO
This prevents excessive current draw, and reduced
Stabilizes Large Capacitive Loads.
battery life, when the part is turned off or on.
Heavy resistive loads at the output can cause Figure 4-4 gives recommended RISO values for
excessive battery drain. Driving a DC voltage of 2.5V different capacitive loads and gains. The x-axis is the
across a 100 k load resistor will cause the supply cur- normalized load capacitance (CL/GN), where GN is the
rent to increase by 25 µA, depleting the battery 43 circuit’s noise gain. For non-inverting gains, GN and the
times as fast as IQ (0.6 µA, typical) alone. Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
High frequency signals (fast edge rate) across
capacitive loads will also significantly increase supply
100,000
100k
current. For instance, a 0.1 µF capacitor at the output
presents an AC impedance of 15.9 k (1/2fC) to a
Recommended RISO (:)

100 Hz sinewave. It can be shown that the average

power drawn from the battery by a 5.0 Vp-p sinewave
(1.77 Vrms), under these conditions, is 10k
10,000
GN = +1
GN = +2
EQUATION 4-1: GN t +5

PSupply = (VDD - VSS) (IQ + VL(p-p) f CL )

1k
1,000
= (5V)(0.6 µA + 5.0Vp-p · 100Hz · 0.1µF) 10p
1.E+01 100p
1.E+02 1n
1.E+03 10n
1.E+04
= 3.0 µW + 50 µW Normalized Load Capacitance; C L/GN (F)

This will drain the battery 18 times as fast as IQ alone. FIGURE 4-4: Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6041/2/3/4 SPICE macro
model are helpful.

DS20001669E-page 14  2019 Microchip Technology Inc.

 MCP6041/2/3/4
4.5 MCP6043 Chip Select 4.8 PCB Surface Leakage
The MCP6043 is a single op amp with Chip Select In applications where low input bias current is critical,
(CS). When CS is pulled high, the supply current drops printed circuit board (PCB) surface leakage effects
to 50 nA (typical) and flows through the CS pin to VSS. need to be considered. Surface leakage is caused by
When this happens, the amplifier output is put into a humidity, dust or other contamination on the board.
high impedance state. By pulling CS low, the amplifier Under low humidity conditions, a typical resistance
is enabled. If the CS pin is left floating, the amplifier between nearby traces is 1012. A 5V difference would
may not operate properly. Figure 1-1 shows the output cause 5 pA of current to flow, which is greater than the
voltage and supply current response to a CS pulse. MCP6041/2/3/4 family’s bias current at +25°C (1 pA,
typical).
4.6 Supply Bypass The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
With this family of operational amplifiers, the power
ring is biased at the same voltage as the sensitive pin.
supply pin (VDD for single supply) should have a local
Figure 4-6 shows an example of this type of layout.
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide Guard Ring VIN– VIN+
large, slow currents. This bulk capacitor is not required
for most applications and can be shared with nearby
analog parts.

4.7 Unused Op Amps

An unused op amp in a quad package (MCP6044)
FIGURE 4-6: Example Guard Ring Layout
should be configured as shown in Figure 4-5. These
for Inverting Gain.
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum 1. Non-inverting Gain and Unity Gain Buffer:
noise gain. The resistor divider produces any desired a) Connect the non-inverting pin (VIN+) to the
reference voltage within the output voltage range of the input with a wire that does not touch the
op amp; the op amp buffers that reference voltage. PCB surface.
Circuit B uses the minimum number of components b) Connect the guard ring to the inverting input
and operates as a comparator, but it may draw more pin (VIN–). This biases the guard ring to the
current. Common-mode input voltage.
2. Inverting Gain and Transimpedance Gain
¼ MCP6044 (A) ¼ MCP6044 (B) (convert current to voltage, such as photo
VDD VDD detectors) amplifiers:
a) Connect the guard ring to the non-inverting
VDD input pin (VIN+). This biases the guard ring
R1
+ to the same reference voltage as the op
+ – amp (e.g., VDD/2 or ground).
VREF
R2 – b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
R2
V REF = V DD  ------------------
R1 + R2

FIGURE 4-5: Unused Op Amps.

 2019 Microchip Technology Inc. DS20001669E-page 15

MCP6041/2/3/4
4.9 Application Circuits 4.9.2 INSTRUMENTATION AMPLIFIER
The MCP6041/2/3/4 op amp is well suited for
4.9.1 BATTERY CURRENT SENSING conditioning sensor signals in battery-powered
The MCP6041/2/3/4 op amps’ Common-mode Input applications. Figure 4-8 shows a two op amp instru-
Range, which goes 0.3V beyond both supply rails, mentation amplifier, using the MCP6042, that works
supports their use in high-side and low-side battery well for applications requiring rejection of Common-
current sensing applications. The very low quiescent mode noise at higher gains. The reference voltage
current (0.6 µA, typical) helps prolong battery life, and (VREF) is supplied by a low impedance source. In single
the rail-to-rail output supports detection low currents. supply applications, VREF is typically VDD/2.
Figure 4-7 shows a high-side battery current sensor
.

circuit. The 10 resistor is sized to minimize power RG

losses. The battery current (IDD) through the 10
resistor causes its top terminal to be more negative
VREF R1 R2 R2 R1 VOUT
than the bottom terminal. This keeps the Common-
mode input voltage of the op amp below VDD, which is
within its allowed range. The output of the op amp will
also be below VDD, which is within its Maximum Output V2
Voltage Swing specification. ½ ½
MCP6042 MCP6042
.
V1
IDD VDD
1.4V R 1 2R 1
10 V OUT =  V 1 – V 2   1 + ------ + --------- + V REF
to R2 RG
VOUT
6.0V
100 k MCP604X
FIGURE 4-8: Two Op Amp
Instrumentation Amplifier.
1 M

V DD – V OUT
I DD = ------------------------------------------
 10 V/V    10  

FIGURE 4-7: High-Side Battery Current

Sensor.

DS20001669E-page 16  2019 Microchip Technology Inc.

 MCP6041/2/3/4
5.0 DESIGN AIDS 5.4 Analog Demonstration and
Evaluation Boards
Microchip provides the basic design tools needed for
the MCP6041/2/3/4 family of op amps. Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
5.1 SPICE Macro Model designed to help you achieve faster time to market. For
a complete listing of these boards and their
The latest SPICE macro model for the MCP6041/2/3/4 corresponding user’s guides and technical information,
op amps is available on the Microchip web site at visit the Microchip web site at www.microchip.com/
www.microchip.com. This model is intended to be an analogtools.
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See Some boards that are especially useful are:
the model file for information on its capabilities. • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Bench testing is a very important part of any design and Evaluation Board
cannot be replaced with simulations. Also, simulation • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evalu-
results using this macro model need to be validated by ation Board
comparing them to the data sheet specifications and • MCP6XXX Amplifier Evaluation Board 1
characteristic curves. • MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
5.2 FilterLab® Software • MCP6XXX Amplifier Evaluation Board 4
Microchip’s FilterLab® software is an innovative • Active Filter Demo Board Kit
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the 5.5 Application Notes
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams The following Microchip Application Notes are avail-
of the filter circuit with component values. It also able on the Microchip web site at www.microchip.com/
outputs the filter circuit in SPICE format, which can be appnotes and are recommended as supplemental ref-
used with the macro model to simulate actual filter erence resources:
performance. ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits,” DS21821
5.3 MAPS (Microchip Advanced Part AN722: “Operational Amplifier Topologies and DC
Selector) Specifications,” DS00722
MAPS is a software tool that helps semiconductor AN723: “Operational Amplifier AC Specifications and
professionals efficiently identify Microchip devices that Applications,” DS00723
fit a particular design requirement. Available at no cost AN884: “Driving Capacitive Loads With Op Amps,”
from the Microchip website at www.microchip.com/ DS00884
maps, the MAPS is an overall selection tool for
AN990: “Analog Sensor Conditioning Circuits – An
Microchip’s product portfolio that includes Analog,
Overview,” DS00990
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of These application notes and others are listed in the
devices and export side-by-side technical comparison design guide:
reports. Helpful links are also provided for data sheets, “Signal Chain Design Guide,” DS21825
purchase, and sampling of Microchip parts.

 2019 Microchip Technology Inc. DS20001669E-page 17

MCP6041/2/3/4
NOTES:

DS20001669E-page 18  2019 Microchip Technology Inc.

 MCP6041/2/3/4
6.0 PACKAGING INFORMATION

6.1 Package Marking Information

5-Lead SOT-23 (MCP6041) Example:

I-Temp E-Temp
Device
Code Code
XXNN MCP6041/T-E/OT SPNN 7XNN 7X25
Note: Parts with date codes prior to
November 2012 have their package
markings in the SBNN format.

6-Lead SOT-23 (MCP6043) Example:

I-Temp E-Temp
Device
Code Code
XXNN MCP6043T-E/CH SCNN SDNN SC25

8-Lead MSOP Example:

6043I
931256

8-Lead PDIP (300 mil) Example:

XXXXXXXX MCP6041 MCP6041

XXXXXNNN I/P256 OR I/P e3256
YYWW 1931 1931

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
e3
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2019 Microchip Technology Inc. DS20001669E-page 19

MCP6041/2/3/4
Package Marking Information (Continued)

8-Lead SOIC (150 mil) Example:

XXXXXXXX MCP6042 MCP6042I

XXXXYYWW I/SN1931 OR SN e3 1931
NNN 256 256

14-Lead PDIP (300 mil) (MCP6044) Example:

XXXXXXXXXXXXXX MCP6044-I/P
XXXXXXXXXXXXXX
YYWWNNN 1931256

MCP6044
OR E/P e3
1931256

14-Lead SOIC (150 mil) (MCP6044) Example:

XXXXXXXXXX MCP6044ISL
XXXXXXXXXX I/SL^^
e3
YYWWNNN 1931256

MCP6044
OR E/SL^^
e3
1931256

DS20001669E-page 20  2019 Microchip Technology Inc.

 MCP6041/2/3/4
Package Marking Information (Continued)

14-Lead TSSOP (MCP6044) Example:

XXXXXXXX 6044ST
YYWW 1931
NNN 256

6044EST
OR
1931
256

 2019 Microchip Technology Inc. DS20001669E-page 21

MCP6041/2/3/4

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

0.20 C 2X
D

e1
A D

E/2
E1/2

E1 E
(DATUM D)
(DATUM A-B)

0.15 C D
2X
NOTE 1 1 2

B NX b
0.20 C A-B D

TOP VIEW

A A2
0.20 C

SEATING PLANE
A
SEE SHEET 2 A1 C

SIDE VIEW

Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2

DS20001669E-page 22  2019 Microchip Technology Inc.

 MCP6041/2/3/4

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

T
L
L1

VIEW A-A
SHEET 1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e 0.95 BSC
Outside lead pitch e1 1.90 BSC
Overall Height A 0.90 - 1.45
Molded Package Thickness A2 0.89 - 1.30
Standoff A1 - - 0.15
Overall Width E 2.80 BSC
Molded Package Width E1 1.60 BSC
Overall Length D 2.90 BSC
Foot Length L 0.30 - 0.60
Footprint L1 0.60 REF
Foot Angle I 0° - 10°
Lead Thickness c 0.08 - 0.26
Lead Width b 0.20 - 0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2

 2019 Microchip Technology Inc. DS20001669E-page 23

MCP6041/2/3/4

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

5 SILK SCREEN

Z C G

1 2

E
GX

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.95 BSC
Contact Pad Spacing C 2.80
Contact Pad Width (X5) X 0.60
Contact Pad Length (X5) Y 1.10
Distance Between Pads G 1.70
Distance Between Pads GX 0.35
Overall Width Z 3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091B [OT]

DS20001669E-page 24  2019 Microchip Technology Inc.

 MCP6041/2/3/4

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2X
0.15 C A-B
D
e1
A D

E
2

E1 E
E1
2

2X
0.15 C D
2X
0.20 C A-B
e
B 6X b
0.20 C A-B D

TOP VIEW

A A2
C
SEATING PLANE
6X
A1 0.10 C
SIDE VIEW

R1
R L2
c
GAUGE PLANE

L Ĭ
(L1)
END VIEW
Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2

 2019 Microchip Technology Inc. DS20001669E-page 25

MCP6041/2/3/4

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 6
Pitch e 0.95 BSC
Outside lead pitch e1 1.90 BSC
Overall Height A 0.90 - 1.45
Molded Package Thickness A2 0.89 1.15 1.30
Standoff A1 0.00 - 0.15
Overall Width E 2.80 BSC
Molded Package Width E1 1.60 BSC
Overall Length D 2.90 BSC
Foot Length L 0.30 0.45 0.60
Footprint L1 0.60 REF
Seating Plane to Gauge Plane L1 0.25 BSC
Foot Angle φ 0° - 10°
Lead Thickness c 0.08 - 0.26
Lead Width b 0.20 - 0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2

DS20001669E-page 26  2019 Microchip Technology Inc.

 MCP6041/2/3/4

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

GX

Z C G G

SILK SCREEN

X
E

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.95 BSC
Contact Pad Spacing C 2.80
Contact Pad Width (X3) X 0.60
Contact Pad Length (X3) Y 1.10
Distance Between Pads G 1.70
Distance Between Pads GX 0.35
Overall Width Z 3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2028B (CH)

 2019 Microchip Technology Inc. DS20001669E-page 27

MCP6041/2/3/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001669E-page 28  2019 Microchip Technology Inc.

 MCP6041/2/3/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001669E-page 29

MCP6041/2/3/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001669E-page 30  2019 Microchip Technology Inc.

 MCP6041/2/3/4

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D A
N B

E1

NOTE 1
1 2
TOP VIEW

C A A2

PLANE
L c
A1

e eB
8X b1
8X b
.010 C

SIDE VIEW END VIEW

Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2

 2019 Microchip Technology Inc. DS20001669E-page 31

MCP6041/2/3/4

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

ALTERNATE LEAD DESIGN

(NOTE 5)

DATUM A DATUM A

b b
e e
2 2

e e

Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.

Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2

DS20001669E-page 32  2019 Microchip Technology Inc.

 MCP6041/2/3/4

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2X
0.10 C A–B
D
A D
NOTE 5
N

E
2
E1
2

E1 E

NOTE 1 1 2

e NX b
B 0.25 C A–B D
NOTE 5
TOP VIEW
0.10 C

C A A2
SEATING
PLANE 8X
0.10 C
A1 SIDE VIEW

h
R0.13
h
R0.13
H 0.23

L
SEE VIEW C
(L1)
VIEW A–A

VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2

 2019 Microchip Technology Inc. DS20001669E-page 33

MCP6041/2/3/4

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Foot Angle 0° - 8°
Lead Thickness c 0.17 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2

DS20001669E-page 34  2019 Microchip Technology Inc.

 MCP6041/2/3/4

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

SILK SCREEN

Y1

X1
E

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X8) X1 0.60
Contact Pad Length (X8) Y1 1.55

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2057-SN Rev E

 2019 Microchip Technology Inc. DS20001669E-page 35

MCP6041/2/3/4

             

  =  $ >    $   %$ > $     
$;??$?$ > 

NOTE 1
E1

1 2 3

A A2

L c

A1
b1

b e eB

@ GJK#
" Q %GJ JU% %+Y
J  J *
  &&9
<$   + Z Z &
%   > <> + 7 !& [7
9    + &7 Z Z
  \  # [& !& !7
%   > \  # *& 7& ]&
U Q " ^!7 ^7& ^^7
<$   Q 7 !& 7&
Q <>  &&] && &7
@$$Q \   &*7 &_& &^&
QQ \   &* &] &
U `$  9 Z Z *!&
 
                
     
! "  "  #    $  %  $     &&'$  
* "     $+%#3*7%
9;9 " <        

%$ <  "  &*j&&79

DS20001669E-page 36  2019 Microchip Technology Inc.

 MCP6041/2/3/4

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2X
0.10 C A–B
D
A NOTE 5 D
N

E
2
E2
2

E1 E

2X
0.10 C D
2X N/2 TIPS
NOTE 1 1 2 3 0.20 C
e NX b
B NOTE 5 0.25 C A–B D

TOP VIEW

0.10 C

C A A2
SEATING
PLANE 14X
A1 SIDE VIEW 0.10 C

h h

H R0.13
R0.13

SEE VIEW C
L
VIEW A–A (L1)

VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2

 2019 Microchip Technology Inc. DS20001669E-page 37

MCP6041/2/3/4

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Lead Angle 0° - -
Foot Angle 0° - 8°
Lead Thickness c 0.10 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2

DS20001669E-page 38  2019 Microchip Technology Inc.

 MCP6041/2/3/4

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

14

SILK SCREEN

1 2
X
E

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X14) X 0.60
Contact Pad Length (X14) Y 1.55

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2065-SL Rev D

 2019 Microchip Technology Inc. DS20001669E-page 39

MCP6041/2/3/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001669E-page 40  2019 Microchip Technology Inc.

 MCP6041/2/3/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001669E-page 41

MCP6041/2/3/4

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001669E-page 42  2019 Microchip Technology Inc.

 MCP6041/2/3/4
APPENDIX A: REVISION HISTORY

Revision E (November 2019)

The following is the list of modifications:
1. Updated Section 6.0 “Packaging Informa-
tion”.

Revision D (March 2013)

The following is the list of modifications:
1. Updated the boards list in Section 5.4 “Analog
Demonstration and Evaluation Boards”.
2. Removed the Mindi™ Circuit Designer &
Simulator section.
3. Updated the E-Temp Code value for the 5-Lead
SOT-23 package in Section 6.0 “Packaging
Information”.

Revision C (February 2008)

The following is the list of modifications:
1. Updated Figure 2-4 and Figure 2-5.
2. Updated trademark and Sales listing pages.
3. Expanded this op amp family:
4. Added the SOT-23-6 package for the MCP6043
op amp with Chip Select.
5. Added Extended Temperature (-40°C to
+125°C) parts.
6. Expanded Analog Input Absolute Max Voltage
Range (applies retroactively).
7. Expanded operating VDD to a maximum of 6.0V.
8. Section 1.0 “Electrical Characteristics”
updated.
9. Section 2.0 “Typical Performance Curves”
updated.
10. Section 3.0 “Pin Descriptions” added.
11. Section 4.0 “Applications Information” added.
12. Added Section 4.7 “Unused Op Amps”.
13. Updated input stage explanation.
14. Section 5.0 “Design Aids” updated.
15. Section 6.0 “Packaging Information” updated.
16. Added SOT-23-6 package.
17. Corrected package marking information.
18. Appendix A: “Revision History” added.

Revision B (June 2002)

The following is the list of modifications.
• Undocumented changes.

Revision A (August 2001)

• Original data sheet release.

 2019 Microchip Technology Inc. DS20001669E-page 39

MCP6041/2/3/4
NOTES:

DS20001669E-page 40  2019 Microchip Technology Inc.

 MCP6041/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX Examples:

a) MCP6041-I/P: Industrial Temperature,
Device Temperature Package 8LD PDIP package.
Range b) MCP6041T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
Device: MCP6041: Single Op Amp a) MCP6042-I/SN: Industrial Temperature,
MCP6041T Single Op Amp 8LD SOIC package.
(Tape and Reel for SOT-23, SOIC, MSOP)
b) MCP6042T-E/MS: Tape and Reel,
MCP6042 Dual Op Amp
Extended Temperature,
MCP6042T Dual Op Amp
8LD MSOP package.
(Tape and Reel for SOIC and MSOP)
MCP6043 Single Op Amp w/ Chip Select a) MCP6043-I/P: Industrial Temperature,
MCP6043T Single Op Amp w/ Chip Select 8LD PDIP package.
(Tape and Reel for SOT-23, SOIC, MSOP)
b) MCP6043T-E/CH: Tape and Reel,
MCP6044 Quad Op Amp
Extended Temperature,
MCP6044T Quad Op Amp
6LD SOT-23 package.
(Tape and Reel for SOIC and TSSOP)
a) MCP6044-I/SL: Industrial Temperature,
14LD SOIC package.
Temperature Range: I = -40°C to +85°C
b) MCP6044T-E/ST: Tape and Reel,
E = -40°C to +125°C
Extended Temperature,
14LD TSSOP package.
Package: CH = Plastic Small Outline Transistor (SOT-23),
6-lead (Tape and Reel - MCP6043 only)
MS = Plastic Micro Small Outline (MSOP), 8-lead
OT = Plastic Small Outline Transistor (SOT-23),
5-lead (Tape and Reel - MCP6041 only)
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SL = Plastic SOIC (150 mil Body), 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
ST = Plastic TSSOP (4.4 mm Body), 14-lead

 2019 Microchip Technology Inc. DS20001669E-page 41

MCP6041/2/3/4
NOTES:

DS20001669E-page 42  2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec,
and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in
FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries.
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company,
the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.

© 2019, Microchip Technology Incorporated, All Rights Reserved.

For information regarding Microchip’s Quality Management Systems, ISBN: 978-1-5224-5306-2

please visit www.microchip.com/quality.

 2019 Microchip Technology Inc. DS20001669E-page 43

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Australia - Sydney India - Bangalore Austria - Wels
2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
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Technical Support: Fax: 45-4485-2829
Tel: 86-28-8665-5511 Tel: 91-20-4121-0141
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China - Chongqing Japan - Osaka Finland - Espoo
support
Tel: 86-23-8980-9588 Tel: 81-6-6152-7160 Tel: 358-9-4520-820
Web Address:
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Houston, TX Tel: 39-049-7625286
Tel: 281-894-5983 China - Xian Vietnam - Ho Chi Minh
Tel: 86-29-8833-7252 Tel: 84-28-5448-2100 Netherlands - Drunen
Indianapolis Tel: 31-416-690399
Noblesville, IN China - Xiamen Fax: 31-416-690340
Tel: 86-592-2388138
Tel: 317-773-8323 Norway - Trondheim
Fax: 317-773-5453 China - Zhuhai Tel: 47-7288-4388
Tel: 317-536-2380 Tel: 86-756-3210040
Poland - Warsaw
Los Angeles Tel: 48-22-3325737
Mission Viejo, CA
Romania - Bucharest
Tel: 949-462-9523 Tel: 40-21-407-87-50
Fax: 949-462-9608
Tel: 951-273-7800 Spain - Madrid
Tel: 34-91-708-08-90
Raleigh, NC Fax: 34-91-708-08-91
Tel: 919-844-7510
Sweden - Gothenberg
New York, NY Tel: 46-31-704-60-40
Tel: 631-435-6000
Sweden - Stockholm
San Jose, CA Tel: 46-8-5090-4654
Tel: 408-735-9110
Tel: 408-436-4270 UK - Wokingham
Tel: 44-118-921-5800
Canada - Toronto Fax: 44-118-921-5820
Tel: 905-695-1980
Fax: 905-695-2078

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05/14/19