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Digital Systems: from bits to microcontrollers
Introduction to digital systems fundamentals
Combinatorial digital systems
Sequential digital systems
Introduction to microcontrollers
Introduction to advanced implementation platforms
Characterisation of a Digital (control) System
• When outputs depend on
inputs at one specific instant
Combinatorial circuits
Black box model: A model whose inputs, outputs, • When outputs depend on the
and functional performance are known, but whose evolution over time of inputs
internal implementation is unknown or irrelevant. [1]
Sequential circuits
[1] "IEEE Standard Computer Dictionary: A Compilation of IEEE Standard Computer Glossaries," in IEEE Std 610 , pp.1-217, 18 Jan. 1991, doi:
10.1109/IEEESTD.1991.106963
2
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Introducing state variables (internal
state)
x Combinatorial f(x)
circuit
x Sequential f(x,Y)
Output depends on current inputs circuit
Output depends on current inputs and internal state
(which in turn depends on history of inputs)
Introducing feedback in logic elements…
Connecting output to input
1 0 0 1
0 1 1 0
Two stable states can be observed
Problem: how to impose a specific state?
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Introducing inputs
R
Q
R
S S
/Q
/Q
Initial state of outputs
Introducing inputs
R
Q
R
S S
/Q
Q
Input R (reset) forces output Q to go 0;
Input S (set) forces output Q to go 1; /Q
Outputs Q and /Q present
complementary values
Initial state of outputs
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Introducing inputs
R
Q
R
S S
/Q
/S Q
Q
/Q
/R
/Q
Introducing inputs
R
Q
R
S S
/Q
S /S Q
Q
/Q
R /R /Q
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SR Latch
R
Q
S R Qt Qt+ /Qt+
R
0 0 0 0 1
0 0 1 1 0
S S
/Q 0 1 0 0 1
0 1 1 0 1
S /S Q
Q 1 0 0 1 0
1 0 1 1 0 /Q
1 1 0 x x
R /R 1 1 1 x x
/Q
Qt+ S
SR Latch 0 0 X 1
Qt+ = S + /[Link] = /(/S . /(/[Link])) Qt 1 0 X 1
Qt+ = /R . (S+Qt) = /(R + /(S+Qt)) R S
R Qt+
Q
S R Qt Qt+ /Qt+ 0 0 X 1
0 0 0 0 1
0 0 1 1 0 Qt 1 0 X 1
S
/Q 0 1 0 0 1 R
0 1 1 0 1 S R Qt+ /Qt+
S /S Q 1 0 0 1 0 0 0 Qt /Qt
1 0 1 1 0 0 1 0 1
1 1 0 x x 1 0 1 0
R /R 1 1 1 x x 1 1 x x
/Q
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SR Latch with enable (gated SR latch)
S
S /S Q /S Q
EN S R Qt+ /Qt+
0 - - Qt /Qt
EN 1 0 0 Qt /Qt
1 0 1 0 1
R /R /Q /R /Q
R 1 1 0 1 0
1 1 1 x x
S R Qt+ /Qt+
0 0 Qt /Qt
0 1 0 1
1 0 1 0
1 1 x x
Delay (D) Latch with enable
D S
/S Q EN D Qt+ /Qt+
EN 0 - Qt /Qt
1 0 0 1
/R /Q
1 1 1 0
R
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Introducing master-slave flip-flop
MASTER SLAVE new data into the master
S S S
/S Q /S Q Q CLK
EN EN
input gates disable
/R /Q /R /Q /Q
R R R
data moved from the
master to the slave
CLK
Introducing master-slave flip-flop
MASTER
SR truth table
SLAVE
S
S R Qn+1 /Qn+1
Q
0 0 Qn /Qn
0 1 0 1
1 0 1 0
R /Q 1 1 x x
CLK
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Introducing master-slave JK flip-flop
MASTER
JK truth table
SLAVE
J
J K Qn+1 /Qn+1
(S) Q
0 0 Qn /Qn
0 1 0 1
1 0 1 0
K (R) /Q 1 1 /Qn Qn
CLK
Master-slave versus edge-trigerred
flip-flops
While:
• master-slave flip-flop are receptive to inputs during one level of the clock and updates
output in one edge of the clock,
• edge-trigerred flip-flops are receptive to inputs in the same clock edge where output are
updated.
In this sense, the edge-trigerred flip-flop truth table applies considering the inputs at the
moment immediatly before the clock edge.
Edge-trigerred flip-flops are the ones normally used.
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Most common flip-flops
Q J Q Q
D T
/Q K /Q /Q
CLK CLK CLK
J K Qn+1
D Qn+1 0 0 Qn T Qn+1
0 0 0 1 0 0 Qn
1 1 1 0 1 1 /Qn
1 1 /Qn
Asynchronous versus synchronous inputs
Synchronous inputs: whenever the CLOCK event occurs, the flip-flop output is governed by
the truth table associated with synchronous inputs.
Asynchronous inputs: they will affect the flip-flop output independently of the CLOCK event.
Asynchronous
inputs { Set / Preset
Reset / Clear
Synchronous
inputs
{ D
JK
T
Synchronizing input enable CE
Q
/Q
Outputs
Synchronizing input CLK
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Asynchronous versus synchronous inputs
Synchronous inputs: normally used to impose a desired behavior over time.
Asynchronous inputs: normally used to force initial state.
Asynchronous
inputs { Set / Preset
Reset / Clear
Synchronous
inputs
{
Synchronizing input enable CE
D
JK
T
Q
/Q
Outputs
Synchronizing input CLK
Asynchronous inputs: active values
Set /Set
Reset /Reset
J Q J Q
Outputs Outputs
K /Q K /Q
CLK CLK
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May I use one flip-flop to produce a different
one?
Q J Q Q
D T
/Q K /Q /Q
CLK CLK CLK
J K Qn+1
D Qn+1 0 0 Qn T Qn+1
0 0 0 1 0 0 Qn
1 1 1 0 1 1 /Qn
1 1 /Qn
May I use one D flip-flop to produce a JK flip-
flop?
J
K ? D
Q
/Q
CLK
J K Qn+1
0 0 Qn D Qn+1
0 1 0 0 0
1 0 1 1 1
1 1 /Qn
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May I use one D flip-flop to produce a JK flip-
flop?
J K Qn Qn+1
0 0 0 0
0
0
0
1
1
0
1
0
J
K ? D
Q
/Q
0 1 1 0
1 0 0 1 CLK
1 0 1 1 J K Qn+1
1 1 0 1 0 0 Qn D Qn+1
1 1 1 0 0 1 0 0 0
1 0 1 1 1
1 1 /Qn
May I use one D flip-flop to produce a JK flip-
flop?
J K Qn Qn+1 D
0 0 0 0 0
0
0
0
1
1
0
1
0
1
0
J
K ? D
Q
/Q
0 1 1 0 0
1 0 0 1 1 CLK
1 0 1 1 1 Qn Qn+1 D
1 1 0 1 1 0 0 0 D Qn+1
1 1 1 0 0 0 1 1 0 0
1 0 0 1 1
1 1 1
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May I use one D flip-flop to produce a JK flip-
flop?
J K Qn Qn+1 D
0 0 0 0 0
0
0
0
1
1
0
1
0
1
0
J
K ? D
Q
/Q
0 1 1 0 0
1 0 0 1 1 J CLK
1 0 1 1 1
1 1 0 1 1 0 0 1 1
1 1 1 0 0 Qn 1 0 0 1 D = J./Qn + /[Link]
K
Flip-flop truth tables and transition tables
Q J Q Q
D T
/Q K /Q /Q
CLK CLK CLK
Qn Qn+1 D Qn Qn+1 T
J K Qn+1 Qn Qn+1 J K
D Qn+1 0 0 0 0 0 0
0 0 Qn 0 0 0 x T Qn+1
0 0 0 1 1 0 1 1
0 1 0 0 1 1 x 0 Qn
1 1 1 0 0 1 0 1
1 0 1 1 0 x 1 1 /Qn
1 1 1 1 1 0
1 1 /Qn 1 1 x 0
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Connecting flip-flops into registers
• A group of flip-flops using the same synchronizing signal is a register.
D0 Q0 Q1 D2 Q2
Q D1 Q Q
D D D
/Q /Q /Q
CLK
JA QA JB QB JC QC
J Q J Q J Q
KA K /Q KB K /Q KC K /Q
CLK
A shift-register
CLK
D0 1 0 0 1 1
D Qn+1 Q0=D1 0 1 0 0 1 1
0 0
1 1 Q1=D2 0 0 1 0 0 1
Q2 0 0 0 1 0 0
D0 Q0 D1 Q1 D2 Q2
Q Q Q
D D D
/Q /Q /Q
CLK
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Left and right shift-registers
Din Q0 D1 Q1 D2 Q2
Q Q Q
D D D
Right /Q /Q /Q
CLK
Din
D0 Q0 D1 Q1 D2 Q2
Left
Q Q Q
D D D
/Q /Q /Q
CLK
Left-right shift-register
SEL
Din
Q0 Q1 D2 Q2
0 D0 Q
0 D1 Q 0
Q
MUX
MUX
MUX
D 1
D D
1 1
/Q /Q /Q
CLK
If (SEL = 0) then shift left
else shift right
