Computers and Electrical Engineering 85 (2020) 106658

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Computers and Electrical Engineering

journal homepage: www.elsevier.com/locate/compeleceng

Power-efficient implementation of pseudo-random number

generator using quantum dot cellular automata-based D Flip
FlopR
S. Senthilnathan a,b, S. Kumaravel a,∗
a
Department of Micro and Nano Electronics, School of Electronics Engineering, Vellore Institute of Technology, Vellore, Tamilnadu, India
b
Department of Electronics and Communication Engineering, A.V.C College of Engineering, Mayiladuthurai, Tamilnadu, India

a r t i c l e i n f o a b s t r a c t

Article history: In secured communication, pseudo-random number generators (PRNGs) are widely used to
Received 14 November 2019 generate random sequences. This paper presents a novel D flip flop and standard EX-NOR
Revised 5 April 2020
gate to realize a Quantum dot Cellular Automata (QCA) based PRNG. For the purpose of
Accepted 6 April 2020
comparison, QCA based PRNG is implemented with existing D flip flops. The proposed D
flip flop comprises a cell count of 24 with area of 0.02 μm2 and delay of 0.05 ps, total
Keywords: power dissipation for D flip flop is 40.30 meV, 49.76 meV and 61.90 meV for different
Complementary Metal Oxide tunneling energy level of 0.5 Ek , 1.0 Ek and 1.5 Ek, respectively at temperature of 2 Kelvin.
Semi-Conductor (CMOS) The implemented PRNG configurations are simulated using QCA Designer tool for area and
Quantum dot Cellular Automata (QCA) delay. Power dissipation of D flip flop is analyzed using QCA Pro simulator tool. From the
Pseudo-Random Number Generator (PRNG) simulated results, it may be noted that PRNG with novel D flip flop realization achieves
Flip flop
low power, low area and less delay compared to other PRNG realization.
Polarization
Power dissipation © 2020 Elsevier Ltd. All rights reserved.

1. Introduction

Nowadays, random number generator (RNG) play an essential role in different applications like cryptography, statistical
sampling and network communication [1]. RNG is typically realized in two modes: namely software and hardware. Software-
based RNG does not rely on sources of naturally occurring entropy, though, it may be occasionally seeded by natural sources
and its output sequence can be predetermined by a precise algorithm. Whereas, hardware RNG brings forth random num-
bers with an unspecified occurrence period without any predefined algorithm. Usually, pseudo-random number generators
(PRNGs) are deterministic in fact and their output occur periodically, nevertheless, the period of occurrence is enormous.
A period of 219937 −1 is the most typical variant of the PRNG. Pseudo RNG design is broadly implemented to generate the
numbers which are random through linear feedback shift register (LFSR) with an EX-OR gate configuration. Despite the
widespread adoption of a conventional CMOS-based PRNG, it provides a predefined algorithm that predicts the generated
number sequence [2]. Moreover, in current CMOS-based architectures, performance of various circuits is assumed to be close
to reach the physical scalability limits, leakage power consumption, and short channel effects. Therefore, conventional CMOS
based PRNG is to be replaced by a QCA based PRNG to render an unpredictable number for every instance using Coulomb
theory [3]. QCA PRNG has several advantages. First, the source of this random number occurs naturally [4], Second, QCA has

R
This paper is for regular issues of CAEE. Reviews processed and recommended for publication to the Editor-in-Chief by Associate Editor Dr. S. Smys.
∗
Corresponding author:
E-mail addresses: [email protected] (S. Senthilnathan), [email protected] (S. Kumaravel).

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2 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658

Fig. 1. A basic 4 dot QCA cell.

the potential to develop high-speed as well as low-latency circuits [5-7] and finally, it occupies very less area and power [8].
Flip flops are the key components of the sequential circuit design. For sequential circuits, storage in QCA follows a memory-
in-motion paradigm, i.e. the state of a memory must be kept in movement in the QCA cells. Two key methods namely line
based [9] and loop based [10-12] techniques are adopted for designing QCA based flip flop. The loop-based design in QCA
technology has less uncertainty when compared to the line-based design. One of the most important parts of sequential cir-
cuit design is the D flip flop. Previously designed levels-sensitive D flip flop models in [11,13,14] are examined in this paper.
The line-based technique is used for realizing the level-sensitive D flip flop by level-sensitive paradigm in [11]. In [13,14] D
flip flop is realized by loop based technique. These entire flip flops suffer from area, delay and dissipation of power. In this
paper, a novel loop-based D flip-flop is introduced in order to minimize the area, latency and power dissipation. In turn, to
justify the efficacy of proposed D flip flop, QCA based PRNG is realized with conventional EX-NOR configuration. Due to its
reduced number of cells, power dissipation of D flip flop is also reduced [8].
In section 2 the basic concepts of QCA are discussed. Existing design of D flip flops is presented in section 3. Novel D flip
flop configuration is presented and simulated with power dissipation analysis in section 4. Section 5 inspects the proposed
QCA based PRNG configuration and compares them with the design of existing D flip flop configuration. The conclusion is
addressed in Section 6.

2. Preface to Quantum dot Cellular Automata

Quantum dot Cellular Automata (QCA) works on the principle of quantum theory which reflects itself in the form of
Columbic interaction between the extra electrons present in the four dots as depicted in Fig. 1 [15]. The dots hold the elec-
trons and tunnels inside the cell, whereas, tunneling does not happen between the two different cells. In QCA cells, binary
information is coded as given in Fig. 1. A negative polarization indicates a binary zero value while a positive polarization
denotes a binary one value in the cell. Polarization defines the polarity of the cell dictated by the alignment of the quantum
dots inside the square cell with respect to the other non-mobile dots [16]. Overall Polarization (P) is defined as described
in expression (1). P1 , P2 , P3 and P4 are the polarization values of the electrons present in the quantum dots of QCA cell.
Equation (1) shows the calculation of polarization of a QCA cell. Here Pi is the charge of the ith quantum-dot (Pi = 1 if an
electron is present, otherwise it is 0). These polarizations are represented by logic ‘0’ and logic ‘1’ (in other words, binary 0
and binary 1)

( P1 + P3 ) − ( P2 + P4 )
Polarization (P ) = (1)
( P1 + P2 ) + ( P2 + P4 )
Another significant characteristic of QCA is clocking. In order to function properly, functional QCA circuits need to be
clocked. Clocking is achieved in QCA by using two methods. One is switching abruptly and the other is switching adia-
batically [17]. Under abrupt switching, the QCA circuit input is drastically changed and the circuit goes to excited state.
Consequently, by dissipating energy to the environment, the QCA circuit hits the ground state which leads to a metastable
state of the QCA circuit. This could be verified by the local ground state and the speed of transmission being high, since,
clocking releases a cell after four phases. Hence, adiabatic switching is given the foremost priority and the system is contin-
uously maintained in its immediate ground state. Adiabatic switching is ensured by an introduction of a clock signal [17].
In QCA, the tunnelling barrier between the dots can be increased or decreased by applying clock signal to the cells, which
are generated through an electric field [18]. In accordance, four difference clocking phases are defined in QCA as illustrated
in Fig. 2. They are release, relax, switch and hold phases. Clocking is primarily achieved with the help of polarization states
of the electrons in the cells. QCA clocking regulates the data flow and serves as a power supply as well [19].
Using the basic concepts elaborated above and with the knowledge of appropriate choice of clocking schemes, a number
of simple logic gates could be implemented using QCA. Simple OR and AND implementations are illustrated in Fig. 3 using
majority gates which contain three inputs.
 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658 3

Fig. 2. Clocking phases in QCA technology.

Fig. 3. (a) Majority gate with three inputs (MG), (b) MG AND gate and (c) MG OR gate.

As depicted in Fig. 3, the majority gate in QCA technology’s fundamental logic device consists of an output, three inputs
as A, B, and C and a central logic cell. The majority gate’s overall functionality [20] is given in equation (2).
M(A, B, C) = AB + BC + CA (2)
If A, B and C are inputs to the majority gate, then the output is given by the equation (2). By setting one input (C) to 0,
the majority gate acts as an AND gate. In other words, M (A, B, 0) = AB. Similarly, by setting one of the three inputs to 1,
the majority gate functions as an OR gate M (A, B, 1) = A + B.
QCA wires are classified into two configurations based on the orientation of the dots presented in the QCA cell. If the
orientation of the dots in the QCA cell is 90°, it is termed as normal wire. If the orientation is 45°, it is termed as rotated
wire [21]. Based on the orientation pattern the wire configurations are shown in Fig. 4.

3. QCA Based D Flip Flops

Implementation of sequential circuits in QCA design helps to achieve additional features including maximum speed, re-
liability and lower power consumption [8]. However, complications in respect to architecture and synchronous mechanisms
draw attention for QCA sequential circuits in literature. Using the inherent capabilities of QCA, two primary techniques, line-
based [9] and loop-based designs [10–12] are commonly used to render the D flip flops. Data storage is carried out using
three different clock zone wires in a line based system, though, data storage in the loop based approach is done using a
loop of four different clocking zones, which is less complicated compared to the line-based design. In this section, for sake
of clarity, the QCA based D flip flop design in the literature [11,13,14] is presented below. Since the D flip flop has single
4 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658

Fig. 4. Illustration of (a) normal wire (b) rotated wire.

Fig. 5. (a) Logical representation of D flip-flop, (b) majority gate design of D flip-flop.

Table 1
D Flip-Flop’s Truth Table.

Input Output State

Clock D Q

0 0 Q(t - 1) No Change
0 1 Q(t - 1) No Change
1 0 0 Follows input
1 1 1 Follows input

input, which helps to reduce the area by huge margin for complex architecture like PRNG. Fig. 5(a) illustrates the logical
representation of D flip flop and Fig. 5(b) shows majority gate representation of D flip-flop, that has two inputs Din and
Clock and an output (Q). The characteristic equation Q(t+ 1) = D gives the logical properties of a D flip-flop indicating the
present state value of D flip-flop input appears as the next state at the output. The operation of D-flip flop is displayed in
Table 1.

3.1. Existing design of D flip-flop

The line-based D flip-flop model output in [11] is level sensitive to the clock input. In three input majority gate layout,
three distinct clocking zones are often used, the input signal wires are represented by the first clocking zone, the output
is generated by middle QCA cells held in the second clocking area, and the third clocking zone comprises output wires.
To optimize the QCA D flip flop design, coplanar wire crossing scheme is adopted. However, implementation of sequential
circuits using this technique increases complexity because of timing and synchronization constraints [12]. The design of
QCA layout is depicted in Fig. 6. Whereas, in [13] QCA D flip-flop design based on the 2 × 1 multiplexer implies the loop
based structure as depicted in Fig. 7. In using loop based architecture, the number of QCA cells presented in this design is
high, due to its design configuration. The implementation of loop based D flip flop design in [14] is executed by employing
 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658 5

Fig. 6. D-flip flop design I [11].

Fig. 7. D-flip flop design II [13].

90° QCA cells with no sort of crossover wire. The requirement of the design involves the connection of two consecutive
gate levels of three majority gates as shown in Fig. 8. It represents the D flip flop layout with regular clock zones. In this
implementation, the output depends upon the positive level of input clock and found that the area and delay of this design
is high.
All the above mentioned flip flops suffer from area and delay constraints. In [11], line based technique is employed due
to its circuit complexity and it occupies a huge area. Design [13] occupies more number of QCA cells. D flip-flop offered
in [14] obtained a larger delay. The releasing of the clocking zone results in an immediate switching of the next zone in
successive majority gate design in the input side.

3.2. Design of Novel D flip-flop

In this paper, the above limitations are addressed through a novel D flip-flop. An introduction of D flip-flop with level
sensitive design by emerging QCA technology is used to build a high performance constructive model in order to employ
the implementation of various sequential circuits.
The existing realization of D flip-flop is depicted in Figs. 6, 7 and 8 is replaced with the novel D flip-flop design which
accounts for the drastic reduction in number of cells. It could be observed from Figs. 6, 7 and 8 that the total number of
cells required to execute the D flip-flop using the majority gate method is 49, 36 and 28 respectively in an area spread of
0.05 μm2 , 0.04 μm2 and 0.03 μm2 while 52%, 34% and 15% reduction in number of cells is observed in the novel D flip-flop
implementation. The design in Fig. 9(a) utilizes only 24 cells over a spread of 0.02 μm2 . The number of cells utilized by the
proposed novel D flip-flop realization is compared with the literature and summarized in Table 2. Delay of the proposed
6 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658

Table 2
Comparison Table for D flip-flop.

D Flip-flop Design No. of Cells Area in μm2 Latency in ps

Hashemi et.al in [11] 49 0.05 1

Angizi et.al in [13] 36 0.04 1.25
Abutaleb et.al in [14] 28 0.03 0.5
Proposed 24 0.02 0.05

Table 3
Comparison for PRNG using Existing D flip flops.

PRNG Design using existing flip flop No. of Cells Area in μm2 Latency in ps

Hashemi et.al in [11] 1169 1.26 1.5

Angizi et.al in [13] 577 1.00 0.75
Abutaleb et.al in [14] 725 0.98 1.0
Proposed 549 0.91 0.5

design is reduced by employing two dimensional clocking schemes [22], where the clocking zone of the majority gate is
switched after all the clocking zones are released. Corresponding simulation result is shown in Fig. 9(b). This highlighting
feature of proposed D flip-flop design is utilized in the proposed 8-bit PRNG realization.

4. QCA Based Pseudo RNG

Generation of random numbers with QCA based Pseudo RNG is discussed in this section. Using D flip flop and EX-NOR
layout, QCA-based PRNG is introduced. Eight D flip flops are interconnected in series to build an 8-bit PRNG. Like a shift
register, the data bits are shifted from one stage to the next stage using series connection of the D flip flop. EX-NOR gates
are used to generate random numbers, since, the inverter gates do not dissipate more power compared to their normal
counterparts. Logical representation of PRNG is shown in Fig. 10. For the purpose of comparison different PRNG are designed
using the existing D flip-flop configurations available in the literature [11,13] and it is shown in Fig. 11 and Fig. 12. Finally,
the proposed global architecture of PRNG is designed and depicted in Fig. 13. Proposed QCA based PRNG consist of 8 D
flip-flops and 3 EX-NOR gates implemented in the QCA designer platform in a single layer configuration thus reducing the
number of cells than the conventional design. The proposed implementation of Pseudo RNG using novel D flip flop covers
less area than the literature’s D flip flop design. Table 3 displays the comparison of cell utilization, area and latency of the
different Pseudo RNG presented in the literature with proposed Pseudo RNG.
To evaluate the randomness of proposed PRNG, Present state and next state table are drawn from the generated random
sequences and shown in Table 4. These values which are acquired from Fig. 14. The sample of different outputs at each stage
reveals the incredible randomness of PRNG output.

5. Results and Discussion

As discussed in previous sections, an 8-bit pseudo-random number generator has been developed and implemented by
novel D flip-flop and conventional EX-NOR configuration which utilizes 8-bit LFSR connected in series with a three EX-NOR
gate configuration. LFSR generates 8 digits of random sequence starting from the MSB, EX-NOR is gate used to generate the

Fig. 8. D-flip flop design III [14].

 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658 7

Fig. 9. (a). QCA implementation of the novel D flip-flop. (b). Simulation output of the novel D flip-flop.

Fig. 10. Logical Representation of 8 bit PRNG.

random numbers. To validate the performance of the proposed Pseudo RNG based on QCA, area and delay were compared
to the other Pseudo RNGs built using the existing D flip-flop configuration presented in [11,13] and the same is reported in
Table 3.

5.1. Reliability Analysis

If temperature is increased progressively, then, the Average Output Polarization (AOP) is dropped gradually [23]. Average
cell output polarization (AOP) can be measured at any specific temperature by taking the average for difference between
8 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658

Fig. 11. QCA implementation of 8-bit PRNG using D flip-flop [11].

Fig. 12. QCA implementation of 8-bit PRNG using D flip-flop [13].

Fig. 13. QCA implementation of proposed 8-bit PRNG using novel D flip-flop.

the highest polarization and the lowest polarization.

Pmax − Pmin
AOP = (3)
2
Pmax is the maximum polarization and Pmin is the minimum polarization. Coherent vector simulation engine in QCADe-
signer ver.2.0.3 [19] is used to determine AOP analysis with the consideration of default parameters. The default constraints
are listed as, the Size of QCA cell = 18 nm, diameter of the dot = 5 nm, distance between the center of two dots = 20 nm,
relaxation time = 1.00 × 10−15 sec, Clock high = 9.800 × 10−22 J, Clock low = 3.800 × 10−23 J, Amplitude factor of the
clock = 2.00, Effective radius = 80.00 nm, Relative permittivity = 12.900 and layer separated by 11.500 nm.
 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658 9

Table 4
Present State and Next State table for Proposed PRNG.

Present State Next State Output

A B C D E F G H A+ B+ C+ D+ E+ F+ G+ H+ D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0
1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1

Table 5
AOP analysis of D flip-flop.

D Flip Flop

Temperature (K) Pmax Pmin Pavg

1 0.988 -0.988 0.988

2 0.988 -0.988 0.988
3 0.988 -0.988 0.988
4 0.988 -0.988 0.988
5 0.988 -0.988 0.988
6 0.988 -0.988 0.988
7 0.988 -0.987 0.987
8 0.988 -0.987 0.987
9 0.987 -0.987 0.987
10 0.986 -0.985 0.985
11 0.984 -0.983 0.983
12 0.982 -0.980 0.981
13 0.978 -0.976 0.977
14 0.973 -0.970 0.971
15 0.966 -0.962 0.964

The temperature effect on AOP of proposed novel D flip flop design has been analyzed by QCA Designer; the response
of a proposed implementation towards the temperature variation is shown in Fig. 15. Table 5 displays the AOP obtained at
different temperatures. In proposed D flip flop configuration, the AOP is almost constant with high accuracy output up to 9
K, afterwards it decreases gradually and the output becomes inconsistent.

5.2. Power dissipation analysis

Timler and Lent predicted the first power calculation formalism for quantum-dot cellular automata [19]. A Hamilton ma-
trix is employed to calculate the entire energy of a Quantum cell. The Hartree-Fock approximation is employed to calculate
the dissipation of power by a QCA cell is defined in equation 4 [24] and it is used in favor of a set of QCA cells where the
columbic relationship between the cells is revealed as [19,25] by a mean field method.
⎛  ⎞
− E2k di, j , pn −γ  Ek 
− 2 p j−1 + p j+1 −γ
H=⎝ ⎠ 
i= j
 = (4)
−γ Ek
2 di, j , n
p −γ Ek
2
p j−1 + p j+1
i= j

In which the nth

adjacent cell’s polarization is listed as Pn and di,j is the mathematical variable that determines elec-
trostatic cell interaction among the cells (i and j) due to geometric distance. In evenly spaced adjacent cells, factor di,j is
incorporated in the concept of kink energy (Ek ). This energy is correlated with the energy cost of the cells (i and j) taking
antipodal polarization is figured out as
4 4
1 qi,u q j,v
Ei, j = (5)
4π ε0 εr ri,u − r j,v
u=1 v=1

At each clock cycle, the expected energy of QCA cell is calculated as

h−→−→
E = H  = .λ (6)
2
10 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658

Fig. 14. Simulation Result of the proposed 8-bit PRNG using novel D flips flop (for values shown in Table 4).

Here h indicates Planck constant, the coherence vector is denoted as λ̄ and ¯ is the cell’s energy environment vector
comprising its neighboring effect and it is obtained as

−
→ 1  
 = −2γ , 0, Ek Cp−1 + Cp+1 (7)
h̄

In equation 7, (Cp-1 +Cp+1 ) is the amount of adjacent cell polarizations. A QCA cell’s energy flows are grouped into four
primary signal flows (Pinput , Poutput , Pclock and Pdissipation ). As established in [19,23] the power of the lateral signal (i.e) Pinput
and Poutput is equal, Where power received from the adjacent left cell is known as Pinput and right cell is known as Poutput .
Inter-dot barriers increase slowly due to a large amount of energy being transferred to the cell (Pclock ) during the switching
phase. These barriers are gradually reduced during the release phase, so that to return the fraction of energy to the clocking
 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658 11

0.99

Average Output Polarization

0.985
0.98
0.975
0.97
0.965 Pmax
Pmin
0.96
Pavg
0.955
0.95
0.945
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Temprature in Kelvin (K)
Fig. 15. Average output polarization analysis of novel D flip-flop configuration.

loop. It is possible to calculate the instant total power factor for a particular QCA cell as
 −
→
  →
−
dE h̄ d −→ h̄ −→ dλ
Pt = = .λ + . = P1 + P2 (8)
dt 2 dt 2 dt

In equation 8, the terminology P1 comprises two core components: power gain and clocking power (Pclock ) transmitted
to the cell, where, power gain is the difference in Pinput and Poutput signal. The terminology P2 corresponds to Pdissipation . The
dissipation of energy in a single clock cycle of QCA cells Tcc=[-T, T] is determined with respect to coherence vectors and
Hamiltonian matrix as
−
→  
h̄
 T →d λ
− h̄
−
→−→T
 T −
→
→ d
−
Ediss = . dt = .λ − λ. dt (9)
2 −T dt 2 −T −T dt

It is remarkable that the maximum dissipation of energy occurs during the rate of ¯ is as high as possible. Thereby,
when considering the upper round power dissipation model presented in [25], the energy cell environment vector, peak
(
¯ +) and low (
¯ -) is treated as peak 
¯ (+T) and low 
¯ (-T), and the corresponding power dissipation equation is stated as
 ⎡ ⎛ − → ⎞ ⎛ − → ⎞⎤
−
→ h̄  + −
→ h̄  −
Ediss h̄ − → + ⎠ +  − tanh ⎝
Pdiss = =  + X ⎣− −
→ tanh ⎝ ⎠⎦ (10)
Tcc 2T cc
+ kB T |− | kB T

Where kB is the Boltzmann constant and T is the temperature. The maximum dissipated power can be determined in a
set of different QCA cells by adding power dissipation of entire cells, as the structure provided for each QCA cell is similar
[24]. In [23] the above principle is suggested for a power dissipation paradigm of QCA circuits, by integrating the overall
dissipated power into two key components namely “leakage” and “switching”. It should be remembered that power loss due
to clock transitions (from bottom to peak and peak to bottom) contributes to power leakage (EL ) and power loss due to cell
switching states leads to switching power (ES ). QCA pro software predicts the maximum, minimum and average dissipated
power of the overall circuit for each input combination under non-adiabatic switching in various tunneling energy levels.
Furthermore, this can be employed to validate the functionality of the circuit in accordance with Bayesian network analysis.

5.2.1. Power dissipation analysis of proposed D flip-flop

A power analysis tool QCA Pro [23] is employed to measure the dissipated power of novel D flip-flop implementation. The
dissipated power is examined at three tunneling energy levels at 2K temperature. Two different terminologies with respect
to power dissipation are defined, namely, the leakage power dissipation, which arises from clock transitions, while switch-
ing power dissipation, which arises during the switching states of the cells. The implemented D flip-flop output validated
against the literature [11,13], switching (ES ), leakage (EL ) and total energy dissipation (ET ) is summarized in the Table 6. In
general, the device measures the dissipated energy of the entire circuit for each output combination based on non-adiabatic
switching in various tunneling energy levels. The power dissipation of proposed D flip flop is calculated for different tun-
neling energy levels like 0.5 Ek , 1.0 Ek and 1.5 Ek at 2K temperature. This map shows more energy dissipated by the darker
cell in the circuit than by others. Observations of the power analysis obtained from QCA Pro power analysis tool show the
dissipation of power as two different components examined at three different standard energy levels of tunneling. The novel
proposed D flip-flop configuration dissipates lower total energy dissipation as 40.3 meV at 0.5 Ek , 49.76 meV at 1.0 Ek and
61.9 meV at 1.5 Ek as compared to the literature. The testing and comparison are done for the proposed novel D flip-flop
12 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658

Table 6
Power dissipation analysis for the proposed method for D-FF.

D Flip Flop

Avg. EL Dissipation (meV) Avg. ES Dissipation (meV) Total Dissipation ET (meV)

Level of Tunnelling Energy @ 2K 0.5 EK 1.0 EK 1.5 EK 0.5 EK 1.0 EK 1.5 EK 0.5 EK 1.0 EK 1.5 EK

Existing D FF [11] 13.5 43.08 78.04 75.34 65.33 55.5 88.84 108.41 133.54
Existing D FF [13] 9.04 27.14 48.25 37.79 32.48 27.46 46.83 59.62 75.71
Proposed D FF 6.94 21.14 37.74 33.36 28.62 24.16 40.3 49.76 61.9

Fig. 16. Power dissipation map of proposed D flip-flop for various Tunneling energy states.

160
Total Energy Dissipaon (E T) of Exisng D FF [11]
140 Total Energy Dissipaon (E T) of Exisng D FF [13] 133.54
Total Energy Dissipaon (E T) of Proposed D FF
120
Total Energy Dissipaon

108.41
100 88.84

80 75.71
59.62 61.9
60
46.83 49.76
40.3
40

20

0
0.5Ek 1.0Ek 1.5Ek
Tunnelling Energy Level @ 2K Temprature

Fig. 17. Average energy dissipation of D flip-flop for various tunneling energy levels.

Configuration with existing works and power dissipation map for the proposed D flip flop configuration is depicted in the
Fig. 16. To justify the proposed work, graphical representation of existing and proposed novel D flip-flop power dissipation
values is compared and depicted in Fig. 17.

6. Conclusion

Quantum cellular dot automata theory is an emerging area of research in nanotechnology owing to its inherent prop-
erties like optimization in power, speed and area. The 8-bit PRNG implemented using QCA technology has been analyzed
extensively for optimization with respect to delay, area and power dissipation. The proposed D-flip flop type implementa-
tion is observed to decrease the cell count by a huge margin when compared to existing designs in the literature. Significant
reductions in area and power have also been accounted in this work. As a future scope of research, the proposed D flip flop
design together with conventional EX-NOR configuration, does tend to offer a huge potential, that could be tapped in future
nanotechnology. Also, the proposed work provides ample scope to build more ultra-low power effective implementations of
PRNG. It could be used to build the complex circuits like encryption and decryption blocks for secured communication.
 S. Senthilnathan and S. Kumaravel / Computers and Electrical Engineering 85 (2020) 106658 13

Declaration of Competing Interests

The authors declare that they have no known competing financial interests or personal relationships that could have
appeared to influence the work reported in this paper.

CRediT authorship contribution statement

S. Senthilnathan: Data curation, Writing - original draft, Visualization, Investigation, Software, Validation. S. Kumaravel:
Conceptualization, Methodology, Supervision, Writing - review & editing.

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S.Senthilnathan received Bachelor’s in Electronics and Communication Engineering from A.V.C College of Engineering, Mayiladuthurai affiliated to Anna
University, M.E from SRM Easwari Engineering college affiliated to Anna University. Presently working as an Assistant Professor, Department of Electronics
and Communication, A.V.C College of Engineering. Also pursuing Ph.D in Vellore Institute of Technology, Vellore. His research interests include Quantum
dot Cellular Automata.

S.Kumaravel, received his B.E in Electronics and Instrumentation Engineering from GCT, Coimbatore in 1999. He received M.E from SRM Easwari Engineer-
ing College Affiliated to Anna University, Chennai in 2007. He completed his Ph.D. from the Department of Electronics and Communication Engineering,
NIT, Tiruchirappalli in January 2015. Presently working as an Associate Professor, School of Electronics Engineering, Vellore Institute of Technology, Vellore.