Chapter 6

Dataflow Modeling

教師: 陳銘志

Electronic Engineering, NKFUST 1

 Learning Objects
 Describe the continuous assignment (assign) statement,
restrictions on the assign statement, and the implicit
continuous assignment statement.
 Explain assignment delay, implicit assignment delay, and
net declaration delay for continuous assignment
statements.
 Define expressions, operators, and operands.
 List operator types for all possible operations －arithmetic,
logical, relational, equality, bitwise, reduction, shift,
concatenation, and conditional.
 Use dataflow constructs to model practical digital circuits in
Verilog.

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 Continuous Assignments
 A continuous assignment is the most basic
statement in dataflow modeling, used to drive a
value onto a net.

continuous_assign ::= assign [ drive_strength ] [ delay3 ]

list_of_net_assignments ;
list_of_net_assignments ::= net_assignment { , net_assignment }
net_assignment ::= net_lvalue = expression

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 Characteristics of Continuous
Assignment
 The left-hand side of an assignment must always
be a scalar or vector net or a concatenation of
scalar and vector nets.
 Continuous assignment are always active.
 The operands on the right-hand side can be
registers or nets or function calls.
 Delay values can be specified for assignment in
terms of time units.

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 Examples of Continuous Assignment
// Continuous assign. out is a net. i1 and i2 are nets.
assign out = i1 & i2;
// Continuous assign for vector nets. addr is a 16-bit vector net
// addr1 and addr2 are 16-bit vector registers.
assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0];
// Concatenation. Left-hand side is a concatenation of a scalar
// net and a vector net.
assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;

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 Implicit Continuous Assignment
 Instead of declaring a net and then writing a continuous
assignment on the net, Verilog provides a shortcut by
which a continuous assignment can be placed on a net
when it is declared.

//Regular continuous assignment

wire out;
assign out = in1 & in2;
//Same effect is achieved by an implicit continuous assignment
wire out = in1 & in2;

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 Implicit Net Declaration
 If a signal name is used to the left of the continuous
assignment, an implicit net declaration will be
inferred for that signal name.

// Continuous assign. out is a net.

wire i1, i2;
assign out = i1 & i2; //Note that out was not declared as a wire
//but an implicit wire declaration for out
//is done by the simulator

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 Delays
 Delay values control the time between the
change in a right-hand-side operand and when
the new value is assigned to the left-hand side.
 Three ways of specifying delays in continuous
assignment statements:
 Regular assignment delay
 Implicit continuous assignment delay
 Net declaration delay

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 Regular Assignment Delay (inertial
delay)
 Any change in values of in1 or in2 will result in a
delay of 10 time units before recomputation of
the expression in1&in2, and the result will be
assigned to out.

assign #10 out = in1 & in2; // Delay in a continuous assign

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 in1 < 10 units, does
Waveform not propagate to the
output

Delay 10 Delay 10
units units

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Implicit Continuous Assignment Delay

 An equivalent method is to use an implicit

continuous assignment to specify both a delay
and an assignment on the net.
//implicit continuous assignment delay
wire #10 out = in1 & in2;
//same as
wire out;
assign #10 out = in1 & in2;

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 Net Declaration Delay
 A delay can be specified on a net when it is
declared without putting a continuous assignment
on the net.
//Net Delays
wire # 10 out;
assign out = in1 & in2;
//The above statement has the same effect as the following.
wire out;
assign #10 out = in1 & in2;

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Expressions, Operators, and Operands

 Dataflow modeling describes the design in terms

of expressions instead of primitive gates.
 Expressions, operators, and operands form the
basis of dataflow modeling.

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 Expressions
 Expressions are constructs that combine
operators and operands to produce a result.
// Examples of expressions. Combines operands and operators
a^b
addr1[20:17] + addr2[20:17]
in1 | in2

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 Operands
 Operands can be constants, integers, real
numbers, nets, registers, times, bit-select (one
bit of vector net or a vector register), part-select
(selected bits of the vector net or register vector),
and memories or function calls.

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 Example of Operands
(Behavioral Modeling)
integer count, final_count;
final_count = count + 1;//count is an integer operand
real a, b, c;
c = a - b; //a and b are real operands
reg [15:0] reg1, reg2;
reg [3:0] reg_out;
reg_out = reg1[3:0] ^ reg2[3:0]; //reg1[3:0] and reg2[3:0] are
//part-select register operands
reg ret_value;
ret_value = calculate_parity(A, B); //calculate_parity is a
//function type operand

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 Operators
 Operators act on the operands to produce
desired results.

d1 && d2 // && is an operator on operands d1 and d2

!a[0] // ! is an operator on operand a[0]
B >> 1 // >> is an operator on operands B and 1

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 Operator Types
 Verilog provides many different operator types.
Operators can be arithmetic, logical, relational,
equality, bitwise, reduction, shift, concatenation,
or conditional.

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Operator
Types
and
Symbols
(1)

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Operator
Types
and
Symbols
(2)

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 Arithmetic Operators
 There are two types of arithmetic operators:
binary and unary.

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 Binary Operators (1)
 Binary arithmetic operators are multiply (*),
divide (/), add (+), subtract (-), power (**), and
modulus (%). Binary operators take two
operands.
A = 4'b0011; B = 4'b0100; // A and B are register vectors
D = 6; E = 4; F=2// D and E are integers
A * B // Multiply A and B. Evaluates to 4'b1100
D / E // Divide D by E. Evaluates to 1. Truncates any fractional part.
A + B // Add A and B. Evaluates to 4'b0111
B - A // Subtract A from B. Evaluates to 4'b0001
F = E ** F; //E to the power F, yields 16

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 Binary Operators (2)
 If any operand bit has a value x, then the result of the
entire expression is x.

in1 = 4'b101x;
in2 = 4'b1010;
sum = in1 + in2; // sum will be evaluated to the value 4'bx

 Modulus operators produce the remainder from the

division of two numbers.
13 % 3 // Evaluates to 1
16 % 4 // Evaluates to 0
-7 % 2 // Evaluates to -1, takes sign of the first operand
7 % -2 // Evaluates to +1, takes sign of the first operand
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 Unary Operators (1)
 They are used to specify the positive or negative sign of the
operand. Unary + or – operators have higher precedence
than the binary + or – operators.

-4 // Negative 4
+5 // Positive 5

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 Unary Operators (2)
 Negative numbers are represented as 2's
complement internally in Verilog. It is advisable
to use negative numbers only of the type integer
or real in expressions.
//Advisable to use integer or real numbers
-10 / 5// Evaluates to -2
//Do not use numbers of type <sss> '<base> <nnn>
-'d10 / 5// Is equivalent (2's complement of 10)/5 = (232 - 10)/5
// where 32 is the default machine word width.
// This evaluates to an incorrect and unexpected result

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 Logical Operators (1)
 Logical operators are logical-and (&&), logical-or
(||) and logical-not (!). Operators && and || are
binary operators. Operator ! is a unary operator.
 Logical operators follow these conditions:
 Logical operators always evaluate to a 1-bit value, 0
(false), 1 (true), or x (ambiguous).
 If an operand is not equal to zero, it is equivalent to a
logical 1 (true condition). If it is equal to zero, it is
equivalent to a logical 0 (false condition). If any
operand bit is x or z, it is equivalent to x (ambiguous
condition) and is normally treated by simulators as a
false condition.
 Logical operators take variables or expressions as
operands.
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 Logical Operators (2)
 Use of parentheses to group logical operations is highly
recommended to improve readability.
// Logical operations
A = 3; B = 0;
A && B // Evaluates to 0. Equivalent to (logical-1 && logical-0)
A || B // Evaluates to 1. Equivalent to (logical-1 || logical-0)
!A// Evaluates to 0. Equivalent to not(logical-1)
!B// Evaluates to 1. Equivalent to not(logical-0)
// Unknowns
A = 2'b0x; B = 2'b10;
A && B // Evaluates to x. Equivalent to (x && logical 1)
// Expressions
(a == 2) && (b == 3) // Evaluates to 1 if both a == 2 and b == 3 are true.
// Evaluates to 0 if either is false.

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 Relational Operators (1)
 Relational operators are greater-than (>), less-
than (<), greater-than-or-equal-to (>=), and less-
than-or-equal-to (<=).
 If relational operators are used in an expression,
the expression returns a logical value of 1 if the
expression is true and 0 if the expression is false.
If there are any unknown (x) or z bits in the
operands, the expression takes a value x.

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 Relational Operators (2)
// A = 4, B = 3
// X = 4'b1010, Y = 4'b1101, Z = 4'b1xxx
A <= B // Evaluates to a logical 0
A > B // Evaluates to a logical 1
Y >= X // Evaluates to a logical 1
Y < Z // Evaluates to an x

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 Equality Operators (1)
 Equality operators are logical equality (==),
logical inequality (!=), case equality (===), and
case inequality (!==).
 These operators compare the two operands bit
by bit, with zero filling if the operands are of
unequal length.
Expression Description Possible Logical Value
a = = b a equal to b, result unknown if x or z in a or b 0, 1, x
a != b a not equal to b, result unknown if x or z in a or b 0, 1, x
a = = = b a equal to b, including x and z 0, 1
a != = b a not equal to b, including x and z 0, 1

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 Equality Operators (2)
 The logical equality operators (==, !=) will yield an x if
either operand has x or z in its bits. However, the case
equality operators ( ===, !== ) compare both operands
bit by bit and compare all bits, including x and z.
// A = 4, B = 3
// X = 4'b1010, Y = 4'b1101
// Z = 4'b1xxz, M = 4'b1xxz, N = 4'b1xxx
A = = B // Results in logical 0
X != Y // Results in logical 1
X = = Z // Results in x
Z = = = M // Results in logical 1 (all bits match, including x and z)
Z = = = N // Results in logical 0 (least significant bit does not match)
M != = N // Results in logical 1
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 Bitwise Operators
 Bitwise operators are negation (~), and(&), or (|),
xor (^), xnor (^~, ~^). Bitwise operators perform
a bit-by-bit operation on two operands.
 If one operand is shorter than the other, it will be
bit-extended with zeros to match the length of
the longer operand.
 The exception is the unary negation operator (~),
which takes only one operand and operates on
the bits of the single operand.

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 Truth
Tables for
Bitwise
Operators

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Examples of Bitwise Operators
// X = 4'b1010, Y = 4'b1101
// Z = 4'b10x1
~X // Negation. Result is 4'b0101
X & Y // Bitwise and. Result is 4'b1000
X | Y // Bitwise or. Result is 4'b1111
X ^ Y // Bitwise xor. Result is 4'b0111
X ^~ Y // Bitwise xnor. Result is 4'b1000
X & Z // Result is 4'b10x0

// X = 4'b1010, Y = 4'b0000
X | Y // bitwise operation. Result is 4'b1010
X || Y // logical operation. Equivalent to 1 || 0.
Result is 1.

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 Reduction Operators
 Reduction operators are and (&), nand (~&), or
(|), nor (~|), xor (^), and xnor (~^, ^~). Reduction
operators take only one operand.
 Reduction operators perform a bitwise operation
on a single vector operand and yield a 1-bit
result.
 Reduction nand, reduction nor, and reduction
xnor are computed by inverting the result of the
reduction and, reduction or, and reduction xor,
respectively.

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Example of Reduction Operators
// X = 4'b1010
&X //Equivalent to 1 & 0 & 1 & 0. Results in 1'b0
|X //Equivalent to 1 | 0 | 1 | 0. Results in 1'b1
^X //Equivalent to 1 ^ 0 ^ 1 ^ 0. Results in 1'b0
//A reduction xor or xnor can be used for even or odd parity
//generation of a vector.

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 Shift Operators
 Shift operators are right shift ( >>), left shift (<<),
arithmetic right shift (>>>), and arithmetic left
shift (<<<).
 When the bits are shifted, the vacant bit
positions are filled with zeros. Shift operations
do not wrap around.
 Arithmetic shift operators use the context of the
expression to determine the value with which to
fill the vacated bits.

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 Example of Shift Operators
// X = 4'b1100
Y = X >> 1; //Y is 4'b0110. Shift right 1 bit. 0 filled in MSB
position.
Y = X << 1; //Y is 4'b1000. Shift left 1 bit. 0 filled in LSB position.
Y = X << 2; //Y is 4'b0000. Shift left 2 bits.
integer a, b, c; //Signed data types
a = 0;
b = -10; // 00111...10110 binary
c = a + (b >>> 3); //Results in -2 decimal, due to arithmetic shift

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 Arithmetic Shift
4-bit value:
 0111 >>> 1 = 0011 (unsigned)
 1100 >>> 1 = 0110 (unsgned)
 1100 >>> 1 = 1110 (signed)

4-bit signed value:

 $signed(1100) >>> 1 = 1110;

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 Shift Example (1)
(From https://nandland.com/shift-operator/)
module shift_operator ();
reg [3:0] r_Shift1 = 4'b1000;
reg signed [3:0] r_Shift2 = 4'b1000;

initial begin
// Left Shift
$display("%b", r_Shift1 << 1);
$display("%b", $signed(r_Shift1) <<< 1); // Cast as signed
$display("%b", r_Shift2 <<< 1); // Declared as signed type
// Right Shift
$display("%b", r_Shift1 >> 2);
$display("%b", $signed(r_Shift1) >>> 2); // Cast as signed
$display("%b", r_Shift2 >>> 2) ; // Declared as signed type
end
endmodule
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 Shift Example (2)
(From https://nandland.com/shift-operator/)
Simulation Output:
# 0000
# 0000
# 0000
# 0010
# 1110
# 1110

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 Concatenation Operator
 The concatenation operator ( {, } ) provides a
mechanism to append multiple operands. The
operands must be sized.
// A = 1'b1, B = 2'b00, C = 2'b10, D = 3'b110
Y = {B , C}; // Result Y is 4'b0010
Y = {A , B , C , D , 3'b001}; // Result Y is 11'b10010110001
Y = {A , B[0], C[1]}; // Result Y is 3'b101

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 Replication Operator
 Repetitive concatenation of the same number
can be expressed by using a replication
constant.
reg A;
reg [1:0] B, C;
reg [2:0] D;
A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;
Y = { 4{A} } // Result Y is 4'b1111
Y = { 4{A} , 2{B} } // Result Y is 8'b11110000
Y = { 4{A} , 2{B} , C } // Result Y is 8'b1111000010

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 Conditional Operator
 Usage: condition_expr ? true_expr : false_expr ;
 The action of a conditional operator is similar to
a multiplexer.

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 Example of Conditional Operator
 The conditional expression acts as a switching control.

//model functionality of a tristate buffer

assign addr_bus = drive_enable ? addr_out : 36'bz;
//model functionality of a 2-to-1 mux
assign out = control ? in1 : in0;

 Conditional operations can be nested.

assign out = (A == 3) ? ( control ? x : y ): ( control ? m : n) ;

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Operator Precedence

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 Examples
 4-to-1 Multiplexer
 Method 1: logic equation
 Method 2: conditional operator
 Ripple Counter

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4-to-1 Multiplexer (Method 1: logic
equation)
// Module 4-to-1 multiplexer using data flow. logic equation
// Compare to gate-level model
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
//Logic equation for out
assign out = (~s1 & ~s0 & i0)|
(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3) ;
endmodule
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 4-to-1 Multiplexer (Method 2:
conditional operator)
// Module 4-to-1 multiplexer using data flow. Conditional
operator.
// Compare to gate-level model
module multiplexer4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
// Use nested conditional operator
assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule

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 Ripple Counter
 We design a 4-bit ripple counter by using negative edge-
triggered flipflops.

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 T-flipflop

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 D-flipflop

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Verilog Code for Ripple Counter
// Ripple counter
module counter(Q , clock, clear);
// I/O ports
output [3:0] Q;
input clock, clear;
// Instantiate the T flipflops
T_FF tff0(Q[0], clock, clear);
T_FF tff1(Q[1], Q[0], clear);
T_FF tff2(Q[2], Q[1], clear);
T_FF tff3(Q[3], Q[2], clear);
endmodule

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 Verilog Code for T-flipflop
// Edge-triggered T-flipflop. Toggles every clock
// cycle.
module T_FF(q, clk, clear);
// I/O ports
output q;
input clk, clear;
// Instantiate the edge-triggered DFF
// Complement of output q is fed back.
// Notice qbar not needed. Unconnected port.
edge_dff ff1(q, ,~q, clk, clear);
endmodule

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 Verilog
// Edge-triggered D flipflop
Code for module edge_dff(q, qbar, d, clk, clear);
Edge- output q,qbar;
Triggered
D-flipflop input d, clk, clear;
// Internal variables
wire s, sbar, r, rbar,cbar;
// dataflow statements
//Create a complement of signal clear
assign cbar = ~clear;
// Input latches; A latch is level sensitive. An edge-sensitive
// flip-flop is implemented by using 3 SR latches.
assign sbar = ~(rbar & s),
s = ~(sbar & cbar & ~clk),
r = ~(rbar & ~clk & s),
rbar = ~(r & cbar & d);
// Output latch
assign q = ~(s & qbar),
qbar = ~(q & r & cbar);
endmodule
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Stimulus Module for Ripple Counter (1)
module stimulus;
// Declare variables for stimulating input
reg CLOCK, CLEAR;
wire [3:0] Q;
initial
$monitor($time, " Count Q = %b Clear= %b", Q[3:0],CLEAR);
// Instantiate the design block counter
counter c1(Q, CLOCK, CLEAR);
// Stimulate the Clear Signal
initial
begin
CLEAR = 1'b1;
#34 CLEAR = 1'b0;
#200 CLEAR = 1'b1;
#50 CLEAR = 1'b0;
end Electronic Engineering, NKFUST 56
Stimulus Module for Ripple Counter (2)
// Set up the clock to toggle every 10 time units
initial
begin
CLOCK = 1'b0;
forever #10 CLOCK = ~CLOCK;
end
// Finish the simulation at time 400
initial
begin
#400 $finish;
end
endmodule

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Output of the Simulation
34 Count Q = 0000 Clear= 0
40 Count Q = 0001 Clear= 0
60 Count Q = 0010 Clear= 0
80 Count Q = 0011 Clear= 0
100 Count Q = 0100 Clear= 0
120 Count Q = 0101 Clear= 0
140 Count Q = 0110 Clear= 0
160 Count Q = 0111 Clear= 0
180 Count Q = 1000 Clear= 0
200 Count Q = 1001 Clear= 0
220 Count Q = 1010 Clear= 0
234 Count Q = 0000 Clear= 1
284 Count Q = 0000 Clear= 0
300 Count Q = 0001 Clear= 0
320 Count Q = 0010 Clear= 0
340 Count Q = 0011 Clear= 0
360 Count Q = 0100 Clear= 0
380 Count Q = 0101 Clear= 0
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