TMS320F28P55x Real-Time

Microcontrollers

Technical Reference Manual

Literature Number: SPRUJ53B

APRIL 2024 – REVISED SEPTEMBER 2024
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Table of Contents

Read This First.........................................................................................................................................................................89

About This Manual................................................................................................................................................................. 89
Notational Conventions.......................................................................................................................................................... 89
Glossary................................................................................................................................................................................. 89
Related Documentation From Texas Instruments.................................................................................................................. 89
Support Resources................................................................................................................................................................ 89
Trademarks............................................................................................................................................................................ 90
1 C2000™ Microcontrollers Software Support......................................................................................................................91
1.1 Introduction...................................................................................................................................................................... 92
1.2 C2000Ware Structure.......................................................................................................................................................92
1.3 Documentation................................................................................................................................................................. 92
1.4 Devices............................................................................................................................................................................ 92
1.5 Libraries........................................................................................................................................................................... 92
1.6 Code Composer Studio™ Integrated Development Environment (IDE).......................................................................... 92
1.7 SysConfig and PinMUX Tool............................................................................................................................................ 93
2 C28x Processor.....................................................................................................................................................................94
2.1 Introduction...................................................................................................................................................................... 95
2.2 C28X Related Collateral...................................................................................................................................................95
2.3 Features........................................................................................................................................................................... 95
2.4 Floating-Point Unit (FPU)................................................................................................................................................. 96
2.5 Trigonometric Math Unit (TMU)........................................................................................................................................96
2.6 VCRC Unit........................................................................................................................................................................97
3 System Control and Interrupts............................................................................................................................................ 98
3.1 Introduction...................................................................................................................................................................... 99
3.1.1 SYSCTL Related Collateral....................................................................................................................................... 99
3.1.2 LOCK Protection on System Configuration Registers............................................................................................... 99
3.1.3 EALLOW Protection.................................................................................................................................................. 99
3.2 Power Management....................................................................................................................................................... 100
3.3 Device Identification and Configuration Registers......................................................................................................... 100
3.4 Resets............................................................................................................................................................................ 100
3.4.1 Reset Sources......................................................................................................................................................... 100
3.4.2 External Reset (XRS).............................................................................................................................................. 101
3.4.3 Simulate External Reset (SIMRESET.XRS)............................................................................................................ 101
3.4.4 Power-On Reset (POR)...........................................................................................................................................101
3.4.5 Brown-Out Reset (BOR)..........................................................................................................................................102
3.4.6 Debugger Reset (SYSRS).......................................................................................................................................102
3.4.7 Simulate CPU Reset (SIMRESET)..........................................................................................................................102
3.4.8 Watchdog Reset (WDRS)........................................................................................................................................102
3.4.9 NMI Watchdog Reset (NMIWDRS)..........................................................................................................................102
3.4.10 DCSM Safe Code Copy Reset (SCCRESET)....................................................................................................... 102
3.5 Peripheral Interrupts.......................................................................................................................................................103
3.5.1 Interrupt Concepts................................................................................................................................................... 103
3.5.2 Interrupt Architecture............................................................................................................................................... 103
3.5.3 Interrupt Entry Sequence.........................................................................................................................................105
3.5.4 Configuring and Using Interrupts.............................................................................................................................106
3.5.5 PIE Channel Mapping..............................................................................................................................................108
3.5.6 PIE Interrupt Priority................................................................................................................................................ 109
3.5.7 System Error............................................................................................................................................................ 110
3.5.8 Vector Tables............................................................................................................................................................111

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3.6 Exceptions and Non-Maskable Interrupts.......................................................................................................................117

3.6.1 Configuring and Using NMIs.................................................................................................................................... 117
3.6.2 Emulation Considerations........................................................................................................................................ 117
3.6.3 NMI Sources............................................................................................................................................................ 117
3.6.4 Illegal Instruction Trap (ITRAP)................................................................................................................................118
3.6.5 ERRORSTS Pin.......................................................................................................................................................118
3.7 Clocking..........................................................................................................................................................................118
3.7.1 Clock Sources......................................................................................................................................................... 120
3.7.2 Derived Clocks........................................................................................................................................................ 124
3.7.3 Device Clock Domains............................................................................................................................................ 124
3.7.4 XCLKOUT................................................................................................................................................................125
3.7.5 Clock Connectivity................................................................................................................................................... 125
3.7.6 Clock Source and PLL Setup.................................................................................................................................. 128
3.7.7 Using an External Crystal or Resonator.................................................................................................................. 128
3.7.8 Using an External Oscillator.................................................................................................................................... 129
3.7.9 Choosing PLL Settings............................................................................................................................................ 129
3.7.10 System Clock Setup.............................................................................................................................................. 130
3.7.11 SYS PLL Bypass....................................................................................................................................................130
3.7.12 Clock (OSCCLK) Failure Detection....................................................................................................................... 131
3.8 32-Bit CPU Timers 0/1/2................................................................................................................................................ 133
3.9 Watchdog Timer............................................................................................................................................................. 134
3.9.1 Servicing the Watchdog Timer.................................................................................................................................135
3.9.2 Minimum Window Check......................................................................................................................................... 135
3.9.3 Watchdog Reset or Watchdog Interrupt Mode.........................................................................................................136
3.9.4 Watchdog Operation in Low-Power Modes............................................................................................................. 136
3.9.5 Emulation Considerations........................................................................................................................................136
3.10 Low-Power Modes....................................................................................................................................................... 137
3.10.1 Clock-Gating Low-Power Modes........................................................................................................................... 137
3.10.2 IDLE.......................................................................................................................................................................137
3.10.3 STANDBY.............................................................................................................................................................. 138
3.10.4 HALT......................................................................................................................................................................139
3.11 Memory Controller Module........................................................................................................................................... 140
3.11.1 Functional Description........................................................................................................................................... 140
3.12 JTAG............................................................................................................................................................................ 148
3.12.1 JTAG Noise and TAP_STATUS............................................................................................................................. 148
3.13 Live Firmware Update.................................................................................................................................................. 148
3.13.1 LFU Background....................................................................................................................................................148
3.13.2 LFU Switchover Steps........................................................................................................................................... 149
3.13.3 Device Features Supporting LFU.......................................................................................................................... 149
3.13.4 LFU Switchover..................................................................................................................................................... 153
3.13.5 LFU Resources......................................................................................................................................................153
3.14 System Control Register Configuration Restrictions.................................................................................................... 153
3.15 Software....................................................................................................................................................................... 154
3.15.1 SYSCTL Registers to Driverlib Functions..............................................................................................................154
3.15.2 CPUTIMER Registers to Driverlib Functions.........................................................................................................163
3.15.3 MEMCFG Registers to Driverlib Functions............................................................................................................164
3.15.4 PIE Registers to Driverlib Functions......................................................................................................................168
3.15.5 NMI Registers to Driverlib Functions..................................................................................................................... 169
3.15.6 XINT Registers to Driverlib Functions................................................................................................................... 170
3.15.7 WWD Registers to Driverlib Functions.................................................................................................................. 171
3.15.8 SYSCTL Examples................................................................................................................................................171
3.15.9 TIMER Examples...................................................................................................................................................172
3.15.10 MEMCFG Examples............................................................................................................................................172
3.15.11 INTERRUPT Examples........................................................................................................................................173
3.15.12 LPM Examples.................................................................................................................................................... 175
3.15.13 WATCHDOG Examples.......................................................................................................................................177
3.16 SYSCTRL Registers.................................................................................................................................................... 178
3.16.1 SYSCTRL Base Address Table............................................................................................................................. 178
3.16.2 CPUTIMER_REGS Registers............................................................................................................................... 179
3.16.3 PIE_CTRL_REGS Registers................................................................................................................................. 186
3.16.4 NMI_INTRUPT_REGS Registers.......................................................................................................................... 238

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3.16.5 XINT_REGS Registers.......................................................................................................................................... 254

3.16.6 SYNC_SOC_REGS Registers.............................................................................................................................. 263
3.16.7 DMA_CLA_SRC_SEL_REGS Registers...............................................................................................................270
3.16.8 LFU_REGS Registers........................................................................................................................................... 277
3.16.9 DEV_CFG_REGS Registers................................................................................................................................. 283
3.16.10 CLK_CFG_REGS Registers................................................................................................................................341
3.16.11 CPU_SYS_REGS Registers................................................................................................................................364
3.16.12 SYS_STATUS_REGS Registers......................................................................................................................... 424
3.16.13 PERIPH_AC_REGS Registers............................................................................................................................433
3.16.14 MEM_CFG_REGS Registers.............................................................................................................................. 484
3.16.15 ACCESS_PROTECTION_REGS Registers........................................................................................................539
3.16.16 MEMORY_ERROR_REGS Registers................................................................................................................. 566
3.16.17 TEST_ERROR_REGS Registers........................................................................................................................ 590
3.16.18 UID_REGS Registers.......................................................................................................................................... 594
4 ROM Code and Peripheral Booting...................................................................................................................................603
4.1 Introduction.................................................................................................................................................................... 604
4.1.1 ROM Related Collateral...........................................................................................................................................604
4.2 Device Boot Sequence...................................................................................................................................................605
4.3 Device Boot Modes........................................................................................................................................................ 605
4.3.1 Default Boot Modes................................................................................................................................................. 605
4.3.2 Custom Boot Modes................................................................................................................................................ 606
4.4 Device Boot Configurations............................................................................................................................................606
4.4.1 Configuring Boot Mode Pins....................................................................................................................................607
4.4.2 Configuring Boot Mode Table Options.....................................................................................................................609
4.4.3 Boot Mode Example Use Cases..............................................................................................................................610
4.5 Device Boot Flow Diagrams........................................................................................................................................... 611
4.5.1 Boot Flow................................................................................................................................................................. 611
4.5.2 Emulation Boot Flow................................................................................................................................................613
4.5.3 Standalone Boot Flow ............................................................................................................................................ 614
4.6 Device Reset and Exception Handling...........................................................................................................................615
4.6.1 Reset Causes and Handling....................................................................................................................................615
4.6.2 Exceptions and Interrupts Handling.........................................................................................................................616
4.7 Boot ROM Description................................................................................................................................................... 617
4.7.1 Boot ROM Configuration Registers......................................................................................................................... 617
4.7.2 Entry Points............................................................................................................................................................. 619
4.7.3 Wait Points...............................................................................................................................................................620
4.7.4 Secure Flash Boot................................................................................................................................................... 620
4.7.5 Firmware Update (FWU) Flash Boot....................................................................................................................... 623
4.7.6 Memory Maps..........................................................................................................................................................624
4.7.7 ROM Tables.............................................................................................................................................................625
4.7.8 Boot Modes and Loaders........................................................................................................................................ 625
4.7.9 GPIO Assignments.................................................................................................................................................. 643
4.7.10 Secure ROM Function APIs.................................................................................................................................. 645
4.7.11 Clock Initializations................................................................................................................................................ 646
4.7.12 Boot Status Information......................................................................................................................................... 646
4.7.13 ROM Version......................................................................................................................................................... 648
4.8 Application Notes for Using the Bootloaders..................................................................................................................648
4.8.1 Bootloader Data Stream Structure.......................................................................................................................... 648
4.8.2 The C2000 Hex Utility..............................................................................................................................................650
4.9 Software......................................................................................................................................................................... 651
4.9.1 BOOT Examples......................................................................................................................................................651
5 Dual Code Security Module (DCSM)................................................................................................................................. 652
5.1 Introduction.................................................................................................................................................................... 653
5.1.1 DCSM Related Collateral........................................................................................................................................ 653
5.2 Functional Description....................................................................................................................................................653
5.2.1 CSM Passwords...................................................................................................................................................... 654
5.2.2 Emulation Code Security Logic (ECSL)...................................................................................................................656
5.2.3 CPU Secure Logic................................................................................................................................................... 656
5.2.4 Execute-Only Protection..........................................................................................................................................656
5.2.5 Password Lock........................................................................................................................................................ 656
5.2.6 JTAGLOCK.............................................................................................................................................................. 657

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5.2.7 Link Pointer and Zone Select.................................................................................................................................. 657

5.2.8 C Code Example to Get Zone Select Block Addr for Zone1....................................................................................660
5.3 Flash and OTP Erase/Program......................................................................................................................................660
5.4 Secure Copy Code.........................................................................................................................................................660
5.5 SecureCRC.................................................................................................................................................................... 661
5.6 CSM Impact on Other On-Chip Resources....................................................................................................................662
5.7 Incorporating Code Security in User Applications..........................................................................................................663
5.7.1 Environments That Require Security Unlocking...................................................................................................... 663
5.7.2 CSM Password Match Flow.................................................................................................................................... 663
5.7.3 C Code Example to Unsecure C28x Zone1............................................................................................................ 665
5.7.4 C Code Example to Resecure C28x Zone1............................................................................................................ 665
5.7.5 Environments That Require ECSL Unlocking..........................................................................................................665
5.7.6 ECSL Password Match Flow................................................................................................................................... 665
5.7.7 ECSL Disable Considerations for any Zone............................................................................................................ 667
5.7.8 Device Unique ID.....................................................................................................................................................667
5.8 Software......................................................................................................................................................................... 667
5.8.1 DCSM Registers to Driverlib Functions................................................................................................................... 667
5.8.2 DCSM Examples..................................................................................................................................................... 671
5.9 DCSM Registers............................................................................................................................................................ 672
5.9.1 DCSM Base Address Table..................................................................................................................................... 672
5.9.2 DCSM_Z1_REGS Registers................................................................................................................................... 673
5.9.3 DCSM_Z2_REGS Registers................................................................................................................................... 721
5.9.4 DCSM_COMMON_REGS Registers.......................................................................................................................758
5.9.5 DCSM_Z1_OTP Registers...................................................................................................................................... 780
5.9.6 DCSM_Z2_OTP Registers...................................................................................................................................... 797
6 Flash Module.......................................................................................................................................................................807
6.1 Introduction to Flash and OTP Memory......................................................................................................................... 808
6.1.1 FLASH Related Collateral....................................................................................................................................... 808
6.1.2 Features.................................................................................................................................................................. 808
6.1.3 Flash Tools.............................................................................................................................................................. 809
6.1.4 Default Flash Configuration..................................................................................................................................... 809
6.2 Flash Bank, OTP, and Pump.......................................................................................................................................... 809
6.3 Flash Wrapper ...............................................................................................................................................................810
6.4 Flash and OTP Memory Performance............................................................................................................................811
6.5 Flash Read Interface...................................................................................................................................................... 811
6.5.1 C28x-Flash Read Interface...................................................................................................................................... 811
6.6 Flash Erase and Program.............................................................................................................................................. 814
6.6.1 Erase....................................................................................................................................................................... 814
6.6.2 Program...................................................................................................................................................................814
6.6.3 Verify........................................................................................................................................................................814
6.7 Error Correction Code (ECC) Protection........................................................................................................................815
6.7.1 Single-Bit Data Error................................................................................................................................................816
6.7.2 Uncorrectable Error................................................................................................................................................. 817
6.7.3 Mechanism to Check the Correctness of ECC Logic.............................................................................................. 817
6.8 Reserved Locations Within Flash and OTP................................................................................................................... 819
6.9 Migrating an Application from RAM to Flash..................................................................................................................819
6.10 Procedure to Change the Flash Control Registers...................................................................................................... 820
6.11 Software....................................................................................................................................................................... 820
6.11.1 FLASH Registers to Driverlib Functions................................................................................................................ 820
6.11.2 FLASH Examples...................................................................................................................................................820
6.12 FLASH Registers......................................................................................................................................................... 821
6.12.1 FLASH Base Address Table.................................................................................................................................. 821
6.12.2 FLASH_CTRL_REGS Registers........................................................................................................................... 822
6.12.3 FLASH_ECC_REGS Registers............................................................................................................................. 826
7 Control Law Accelerator (CLA)..........................................................................................................................................829
7.1 Introduction.................................................................................................................................................................... 830
7.1.1 Features.................................................................................................................................................................. 830
7.1.2 CLA Related Collateral............................................................................................................................................ 830
7.1.3 Block Diagram......................................................................................................................................................... 831
7.2 CLA Interface................................................................................................................................................................. 832
7.2.1 CLA Memory............................................................................................................................................................832

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7.2.2 CLA Memory Bus.................................................................................................................................................... 833

7.2.3 Shared Peripherals and EALLOW Protection..........................................................................................................833
7.2.4 CLA Tasks and Interrupt Vectors............................................................................................................................. 834
7.3 CLA, DMA, and CPU Arbitration.................................................................................................................................... 838
7.3.1 CLA Message RAM................................................................................................................................................. 838
7.3.2 CLA Program Memory.............................................................................................................................................839
7.3.3 CLA Data Memory................................................................................................................................................... 840
7.3.4 Peripheral Registers (ePWM, HRPWM, Comparator).............................................................................................840
7.4 CLA Configuration and Debug....................................................................................................................................... 841
7.4.1 Building a CLA Application...................................................................................................................................... 841
7.4.2 Typical CLA Initialization Sequence........................................................................................................................ 841
7.4.3 Debugging CLA Code..............................................................................................................................................842
7.4.4 CLA Illegal Opcode Behavior.................................................................................................................................. 843
7.4.5 Resetting the CLA................................................................................................................................................... 844
7.5 Pipeline.......................................................................................................................................................................... 844
7.5.1 Pipeline Overview....................................................................................................................................................844
7.5.2 CLA Pipeline Alignment...........................................................................................................................................845
7.5.3 Parallel Instructions................................................................................................................................................. 849
7.5.4 CLA Task Execution Latency...................................................................................................................................849
7.6 Software......................................................................................................................................................................... 850
7.6.1 CLA Registers to Driverlib Functions.......................................................................................................................850
7.6.2 CLA Examples.........................................................................................................................................................852
7.7 Instruction Set................................................................................................................................................................ 857
7.7.1 Instruction Descriptions........................................................................................................................................... 857
7.7.2 Addressing Modes and Encoding............................................................................................................................858
7.7.3 Instructions.............................................................................................................................................................. 861
7.8 CLA Registers................................................................................................................................................................ 988
7.8.1 CLA Base Address Table.........................................................................................................................................988
7.8.2 CLA_ONLY_REGS Registers..................................................................................................................................989
7.8.3 CLA_SOFTINT_REGS Registers............................................................................................................................998
7.8.4 CLA_REGS Registers........................................................................................................................................... 1002
8 Neural-network Processing Unit (NPU).......................................................................................................................... 1051
8.1 Introduction.................................................................................................................................................................. 1052
8.1.1 NPU Related Collateral......................................................................................................................................... 1052
9 Dual-Clock Comparator (DCC).........................................................................................................................................1053
9.1 Introduction.................................................................................................................................................................. 1054
9.1.1 Features................................................................................................................................................................ 1054
9.1.2 Block Diagram....................................................................................................................................................... 1054
9.2 Module Operation.........................................................................................................................................................1055
9.2.1 Configuring DCC Counters....................................................................................................................................1056
9.2.2 Single-Shot Measurement Mode........................................................................................................................... 1057
9.2.3 Continuous Monitoring Mode.................................................................................................................................1058
9.2.4 Error Conditions.....................................................................................................................................................1059
9.3 Interrupts...................................................................................................................................................................... 1061
9.4 Software....................................................................................................................................................................... 1062
9.4.1 DCC Registers to Driverlib Functions....................................................................................................................1062
9.4.2 DCC Examples...................................................................................................................................................... 1062
9.5 DCC Registers............................................................................................................................................................. 1064
9.5.1 DCC Base Address Table......................................................................................................................................1064
9.5.2 DCC_REGS Registers.......................................................................................................................................... 1065
10 General-Purpose Input/Output (GPIO)..........................................................................................................................1076
10.1 Introduction................................................................................................................................................................ 1077
10.1.1 GPIO Related Collateral...................................................................................................................................... 1078
10.2 Configuration Overview..............................................................................................................................................1079
10.3 Digital Inputs on ADC Pins (AIOs)............................................................................................................................. 1080
10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)....................................................................................................1080
10.5 Digital General-Purpose I/O Control.......................................................................................................................... 1082
10.6 Input Qualification...................................................................................................................................................... 1083
10.6.1 No Synchronization (Asynchronous Input).......................................................................................................... 1083
10.6.2 Synchronization to SYSCLKOUT Only................................................................................................................1083
10.6.3 Qualification Using a Sampling Window..............................................................................................................1084

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10.7 USB Signals............................................................................................................................................................... 1088

10.8 PMBUS and I2C Signals............................................................................................................................................ 1088
10.9 GPIO and Peripheral Muxing..................................................................................................................................... 1089
10.9.1 GPIO Muxing....................................................................................................................................................... 1089
10.9.2 Peripheral Muxing................................................................................................................................................1094
10.10 Internal Pullup Configuration Requirements............................................................................................................ 1096
10.11 Software................................................................................................................................................................... 1096
10.11.1 GPIO Registers to Driverlib Functions............................................................................................................... 1096
10.11.2 GPIO Examples................................................................................................................................................. 1101
10.11.3 LED Examples................................................................................................................................................... 1102
10.12 GPIO Registers........................................................................................................................................................ 1102
10.12.1 GPIO Base Address Table................................................................................................................................. 1102
10.12.2 GPIO_CTRL_REGS Registers.......................................................................................................................... 1103
10.12.3 GPIO_DATA_REGS Registers.......................................................................................................................... 1264
10.12.4 GPIO_DATA_READ_REGS Registers.............................................................................................................. 1311
11 Crossbar (X-BAR)........................................................................................................................................................... 1317
11.1 Input X-BAR and CLB Input X-BAR ...........................................................................................................................1318
11.1.1 CLB Input X-BAR................................................................................................................................................. 1321
11.2 ePWM , CLB, and GPIO Output X-BAR..................................................................................................................... 1322
11.2.1 ePWM X-BAR...................................................................................................................................................... 1322
11.2.2 CLB X-BAR.......................................................................................................................................................... 1324
11.2.3 GPIO Output X-BAR............................................................................................................................................ 1327
11.2.4 X-BAR Flags........................................................................................................................................................ 1329
11.3 Software..................................................................................................................................................................... 1331
11.3.1 INPUTXBAR Registers to Driverlib Functions..................................................................................................... 1331
11.3.2 EPWMXBAR Registers to Driverlib Functions..................................................................................................... 1331
11.3.3 CLBXBAR Registers to Driverlib Functions......................................................................................................... 1333
11.3.4 OUTPUTXBAR Registers to Driverlib Functions................................................................................................. 1334
11.3.5 XBAR Registers to Driverlib Functions................................................................................................................ 1335
11.4 XBAR Registers..........................................................................................................................................................1336
11.4.1 XBAR Base Address Table.................................................................................................................................. 1336
11.4.2 INPUT_XBAR_REGS Registers.......................................................................................................................... 1337
11.4.3 XBAR_REGS Registers.......................................................................................................................................1356
11.4.4 EPWM_XBAR_REGS Registers..........................................................................................................................1380
11.4.5 CLB_XBAR_REGS Registers..............................................................................................................................1473
11.4.6 OUTPUT_XBAR_REGS Registers...................................................................................................................... 1566
11.4.7 OUTPUT_XBAR_REGS Registers...................................................................................................................... 1667
12 Direct Memory Access (DMA)........................................................................................................................................1768
12.1 Introduction................................................................................................................................................................ 1769
12.1.1 Features.............................................................................................................................................................. 1769
12.1.2 Block Diagram..................................................................................................................................................... 1770
12.2 Architecture................................................................................................................................................................ 1771
12.2.1 Peripheral Interrupt Event Trigger Sources......................................................................................................... 1771
12.2.2 DMA Bus............................................................................................................................................................. 1775
12.3 Address Pointer and Transfer Control........................................................................................................................1776
12.4 Pipeline Timing and Throughput................................................................................................................................ 1782
12.5 CPU and CLA Arbitration........................................................................................................................................... 1783
12.6 Channel Priority..........................................................................................................................................................1784
12.6.1 Round-Robin Mode............................................................................................................................................. 1784
12.6.2 Channel 1 High-Priority Mode............................................................................................................................. 1785
12.7 Overrun Detection Feature.........................................................................................................................................1785
12.8 Software..................................................................................................................................................................... 1786
12.8.1 DMA Registers to Driverlib Functions..................................................................................................................1786
12.8.2 DMA Examples....................................................................................................................................................1787
12.9 DMA Registers........................................................................................................................................................... 1788
12.9.1 DMA Base Address Table....................................................................................................................................1788
12.9.2 DMA_REGS Registers........................................................................................................................................ 1789
12.9.3 DMA_CH_REGS Registers................................................................................................................................. 1794
13 Embedded Real-time Analysis and Diagnostic (ERAD).............................................................................................. 1821
13.1 Introduction................................................................................................................................................................ 1822
13.1.1 ERAD Related Collateral..................................................................................................................................... 1822

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13.2 Enhanced Bus Comparator Unit................................................................................................................................ 1823

13.2.1 Enhanced Bus Comparator Unit Operations....................................................................................................... 1823
13.2.2 Event Masking and Exporting..............................................................................................................................1824
13.3 System Event Counter Unit........................................................................................................................................1825
13.3.1 System Event Counter Modes.............................................................................................................................1825
13.3.2 Reset on Event.................................................................................................................................................... 1830
13.3.3 Operation Conditions...........................................................................................................................................1830
13.4 ERAD Ownership, Initialization and Reset.................................................................................................................1831
13.5 ERAD Programming Sequence................................................................................................................................. 1832
13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence....................................................... 1832
13.5.2 Timer and Counter Programming Sequence....................................................................................................... 1833
13.6 Cyclic Redundancy Check Unit..................................................................................................................................1833
13.6.1 CRC Unit Qualifier............................................................................................................................................... 1834
13.6.2 CRC Unit Programming Sequence......................................................................................................................1835
13.7 Program Counter Trace..............................................................................................................................................1836
13.7.1 Functional Block Diagram....................................................................................................................................1837
13.7.2 Trace Qualification Modes................................................................................................................................... 1838
13.7.3 Trace Memory......................................................................................................................................................1842
13.7.4 Trace Input Signal Conditioning...........................................................................................................................1843
13.7.5 PC Trace Software Operation..............................................................................................................................1844
13.7.6 Trace Operation in Debug Mode......................................................................................................................... 1844
13.8 Software..................................................................................................................................................................... 1845
13.8.1 ERAD Registers to Driverlib Functions................................................................................................................1845
13.8.2 ERAD Examples..................................................................................................................................................1847
13.9 ERAD Registers......................................................................................................................................................... 1855
13.9.1 ERAD Base Address Table..................................................................................................................................1855
13.9.2 ERAD_GLOBAL_REGS Registers......................................................................................................................1856
13.9.3 ERAD_HWBP_REGS Registers......................................................................................................................... 1879
13.9.4 ERAD_COUNTER_REGS Registers.................................................................................................................. 1886
13.9.5 ERAD_CRC_GLOBAL_REGS Registers............................................................................................................ 1897
13.9.6 ERAD_CRC_REGS Registers............................................................................................................................ 1900
13.9.7 PCTRACE_REGS Registers............................................................................................................................... 1904
13.9.8 PCTRACE_BUFFER_REGS Registers............................................................................................................... 1911
14 Analog Subsystem......................................................................................................................................................... 1913
14.1 Introduction................................................................................................................................................................ 1914
14.1.1 Features.............................................................................................................................................................. 1914
14.1.2 Block Diagram..................................................................................................................................................... 1914
14.2 Optimizing Power-Up Time........................................................................................................................................ 1919
14.3 Digital Inputs on ADC Pins (AIOs)............................................................................................................................. 1919
14.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)....................................................................................................1919
14.5 Analog Pins and Internal Connections....................................................................................................................... 1922
14.6 Software..................................................................................................................................................................... 1926
14.6.1 ASYSCTL Registers to Driverlib Functions......................................................................................................... 1926
14.7 ASBSYS Registers.....................................................................................................................................................1928
14.7.1 ASBSYS Base Address Table............................................................................................................................. 1928
14.7.2 ANALOG_SUBSYS_REGS Registers.................................................................................................................1929
15 Analog-to-Digital Converter (ADC)................................................................................................................................1966
15.1 Introduction................................................................................................................................................................ 1967
15.1.1 ADC Related Collateral....................................................................................................................................... 1967
15.1.2 Features.............................................................................................................................................................. 1968
15.1.3 Block Diagram..................................................................................................................................................... 1969
15.2 ADC Configurability....................................................................................................................................................1970
15.2.1 Clock Configuration............................................................................................................................................. 1970
15.2.2 Resolution............................................................................................................................................................1970
15.2.3 Voltage Reference............................................................................................................................................... 1971
15.2.4 Signal Mode.........................................................................................................................................................1972
15.2.5 Expected Conversion Results............................................................................................................................. 1972
15.2.6 Interpreting Conversion Results.......................................................................................................................... 1972
15.3 SOC Principle of Operation........................................................................................................................................1973
15.3.1 SOC Configuration.............................................................................................................................................. 1974
15.3.2 Trigger Operation.................................................................................................................................................1974

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15.3.3 ADC Acquisition (Sample and Hold) Window......................................................................................................1982

15.3.4 Sample Capacitor Reset......................................................................................................................................1983
15.3.5 ADC Input Models............................................................................................................................................... 1983
15.3.6 Channel Selection............................................................................................................................................... 1984
15.4 SOC Configuration Examples.................................................................................................................................... 1991
15.4.1 Single Conversion from ePWM Trigger............................................................................................................... 1991
15.4.2 Oversampled Conversion from ePWM Trigger....................................................................................................1991
15.4.3 Multiple Conversions from CPU Timer Trigger.................................................................................................... 1992
15.4.4 Software Triggering of SOCs...............................................................................................................................1993
15.5 ADC Conversion Priority............................................................................................................................................ 1993
15.6 Burst Mode.................................................................................................................................................................1996
15.6.1 Burst Mode Example........................................................................................................................................... 1996
15.6.2 Burst Mode Priority Example............................................................................................................................... 1997
15.7 EOC and Interrupt Operation..................................................................................................................................... 1998
15.7.1 Interrupt Overflow................................................................................................................................................ 1999
15.7.2 Continue to Interrupt Mode..................................................................................................................................1999
15.7.3 Early Interrupt Configuration Mode......................................................................................................................2000
15.8 Post-Processing Blocks............................................................................................................................................. 2001
15.8.1 PPB Offset Correction......................................................................................................................................... 2002
15.8.2 PPB Error Calculation..........................................................................................................................................2002
15.8.3 PPB Result Delta Calculation.............................................................................................................................. 2002
15.8.4 PPB Limit Detection and Zero-Crossing Detection..............................................................................................2003
15.8.5 PPB Sample Delay Capture................................................................................................................................ 2006
15.8.6 PPB Oversampling.............................................................................................................................................. 2006
15.9 Opens/Shorts Detection Circuit (OSDETECT)...........................................................................................................2008
15.9.1 Implementation.................................................................................................................................................... 2009
15.9.2 Detecting an Open Input Pin............................................................................................................................... 2009
15.9.3 Detecting a Shorted Input Pin..............................................................................................................................2009
15.10 Power-Up Sequence................................................................................................................................................ 2010
15.11 ADC Calibration........................................................................................................................................................2010
15.11.1 ADC Zero Offset Calibration.............................................................................................................................. 2010
15.12 ADC Timings............................................................................................................................................................ 2011
15.12.1 ADC Timing Diagrams....................................................................................................................................... 2011
15.12.2 Post-Processing Block Timings......................................................................................................................... 2015
15.13 Additional Information.............................................................................................................................................. 2017
15.13.1 Ensuring Synchronous Operation......................................................................................................................2017
15.13.2 Choosing an Acquisition Window Duration........................................................................................................2020
15.13.3 Achieving Simultaneous Sampling.................................................................................................................... 2022
15.13.4 Result Register Mapping................................................................................................................................... 2022
15.13.5 Internal Temperature Sensor............................................................................................................................. 2022
15.13.6 Designing an External Reference Circuit...........................................................................................................2023
15.13.7 ADC-DAC Loopback Testing............................................................................................................................. 2023
15.13.8 Internal Test Mode............................................................................................................................................. 2025
15.13.9 ADC Gain and Offset Calibration.......................................................................................................................2025
15.14 Software................................................................................................................................................................... 2026
15.14.1 ADC Registers to Driverlib Functions................................................................................................................ 2026
15.14.2 ADC Examples.................................................................................................................................................. 2034
15.15 ADC Registers......................................................................................................................................................... 2039
15.15.1 ADC Base Address Table.................................................................................................................................. 2039
15.15.2 ADC_RESULT_REGS Registers.......................................................................................................................2040
15.15.3 ADC_REGS Registers.......................................................................................................................................2086
16 Buffered Digital-to-Analog Converter (DAC)................................................................................................................2284
16.1 Introduction................................................................................................................................................................ 2285
16.1.1 DAC Related Collateral....................................................................................................................................... 2285
16.1.2 Features.............................................................................................................................................................. 2285
16.1.3 Block Diagram..................................................................................................................................................... 2285
16.2 Using the DAC........................................................................................................................................................... 2286
16.2.1 Initialization Sequence.........................................................................................................................................2286
16.2.2 DAC Offset Adjustment........................................................................................................................................2287
16.2.3 EPWMSYNCPER Signal..................................................................................................................................... 2287
16.3 Lock Registers........................................................................................................................................................... 2287

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16.4 Software..................................................................................................................................................................... 2288

16.4.1 DAC Registers to Driverlib Functions.................................................................................................................. 2288
16.4.2 DAC Examples.................................................................................................................................................... 2288
16.5 DAC Registers........................................................................................................................................................... 2289
16.5.1 DAC Base Address Table.................................................................................................................................... 2289
16.5.2 DAC_REGS Registers.........................................................................................................................................2290
17 Comparator Subsystem (CMPSS)................................................................................................................................. 2298
17.1 Introduction................................................................................................................................................................ 2299
17.1.1 CMPSS Related Collateral.................................................................................................................................. 2299
17.1.2 Features.............................................................................................................................................................. 2299
17.1.3 Block Diagram..................................................................................................................................................... 2300
17.2 Comparator................................................................................................................................................................ 2300
17.3 Reference DAC.......................................................................................................................................................... 2301
17.4 Ramp Generator........................................................................................................................................................ 2302
17.4.1 Ramp Generator Overview..................................................................................................................................2302
17.4.2 Ramp Generator Behavior...................................................................................................................................2303
17.4.3 Ramp Generator Behavior at Corner Cases....................................................................................................... 2304
17.5 Digital Filter................................................................................................................................................................ 2306
17.5.1 Filter Initialization Sequence................................................................................................................................2307
17.6 Using the CMPSS...................................................................................................................................................... 2307
17.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals ..............................................................................2307
17.6.2 Synchronizer, Digital Filter, and Latch Delays..................................................................................................... 2307
17.6.3 Calibrating the CMPSS .......................................................................................................................................2308
17.6.4 Enabling and Disabling the CMPSS Clock.......................................................................................................... 2308
17.7 CMPSS DAC Output.................................................................................................................................................. 2309
17.8 Software..................................................................................................................................................................... 2309
17.8.1 CMPSS Registers to Driverlib Functions.............................................................................................................2309
17.8.2 CMPSS Examples............................................................................................................................................... 2312
17.9 CMPSS Registers...................................................................................................................................................... 2313
17.9.1 CMPSS Base Address Table...............................................................................................................................2313
17.9.2 CMPSS_REGS Registers................................................................................................................................... 2314
18 Programmable Gain Amplifier (PGA)............................................................................................................................2356
18.1 Programmable Gain Amplifier (PGA) Overview......................................................................................................... 2357
18.1.1 Features.............................................................................................................................................................. 2357
18.1.2 Block Diagram..................................................................................................................................................... 2357
18.2 Linear Output Range..................................................................................................................................................2358
18.3 Gain Values................................................................................................................................................................2358
18.4 Modes of Operation....................................................................................................................................................2359
18.4.1 Buffer Mode......................................................................................................................................................... 2359
18.4.2 Standalone Mode................................................................................................................................................ 2360
18.4.3 Non-inverting Mode............................................................................................................................................. 2361
18.4.4 Subtractor Mode.................................................................................................................................................. 2362
18.5 External Filtering........................................................................................................................................................ 2363
18.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor................................................................2363
18.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor............................................. 2364
18.6 Error Calibration......................................................................................................................................................... 2365
18.6.1 Offset Error.......................................................................................................................................................... 2365
18.6.2 Gain Error............................................................................................................................................................ 2365
18.7 Chopping Feature...................................................................................................................................................... 2366
18.8 Enabling and Disabling the PGA Clock......................................................................................................................2367
18.9 Lock Register............................................................................................................................................................. 2367
18.10 Analog Front-End Integration................................................................................................................................... 2368
18.10.1 Buffered DAC.....................................................................................................................................................2368
18.10.2 Analog-to-Digital Converter (ADC) ................................................................................................................... 2369
18.10.3 Comparator Subsystem (CMPSS).....................................................................................................................2369
18.10.4 PGA_NEG_SHARED Feature...........................................................................................................................2369
18.10.5 Alternate Functions............................................................................................................................................2371
18.11 Examples..................................................................................................................................................................2372
18.11.1 Non-Inverting Amplifier Using Non-Inverting Mode............................................................................................2372
18.11.2 Buffer Mode....................................................................................................................................................... 2372
18.11.3 Low-Side Current Sensing................................................................................................................................. 2373

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18.11.4 Bidirectional Current Sensing............................................................................................................................ 2374

18.12 Software................................................................................................................................................................... 2375
18.12.1 PGA Registers to Driverlib Functions................................................................................................................ 2375
18.12.2 PGA Examples.................................................................................................................................................. 2375
18.13 PGA Registers......................................................................................................................................................... 2376
18.13.1 PGA Base Address Table.................................................................................................................................. 2376
18.13.2 PGA_REGS Registers.......................................................................................................................................2377
19 Enhanced Pulse Width Modulator (ePWM)...................................................................................................................2383
19.1 Introduction................................................................................................................................................................ 2384
19.1.1 EPWM Related Collateral....................................................................................................................................2385
19.1.2 Submodule Overview.......................................................................................................................................... 2386
19.2 Configuring Device Pins.............................................................................................................................................2391
19.3 ePWM Modules Overview..........................................................................................................................................2391
19.4 Time-Base (TB) Submodule.......................................................................................................................................2393
19.4.1 Purpose of the Time-Base Submodule................................................................................................................2393
19.4.2 Controlling and Monitoring the Time-Base Submodule....................................................................................... 2394
19.4.3 Calculating PWM Period and Frequency.............................................................................................................2396
19.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules..................................................................... 2400
19.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules............................................... 2401
19.4.6 Time-Base Counter Modes and Timing Waveforms............................................................................................ 2401
19.4.7 Global Load......................................................................................................................................................... 2406
19.5 Counter-Compare (CC) Submodule...........................................................................................................................2408
19.5.1 Purpose of the Counter-Compare Submodule.................................................................................................... 2408
19.5.2 Controlling and Monitoring the Counter-Compare Submodule............................................................................2409
19.5.3 Operational Highlights for the Counter-Compare Submodule............................................................................. 2410
19.5.4 Count Mode Timing Waveforms...........................................................................................................................2411
19.6 Action-Qualifier (AQ) Submodule...............................................................................................................................2414
19.6.1 Purpose of the Action-Qualifier Submodule........................................................................................................ 2414
19.6.2 Action-Qualifier Submodule Control and Status Register Definitions..................................................................2415
19.6.3 Action-Qualifier Event Priority..............................................................................................................................2417
19.6.4 AQCTLA and AQCTLB Shadow Mode Operations............................................................................................. 2418
19.6.5 Configuration Requirements for Common Waveforms........................................................................................ 2420
19.7 Dead-Band Generator (DB) Submodule.................................................................................................................... 2427
19.7.1 Purpose of the Dead-Band Submodule...............................................................................................................2427
19.7.2 Dead-band Submodule Additional Operating Modes.......................................................................................... 2428
19.7.3 Operational Highlights for the Dead-Band Submodule........................................................................................2430
19.8 PWM Chopper (PC) Submodule................................................................................................................................ 2434
19.8.1 Purpose of the PWM Chopper Submodule......................................................................................................... 2434
19.8.2 Operational Highlights for the PWM Chopper Submodule.................................................................................. 2434
19.8.3 Waveforms...........................................................................................................................................................2435
19.9 Trip-Zone (TZ) Submodule.........................................................................................................................................2438
19.9.1 Purpose of the Trip-Zone Submodule..................................................................................................................2438
19.9.2 Operational Highlights for the Trip-Zone Submodule.......................................................................................... 2439
19.9.3 Generating Trip Event Interrupts......................................................................................................................... 2441
19.10 Event-Trigger (ET) Submodule................................................................................................................................ 2444
19.10.1 Operational Overview of the ePWM Event-Trigger Submodule........................................................................ 2445
19.11 Digital Compare (DC) Submodule............................................................................................................................ 2449
19.11.1 Purpose of the Digital Compare Submodule......................................................................................................2451
19.11.2 Enhanced Trip Action Using CMPSS.................................................................................................................2451
19.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis............................................................................ 2451
19.11.4 Operation Highlights of the Digital Compare Submodule.................................................................................. 2452
19.12 ePWM Crossbar (X-BAR)........................................................................................................................................ 2459
19.13 Applications to Power Topologies............................................................................................................................ 2460
19.13.1 Overview of Multiple Modules............................................................................................................................2460
19.13.2 Key Configuration Capabilities.......................................................................................................................... 2461
19.13.3 Controlling Multiple Buck Converters With Independent Frequencies.............................................................. 2462
19.13.4 Controlling Multiple Buck Converters With Same Frequencies......................................................................... 2464
19.13.5 Controlling Multiple Half H-Bridge (HHB) Converters........................................................................................2466
19.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)...................................................................... 2468
19.13.7 Practical Applications Using Phase Control Between PWM Modules............................................................... 2470
19.13.8 Controlling a 3-Phase Interleaved DC/DC Converter........................................................................................ 2471

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19.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter.................................................................. 2474
19.13.10 Controlling a Peak Current Mode Controlled Buck Module............................................................................. 2476
19.13.11 Controlling H-Bridge LLC Resonant Converter................................................................................................2477
19.14 Register Lock Protection.......................................................................................................................................... 2478
19.15 High-Resolution Pulse Width Modulator (HRPWM)................................................................................................. 2479
19.15.1 Operational Description of HRPWM.................................................................................................................. 2481
19.15.2 SFO Library Software - SFO_TI_Build_V8.lib................................................................................................... 2502
19.16 Software................................................................................................................................................................... 2505
19.16.1 EPWM Registers to Driverlib Functions............................................................................................................ 2505
19.16.2 HRPWM Registers to Driverlib Functions..........................................................................................................2512
19.16.3 EPWM Examples...............................................................................................................................................2516
19.16.4 HRPWM Examples............................................................................................................................................2521
19.17 EPWM Registers......................................................................................................................................................2524
19.17.1 EPWM Base Address Table.............................................................................................................................. 2524
19.17.2 EPWM_REGS Registers................................................................................................................................... 2525
20 Enhanced Capture (eCAP)............................................................................................................................................. 2655
20.1 Introduction................................................................................................................................................................ 2656
20.1.1 Features.............................................................................................................................................................. 2656
20.1.2 ECAP Related Collateral..................................................................................................................................... 2656
20.2 Description................................................................................................................................................................. 2657
20.3 Configuring Device Pins for the eCAP....................................................................................................................... 2658
20.4 Capture and APWM Operating Mode........................................................................................................................ 2661
20.5 Capture Mode Description......................................................................................................................................... 2663
20.5.1 Event Prescaler................................................................................................................................................... 2664
20.5.2 Edge Polarity Select and Qualifier.......................................................................................................................2664
20.5.3 Continuous/One-Shot Control............................................................................................................................. 2665
20.5.4 32-Bit Counter and Phase Control.......................................................................................................................2666
20.5.5 CAP1-CAP4 Registers........................................................................................................................................ 2666
20.5.6 eCAP Synchronization.........................................................................................................................................2666
20.5.7 Interrupt Control...................................................................................................................................................2667
20.5.8 DMA Interrupt...................................................................................................................................................... 2669
20.5.9 Shadow Load and Lockout Control..................................................................................................................... 2669
20.5.10 APWM Mode Operation.....................................................................................................................................2669
20.6 Application of the eCAP Module................................................................................................................................ 2671
20.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger.................................................................... 2671
20.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger.................................................2672
20.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger..................................................................2673
20.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger.............................................. 2674
20.7 Application of the APWM Mode................................................................................................................................. 2675
20.7.1 Example 1 - Simple PWM Generation (Independent Channels)......................................................................... 2675
20.8 Software..................................................................................................................................................................... 2676
20.8.1 ECAP Registers to Driverlib Functions................................................................................................................2676
20.8.2 ECAP Examples.................................................................................................................................................. 2677
20.9 ECAP Registers......................................................................................................................................................... 2678
20.9.1 ECAP Base Address Table..................................................................................................................................2678
20.9.2 ECAP_REGS Registers...................................................................................................................................... 2679
21 Enhanced Quadrature Encoder Pulse (eQEP)............................................................................................................. 2698
21.1 Introduction................................................................................................................................................................ 2699
21.1.1 EQEP Related Collateral..................................................................................................................................... 2701
21.2 Configuring Device Pins.............................................................................................................................................2701
21.3 Description................................................................................................................................................................. 2702
21.3.1 EQEP Inputs........................................................................................................................................................2702
21.3.2 Functional Description......................................................................................................................................... 2705
21.3.3 eQEP Memory Map............................................................................................................................................. 2706
21.4 Quadrature Decoder Unit (QDU)................................................................................................................................2707
21.4.1 Position Counter Input Modes............................................................................................................................. 2707
21.4.2 eQEP Input Polarity Selection............................................................................................................................. 2710
21.4.3 Position-Compare Sync Output........................................................................................................................... 2710
21.5 Position Counter and Control Unit (PCCU)................................................................................................................ 2710
21.5.1 Position Counter Operating Modes..................................................................................................................... 2710
21.5.2 Position Counter Latch........................................................................................................................................ 2713

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21.5.3 Position Counter Initialization.............................................................................................................................. 2715

21.5.4 eQEP Position-compare Unit...............................................................................................................................2716
21.6 eQEP Edge Capture Unit........................................................................................................................................... 2718
21.7 eQEP Watchdog.........................................................................................................................................................2722
21.8 eQEP Unit Timer Base............................................................................................................................................... 2722
21.9 QMA Module.............................................................................................................................................................. 2723
21.9.1 Modes of Operation............................................................................................................................................. 2724
21.9.2 Interrupt and Error Generation............................................................................................................................ 2725
21.10 eQEP Interrupt Structure..........................................................................................................................................2726
21.11 Software................................................................................................................................................................... 2727
21.11.1 EQEP Registers to Driverlib Functions.............................................................................................................. 2727
21.11.2 EQEP Examples................................................................................................................................................ 2728
21.12 EQEP Registers....................................................................................................................................................... 2731
21.12.1 EQEP Base Address Table................................................................................................................................2731
21.12.2 EQEP_REGS Registers.................................................................................................................................... 2732
22 Serial Peripheral Interface (SPI).................................................................................................................................... 2770
22.1 Introduction................................................................................................................................................................ 2771
22.1.1 Features.............................................................................................................................................................. 2771
22.1.2 SPI Related Collateral......................................................................................................................................... 2771
22.1.3 Block Diagram..................................................................................................................................................... 2772
22.2 System-Level Integration........................................................................................................................................... 2773
22.2.1 SPI Module Signals............................................................................................................................................. 2773
22.2.2 Configuring Device Pins...................................................................................................................................... 2774
22.2.3 SPI Interrupts.......................................................................................................................................................2774
22.2.4 DMA Support....................................................................................................................................................... 2776
22.3 SPI Operation.............................................................................................................................................................2777
22.3.1 Introduction to Operation..................................................................................................................................... 2777
22.3.2 Controller Mode................................................................................................................................................... 2778
22.3.3 Peripheral Mode.................................................................................................................................................. 2779
22.3.4 Data Format.........................................................................................................................................................2781
22.3.5 Baud Rate Selection............................................................................................................................................2782
22.3.6 SPI Clocking Schemes........................................................................................................................................ 2783
22.3.7 SPI FIFO Description...........................................................................................................................................2784
22.3.8 SPI DMA Transfers..............................................................................................................................................2785
22.3.9 SPI High-Speed Mode.........................................................................................................................................2786
22.3.10 SPI 3-Wire Mode Description............................................................................................................................ 2786
22.4 Programming Procedure............................................................................................................................................ 2788
22.4.1 Initialization Upon Reset......................................................................................................................................2788
22.4.2 Configuring the SPI............................................................................................................................................. 2788
22.4.3 Configuring the SPI for High-Speed Mode.......................................................................................................... 2789
22.4.4 Data Transfer Example........................................................................................................................................2790
22.4.5 SPI 3-Wire Mode Code Examples.......................................................................................................................2791
22.4.6 SPI STEINV Bit in Digital Audio Transfers...........................................................................................................2793
22.5 Software..................................................................................................................................................................... 2794
22.5.1 SPI Registers to Driverlib Functions....................................................................................................................2794
22.5.2 SPI Examples...................................................................................................................................................... 2795
22.6 SPI Registers............................................................................................................................................................. 2798
22.6.1 SPI Base Address Table......................................................................................................................................2798
22.6.2 SPI_REGS Registers.......................................................................................................................................... 2799
23 Serial Communications Interface (SCI)........................................................................................................................ 2818
23.1 Introduction................................................................................................................................................................ 2819
23.1.1 Features.............................................................................................................................................................. 2819
23.1.2 SCI Related Collateral......................................................................................................................................... 2820
23.1.3 Block Diagram..................................................................................................................................................... 2820
23.2 Architecture................................................................................................................................................................ 2820
23.3 SCI Module Signal Summary..................................................................................................................................... 2820
23.4 Configuring Device Pins.............................................................................................................................................2822
23.5 Multiprocessor and Asynchronous Communication Modes....................................................................................... 2822
23.6 SCI Programmable Data Format................................................................................................................................2823
23.7 SCI Multiprocessor Communication...........................................................................................................................2824
23.7.1 Recognizing the Address Byte............................................................................................................................ 2824

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23.7.2 Controlling the SCI TX and RX Features.............................................................................................................2824

23.7.3 Receipt Sequence............................................................................................................................................... 2824
23.8 Idle-Line Multiprocessor Mode................................................................................................................................... 2825
23.8.1 Idle-Line Mode Steps...........................................................................................................................................2825
23.8.2 Block Start Signal................................................................................................................................................ 2826
23.8.3 Wake-Up Temporary (WUT) Flag........................................................................................................................ 2826
23.8.4 Receiver Operation..............................................................................................................................................2826
23.9 Address-Bit Multiprocessor Mode.............................................................................................................................. 2827
23.9.1 Sending an Address............................................................................................................................................ 2827
23.10 SCI Communication Format.....................................................................................................................................2828
23.10.1 Receiver Signals in Communication Modes...................................................................................................... 2829
23.10.2 Transmitter Signals in Communication Modes.................................................................................................. 2830
23.11 SCI Port Interrupts....................................................................................................................................................2831
23.11.1 Break Detect...................................................................................................................................................... 2832
23.12 SCI Baud Rate Calculations.....................................................................................................................................2832
23.13 SCI Enhanced Features...........................................................................................................................................2833
23.13.1 SCI FIFO Description........................................................................................................................................ 2833
23.13.2 SCI Auto-Baud...................................................................................................................................................2835
23.13.3 Autobaud-Detect Sequence.............................................................................................................................. 2835
23.14 Software................................................................................................................................................................... 2836
23.14.1 SCI Registers to Driverlib Functions..................................................................................................................2836
23.14.2 SCI Examples....................................................................................................................................................2838
23.15 SCI Registers........................................................................................................................................................... 2840
23.15.1 SCI Base Address Table....................................................................................................................................2840
23.15.2 SCI_REGS Registers........................................................................................................................................ 2841
24 Universal Serial Bus (USB) Controller..........................................................................................................................2863
24.1 Introduction................................................................................................................................................................ 2864
24.1.1 Features.............................................................................................................................................................. 2864
24.1.2 USB Related Collateral........................................................................................................................................2864
24.1.3 Block Diagram..................................................................................................................................................... 2865
24.2 Functional Description................................................................................................................................................2867
24.2.1 Operation as a Device......................................................................................................................................... 2867
24.2.2 Operation as a Host.............................................................................................................................................2872
24.2.3 DMA Operation....................................................................................................................................................2876
24.2.4 Address/Data Bus Bridge.................................................................................................................................... 2876
24.3 Initialization and Configuration................................................................................................................................... 2878
24.3.1 Pin Configuration................................................................................................................................................. 2878
24.3.2 Endpoint Configuration........................................................................................................................................ 2879
24.4 USB Global Interrupts................................................................................................................................................ 2879
24.5 Software..................................................................................................................................................................... 2880
24.5.1 USB Registers to Driverlib Functions.................................................................................................................. 2880
24.5.2 USB Examples.................................................................................................................................................... 2897
24.6 USB Registers............................................................................................................................................................2899
24.6.1 USB Base Address Table.................................................................................................................................... 2899
24.6.2 USB_REGS Registers.........................................................................................................................................2900
25 Fast Serial Interface (FSI)...............................................................................................................................................3047
25.1 Introduction................................................................................................................................................................ 3048
25.1.1 FSI Related Collateral......................................................................................................................................... 3048
25.1.2 FSI Features........................................................................................................................................................3048
25.2 System-level Integration.............................................................................................................................................3049
25.2.1 CPU Interface...................................................................................................................................................... 3049
25.2.2 Signal Description................................................................................................................................................3051
25.2.3 FSI Interrupts.......................................................................................................................................................3052
25.2.4 CLA Task Triggering............................................................................................................................................ 3054
25.2.5 DMA Interface......................................................................................................................................................3054
25.2.6 External Frame Trigger Mux................................................................................................................................ 3055
25.3 FSI Functional Description......................................................................................................................................... 3056
25.3.1 Introduction to Operation .................................................................................................................................... 3056
25.3.2 FSI Transmitter Module....................................................................................................................................... 3057
25.3.3 FSI Receiver Module........................................................................................................................................... 3063
25.3.4 Frame Format......................................................................................................................................................3069

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25.3.5 Flush Sequence...................................................................................................................................................3073

25.3.6 Internal Loopback................................................................................................................................................ 3074
25.3.7 CRC Generation.................................................................................................................................................. 3074
25.3.8 ECC Module........................................................................................................................................................ 3075
25.3.9 Tag Matching....................................................................................................................................................... 3076
25.3.10 User Data Filtering (UDATA Matching).............................................................................................................. 3076
25.3.11 TDM Configurations........................................................................................................................................... 3076
25.3.12 FSI Trigger Generation...................................................................................................................................... 3078
25.3.13 FSI-SPI Compatibility Mode.............................................................................................................................. 3080
25.4 FSI Programing Guide............................................................................................................................................... 3084
25.4.1 Establishing the Communication Link..................................................................................................................3084
25.4.2 Register Protection.............................................................................................................................................. 3086
25.4.3 Emulation Mode...................................................................................................................................................3086
25.5 Software..................................................................................................................................................................... 3087
25.5.1 FSI Registers to Driverlib Functions.................................................................................................................... 3087
25.5.2 FSI Examples...................................................................................................................................................... 3091
25.6 FSI Registers............................................................................................................................................................. 3097
25.6.1 FSI Base Address Table...................................................................................................................................... 3097
25.6.2 FSI_TX_REGS Registers.................................................................................................................................... 3098
25.6.3 FSI_RX_REGS Registers....................................................................................................................................3125
26 Inter-Integrated Circuit Module (I2C).............................................................................................................................3174
26.1 Introduction................................................................................................................................................................ 3175
26.1.1 I2C Related Collateral......................................................................................................................................... 3175
26.1.2 Features.............................................................................................................................................................. 3176
26.1.3 Features Not Supported...................................................................................................................................... 3176
26.1.4 Functional Overview............................................................................................................................................ 3177
26.1.5 Clock Generation.................................................................................................................................................3178
26.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)....................................................................................... 3179
26.2 Configuring Device Pins.............................................................................................................................................3180
26.3 I2C Module Operational Details................................................................................................................................. 3180
26.3.1 Input and Output Voltage Levels......................................................................................................................... 3180
26.3.2 Selecting Pullup Resistors...................................................................................................................................3180
26.3.3 Data Validity.........................................................................................................................................................3180
26.3.4 Operating Modes................................................................................................................................................. 3181
26.3.5 I2C Module START and STOP Conditions.......................................................................................................... 3185
26.3.6 Non-repeat Mode versus Repeat Mode.............................................................................................................. 3186
26.3.7 Serial Data Formats.............................................................................................................................................3186
26.3.8 Clock Synchronization......................................................................................................................................... 3189
26.3.9 Clock Stretching.................................................................................................................................................. 3190
26.3.10 Arbitration.......................................................................................................................................................... 3192
26.3.11 Digital Loopback Mode...................................................................................................................................... 3193
26.3.12 NACK Bit Generation.........................................................................................................................................3194
26.4 Interrupt Requests Generated by the I2C Module..................................................................................................... 3194
26.4.1 Basic I2C Interrupt Requests...............................................................................................................................3195
26.4.2 I2C FIFO Interrupts..............................................................................................................................................3197
26.5 Resetting or Disabling the I2C Module.......................................................................................................................3197
26.6 Software..................................................................................................................................................................... 3198
26.6.1 I2C Registers to Driverlib Functions.................................................................................................................... 3198
26.6.2 I2C Examples...................................................................................................................................................... 3199
26.7 I2C Registers............................................................................................................................................................. 3202
26.7.1 I2C Base Address Table...................................................................................................................................... 3202
26.7.2 I2C_REGS Registers...........................................................................................................................................3203
27 Power Management Bus Module (PMBus)................................................................................................................... 3227
27.1 Introduction................................................................................................................................................................ 3228
27.1.1 PMBUS Related Collateral.................................................................................................................................. 3228
27.1.2 Features.............................................................................................................................................................. 3228
27.1.3 Block Diagram..................................................................................................................................................... 3229
27.2 Configuring Device Pins.............................................................................................................................................3230
27.3 Target Mode Operation.............................................................................................................................................. 3230
27.3.1 Configuration....................................................................................................................................................... 3230
27.3.2 Message Handling...............................................................................................................................................3231

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27.4 Controller Mode Operation.........................................................................................................................................3241

27.4.1 Configuration....................................................................................................................................................... 3241
27.4.2 Message Handling...............................................................................................................................................3241
27.5 Software..................................................................................................................................................................... 3252
27.5.1 PMBUS Registers to Driverlib Functions.............................................................................................................3252
27.6 PMBUS Registers...................................................................................................................................................... 3253
27.6.1 PMBUS Base Address Table...............................................................................................................................3253
27.6.2 PMBUS_REGS Registers................................................................................................................................... 3254
28 Modular Controller Area Network (MCAN)................................................................................................................... 3275
28.1 MCAN Introduction.....................................................................................................................................................3276
28.1.1 MCAN Related Collateral.................................................................................................................................... 3276
28.1.2 MCAN Features...................................................................................................................................................3277
28.2 MCAN Environment................................................................................................................................................... 3277
28.3 CAN Network Basics..................................................................................................................................................3278
28.4 MCAN Integration.......................................................................................................................................................3279
28.5 MCAN Functional Description.................................................................................................................................... 3281
28.5.1 Module Clocking Requirements...........................................................................................................................3282
28.5.2 Interrupt Requests............................................................................................................................................... 3282
28.5.3 Operating Modes................................................................................................................................................. 3283
28.5.4 Transmitter Delay Compensation........................................................................................................................ 3286
28.5.5 Restricted Operation Mode..................................................................................................................................3288
28.5.6 Bus Monitoring Mode...........................................................................................................................................3288
28.5.7 Disabled Automatic Retransmission (DAR) Mode...............................................................................................3289
28.5.8 Clock Stop Mode................................................................................................................................................. 3289
28.5.9 Test Modes.......................................................................................................................................................... 3292
28.5.10 Timestamp Generation...................................................................................................................................... 3293
28.5.11 Timeout Counter................................................................................................................................................ 3295
28.5.12 Safety................................................................................................................................................................ 3295
28.5.13 Rx Handling....................................................................................................................................................... 3297
28.5.14 Tx Handling....................................................................................................................................................... 3303
28.5.15 FIFO Acknowledge Handling.............................................................................................................................3307
28.5.16 Message RAM................................................................................................................................................... 3307
28.6 Software..................................................................................................................................................................... 3318
28.6.1 MCAN Registers to Driverlib Functions............................................................................................................... 3318
28.6.2 MCAN Examples................................................................................................................................................. 3321
28.7 MCAN Registers........................................................................................................................................................ 3325
28.7.1 MCAN Base Address Table................................................................................................................................. 3325
28.7.2 MCANSS_REGS Registers.................................................................................................................................3326
28.7.3 MCAN_REGS Registers......................................................................................................................................3338
28.7.4 MCAN_ERROR_REGS Registers.......................................................................................................................3416
29 Local Interconnect Network (LIN)..................................................................................................................................3442
29.1 LIN Overview..............................................................................................................................................................3443
29.1.1 SCI Features....................................................................................................................................................... 3443
29.1.2 LIN Features........................................................................................................................................................3444
29.1.3 LIN Related Collateral......................................................................................................................................... 3444
29.1.4 Block Diagram..................................................................................................................................................... 3445
29.2 Serial Communications Interface Module.................................................................................................................. 3448
29.2.1 SCI Communication Formats.............................................................................................................................. 3448
29.2.2 SCI Interrupts...................................................................................................................................................... 3458
29.2.3 SCI DMA Interface...............................................................................................................................................3462
29.2.4 SCI Configurations.............................................................................................................................................. 3463
29.2.5 SCI Low-Power Mode..........................................................................................................................................3465
29.3 Local Interconnect Network Module...........................................................................................................................3466
29.3.1 LIN Communication Formats...............................................................................................................................3466
29.3.2 LIN Interrupts.......................................................................................................................................................3485
29.3.3 Servicing LIN Interrupts....................................................................................................................................... 3485
29.3.4 LIN DMA Interface............................................................................................................................................... 3486
29.3.5 LIN Configurations...............................................................................................................................................3486
29.4 Low-Power Mode....................................................................................................................................................... 3488
29.4.1 Entering Sleep Mode........................................................................................................................................... 3489
29.4.2 Wakeup................................................................................................................................................................3489

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29.4.3 Wakeup Timeouts................................................................................................................................................ 3490

29.5 Emulation Mode......................................................................................................................................................... 3490
29.6 Software..................................................................................................................................................................... 3491
29.6.1 LIN Registers to Driverlib Functions.................................................................................................................... 3491
29.6.2 LIN Examples...................................................................................................................................................... 3494
29.7 LIN Registers............................................................................................................................................................. 3496
29.7.1 LIN Base Address Table...................................................................................................................................... 3496
29.7.2 LIN_REGS Registers...........................................................................................................................................3497
30 Configurable Logic Block (CLB)....................................................................................................................................3552
30.1 Introduction................................................................................................................................................................ 3553
30.1.1 CLB Related Collateral........................................................................................................................................ 3553
30.2 Description................................................................................................................................................................. 3553
30.2.1 CLB Clock............................................................................................................................................................3555
30.3 CLB Input/Output Connection.................................................................................................................................... 3557
30.3.1 Overview..............................................................................................................................................................3557
30.3.2 CLB Input Selection.............................................................................................................................................3557
30.3.3 CLB Output Selection.......................................................................................................................................... 3565
30.3.4 CLB Output Signal Multiplexer............................................................................................................................ 3567
30.4 CLB Tile......................................................................................................................................................................3570
30.4.1 Static Switch Block.............................................................................................................................................. 3571
30.4.2 Counter Block...................................................................................................................................................... 3573
30.4.3 FSM Block........................................................................................................................................................... 3577
30.4.4 LUT4 Block.......................................................................................................................................................... 3579
30.4.5 Output LUT Block................................................................................................................................................ 3579
30.4.6 Asynchronous Output Conditioning (AOC) Block................................................................................................ 3580
30.4.7 High Level Controller (HLC)................................................................................................................................ 3583
30.5 CPU Interface.............................................................................................................................................................3588
30.5.1 Register Description............................................................................................................................................ 3588
30.5.2 Non-Memory Mapped Registers..........................................................................................................................3589
30.6 DMA Access...............................................................................................................................................................3589
30.7 CLB Data Export Through SPI RX Buffer...................................................................................................................3590
30.8 Software..................................................................................................................................................................... 3591
30.8.1 CLB Registers to Driverlib Functions...................................................................................................................3591
30.8.2 CLB Examples.....................................................................................................................................................3594
30.9 CLB Registers............................................................................................................................................................ 3600
30.9.1 CLB Base Address Table.....................................................................................................................................3600
30.9.2 CLB_LOGIC_CONFIG_REGS Registers............................................................................................................ 3601
30.9.3 CLB_LOGIC_CONTROL_REGS Registers........................................................................................................ 3653
30.9.4 CLB_DATA_EXCHANGE_REGS Registers........................................................................................................ 3686
31 Advanced Encryption Standard (AES) Accelerator.....................................................................................................3689
31.1 Introduction................................................................................................................................................................ 3690
31.1.1 AES Block Diagram............................................................................................................................................. 3690
31.1.2 AES Algorithm..................................................................................................................................................... 3693
31.2 AES Operating Modes............................................................................................................................................... 3694
31.2.1 GCM Operation................................................................................................................................................... 3694
31.2.2 CCM Operation....................................................................................................................................................3695
31.2.3 XTS Operation.....................................................................................................................................................3696
31.2.4 ECB Feedback Mode.......................................................................................................................................... 3697
31.2.5 CBC Feedback Mode.......................................................................................................................................... 3698
31.2.6 CTR and ICM Feedback Modes.......................................................................................................................... 3699
31.2.7 CFB Mode........................................................................................................................................................... 3700
31.2.8 F8 Mode.............................................................................................................................................................. 3701
31.2.9 F9 Operation........................................................................................................................................................3702
31.2.10 CBC-MAC Operation......................................................................................................................................... 3703
31.3 Extended and Combined Modes of Operations......................................................................................................... 3704
31.3.1 GCM Protocol Operation..................................................................................................................................... 3704
31.3.2 CCM Protocol Operation..................................................................................................................................... 3704
31.3.3 Hardware Requests.............................................................................................................................................3704
31.4 AES Module Programming Guide.............................................................................................................................. 3705
31.4.1 AES Low-Level Programming Models.................................................................................................................3705
31.5 Software..................................................................................................................................................................... 3710

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31.5.1 AES Registers to Driverlib Functions.................................................................................................................. 3710

31.5.2 AES_SS Registers to Driverlib Functions............................................................................................................3712
31.5.3 AES Examples.....................................................................................................................................................3712
31.6 AES Registers............................................................................................................................................................3714
31.6.1 AES Base Address Table.................................................................................................................................... 3714
31.6.2 AES_REGS Registers......................................................................................................................................... 3715
31.6.3 AES_SS_REGS Registers.................................................................................................................................. 3759
32 Embedded Pattern Generator (EPG).............................................................................................................................3762
32.1 Introduction................................................................................................................................................................ 3763
32.1.1 Features.............................................................................................................................................................. 3763
32.1.2 EPG Block Diagram.............................................................................................................................................3763
32.1.3 EPG Related Collateral....................................................................................................................................... 3764
32.2 Clock Generator Modules.......................................................................................................................................... 3765
32.2.1 DCLK (50% duty cycle clock).............................................................................................................................. 3765
32.2.2 Clock Stop........................................................................................................................................................... 3766
32.3 Signal Generator Module........................................................................................................................................... 3767
32.4 EPG Peripheral Signal Mux Selection........................................................................................................................3770
32.5 Application Software Notes........................................................................................................................................ 3772
32.6 EPG Example Use Cases.......................................................................................................................................... 3773
32.6.1 EPG Example: Synchronous Clocks with Offset................................................................................................. 3773
32.6.2 EPG Example: Serial Data Bit Stream (LSB first)............................................................................................... 3774
32.6.3 EPG Example: Serial Data Bit Stream (MSB first).............................................................................................. 3775
32.7 EPG Interrupt............................................................................................................................................................. 3776
32.8 Software..................................................................................................................................................................... 3777
32.8.1 EPG Registers to Driverlib Functions.................................................................................................................. 3777
32.8.2 EPG Examples.................................................................................................................................................... 3778
32.9 EPG Registers........................................................................................................................................................... 3779
32.9.1 EPG Base Address Table.................................................................................................................................... 3779
32.9.2 EPG_REGS Registers.........................................................................................................................................3780
32.9.3 EPG_MUX_REGS Registers...............................................................................................................................3809
33 Revision History............................................................................................................................................................. 3815

List of Figures
Figure 3-1. Device Interrupt Architecture.................................................................................................................................103
Figure 3-2. Interrupt Propagation Path.................................................................................................................................... 105
Figure 3-3. System Error..........................................................................................................................................................110
Figure 3-4. ERRORSTS Pin Diagram...................................................................................................................................... 118
Figure 3-5. Clocking System.................................................................................................................................................... 119
Figure 3-6. System PLL........................................................................................................................................................... 120
Figure 3-7. AUXCLKIN............................................................................................................................................................ 121
Figure 3-8. Single-ended 3.3V External Clock.........................................................................................................................122
Figure 3-9. External Crystal..................................................................................................................................................... 122
Figure 3-10. External Resonator..............................................................................................................................................123
Figure 3-11. Missing Clock Detection Logic.............................................................................................................................132
Figure 3-12. CPU Timers......................................................................................................................................................... 133
Figure 3-13. CPU Timer Interrupt Signals and Output Signal..................................................................................................133
Figure 3-14. Watchdog Timer Module......................................................................................................................................134
Figure 3-15. Memory Architecture........................................................................................................................................... 140
Figure 3-16. Arbitration Scheme on Local Shared Memories..................................................................................................143
Figure 3-17. Arbitration Scheme on Global Shared Memories................................................................................................ 143
Figure 3-18. Simplified LFU Representation............................................................................................................................149
Figure 3-19. PIE Vector Table Swap........................................................................................................................................150
Figure 3-20. LS0/LS1 RAM Memory Swap..............................................................................................................................151
Figure 3-21. TIM Register........................................................................................................................................................180
Figure 3-22. PRD Register...................................................................................................................................................... 181
Figure 3-23. TCR Register.......................................................................................................................................................182
Figure 3-24. TPR Register.......................................................................................................................................................184
Figure 3-25. TPRH Register.................................................................................................................................................... 185
Figure 3-26. PIECTRL Register...............................................................................................................................................188
Figure 3-27. PIEACK Register.................................................................................................................................................189

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Figure 3-28. PIEIER1 Register................................................................................................................................................ 190

Figure 3-29. PIEIFR1 Register................................................................................................................................................ 192
Figure 3-30. PIEIER2 Register................................................................................................................................................ 194
Figure 3-31. PIEIFR2 Register................................................................................................................................................ 196
Figure 3-32. PIEIER3 Register................................................................................................................................................ 198
Figure 3-33. PIEIFR3 Register................................................................................................................................................ 200
Figure 3-34. PIEIER4 Register................................................................................................................................................ 202
Figure 3-35. PIEIFR4 Register................................................................................................................................................ 204
Figure 3-36. PIEIER5 Register................................................................................................................................................ 206
Figure 3-37. PIEIFR5 Register................................................................................................................................................ 208
Figure 3-38. PIEIER6 Register................................................................................................................................................ 210
Figure 3-39. PIEIFR6 Register................................................................................................................................................ 212
Figure 3-40. PIEIER7 Register................................................................................................................................................ 214
Figure 3-41. PIEIFR7 Register................................................................................................................................................ 216
Figure 3-42. PIEIER8 Register................................................................................................................................................ 218
Figure 3-43. PIEIFR8 Register................................................................................................................................................ 220
Figure 3-44. PIEIER9 Register................................................................................................................................................ 222
Figure 3-45. PIEIFR9 Register................................................................................................................................................ 224
Figure 3-46. PIEIER10 Register.............................................................................................................................................. 226
Figure 3-47. PIEIFR10 Register.............................................................................................................................................. 228
Figure 3-48. PIEIER11 Register...............................................................................................................................................230
Figure 3-49. PIEIFR11 Register...............................................................................................................................................232
Figure 3-50. PIEIER12 Register.............................................................................................................................................. 234
Figure 3-51. PIEIFR12 Register.............................................................................................................................................. 236
Figure 3-52. NMICFG Register................................................................................................................................................239
Figure 3-53. NMIFLG Register................................................................................................................................................ 240
Figure 3-54. NMIFLGCLR Register......................................................................................................................................... 242
Figure 3-55. NMIFLGFRC Register......................................................................................................................................... 244
Figure 3-56. NMIWDCNT Register.......................................................................................................................................... 245
Figure 3-57. NMIWDPRD Register..........................................................................................................................................246
Figure 3-58. NMISHDFLG Register.........................................................................................................................................247
Figure 3-59. ERRORSTS Register.......................................................................................................................................... 249
Figure 3-60. ERRORSTSCLR Register...................................................................................................................................250
Figure 3-61. ERRORSTSFRC Register...................................................................................................................................251
Figure 3-62. ERRORCTL Register.......................................................................................................................................... 252
Figure 3-63. ERRORLOCK Register....................................................................................................................................... 253
Figure 3-64. XINT1CR Register...............................................................................................................................................255
Figure 3-65. XINT2CR Register...............................................................................................................................................256
Figure 3-66. XINT3CR Register...............................................................................................................................................257
Figure 3-67. XINT4CR Register...............................................................................................................................................258
Figure 3-68. XINT5CR Register...............................................................................................................................................259
Figure 3-69. XINT1CTR Register............................................................................................................................................ 260
Figure 3-70. XINT2CTR Register............................................................................................................................................ 261
Figure 3-71. XINT3CTR Register............................................................................................................................................ 262
Figure 3-72. SYNCSELECT Register...................................................................................................................................... 264
Figure 3-73. ADCSOCOUTSELECT Register......................................................................................................................... 266
Figure 3-74. SYNCSOCLOCK Register.................................................................................................................................. 269
Figure 3-75. CLA1TASKSRCSELLOCK Register....................................................................................................................271
Figure 3-76. DMACHSRCSELLOCK Register.........................................................................................................................272
Figure 3-77. CLA1TASKSRCSEL1 Register............................................................................................................................273
Figure 3-78. CLA1TASKSRCSEL2 Register............................................................................................................................274
Figure 3-79. DMACHSRCSEL1 Register................................................................................................................................ 275
Figure 3-80. DMACHSRCSEL2 Register................................................................................................................................ 276
Figure 3-81. LFUConfig Register.............................................................................................................................................278
Figure 3-82. LFUStatus Register............................................................................................................................................. 279
Figure 3-83. LFU_LOCK Register........................................................................................................................................... 280
Figure 3-84. LFU_COMMIT Register.......................................................................................................................................281
Figure 3-85. PARTIDL Register............................................................................................................................................... 285
Figure 3-86. PARTIDH Register...............................................................................................................................................287
Figure 3-87. REVID Register................................................................................................................................................... 288
Figure 3-88. TRIMERRSTS Register.......................................................................................................................................289

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Figure 3-89. SOFTPRES0 Register.........................................................................................................................................290

Figure 3-90. SOFTPRES2 Register.........................................................................................................................................291
Figure 3-91. SOFTPRES3 Register.........................................................................................................................................293
Figure 3-92. SOFTPRES4 Register.........................................................................................................................................294
Figure 3-93. SOFTPRES7 Register.........................................................................................................................................295
Figure 3-94. SOFTPRES8 Register.........................................................................................................................................296
Figure 3-95. SOFTPRES9 Register.........................................................................................................................................297
Figure 3-96. SOFTPRES10 Register.......................................................................................................................................298
Figure 3-97. SOFTPRES11 Register....................................................................................................................................... 299
Figure 3-98. SOFTPRES13 Register.......................................................................................................................................300
Figure 3-99. SOFTPRES14 Register.......................................................................................................................................301
Figure 3-100. SOFTPRES15 Register.....................................................................................................................................302
Figure 3-101. SOFTPRES16 Register.....................................................................................................................................303
Figure 3-102. SOFTPRES17 Register.....................................................................................................................................304
Figure 3-103. SOFTPRES18 Register.....................................................................................................................................305
Figure 3-104. SOFTPRES19 Register.....................................................................................................................................306
Figure 3-105. SOFTPRES20 Register.....................................................................................................................................307
Figure 3-106. SOFTPRES21 Register.....................................................................................................................................308
Figure 3-107. SOFTPRES26 Register.....................................................................................................................................309
Figure 3-108. SOFTPRES27 Register.....................................................................................................................................310
Figure 3-109. SOFTPRES28 Register..................................................................................................................................... 311
Figure 3-110. SOFTPRES30 Register..................................................................................................................................... 312
Figure 3-111. SOFTPRES40 Register..................................................................................................................................... 313
Figure 3-112. TAP_STATUS Register...................................................................................................................................... 314
Figure 3-113. TAP_CONTROL Register.................................................................................................................................. 315
Figure 3-114. USBTYPE Register............................................................................................................................................316
Figure 3-115. ECAPTYPE Register......................................................................................................................................... 317
Figure 3-116. MCUCNF3 Register...........................................................................................................................................318
Figure 3-117. MCUCNF8 Register...........................................................................................................................................320
Figure 3-118. MCUCNF11 Register......................................................................................................................................... 321
Figure 3-119. MCUCNF12 Register.........................................................................................................................................322
Figure 3-120. MCUCNF14 Register........................................................................................................................................ 323
Figure 3-121. MCUCNF16 Register........................................................................................................................................ 324
Figure 3-122. MCUCNF18 Register........................................................................................................................................ 325
Figure 3-123. MCUCNF20 Register........................................................................................................................................ 327
Figure 3-124. MCUCNF21 Register........................................................................................................................................ 329
Figure 3-125. MCUCNF23 Register........................................................................................................................................ 330
Figure 3-126. MCUCNF31 Register........................................................................................................................................ 331
Figure 3-127. MCUCNF32 Register........................................................................................................................................ 333
Figure 3-128. MCUCNF33 Register........................................................................................................................................ 335
Figure 3-129. MCUCNF34 Register........................................................................................................................................ 337
Figure 3-130. MCUCNF35 Register........................................................................................................................................ 339
Figure 3-131. MCUCNFLOCK Register...................................................................................................................................340
Figure 3-132. CLKCFGLOCK1 Register..................................................................................................................................343
Figure 3-133. CLKSRCCTL1 Register.....................................................................................................................................345
Figure 3-134. CLKSRCCTL2 Register.....................................................................................................................................347
Figure 3-135. CLKSRCCTL3 Register.....................................................................................................................................348
Figure 3-136. SYSPLLCTL1 Register......................................................................................................................................349
Figure 3-137. SYSPLLMULT Register..................................................................................................................................... 350
Figure 3-138. SYSPLLSTS Register....................................................................................................................................... 351
Figure 3-139. SYSCLKDIVSEL Register................................................................................................................................. 352
Figure 3-140. AUXCLKDIVSEL Register.................................................................................................................................353
Figure 3-141. PERCLKDIVSEL Register.................................................................................................................................354
Figure 3-142. XCLKOUTDIVSEL Register.............................................................................................................................. 355
Figure 3-143. CLBCLKCTL Register....................................................................................................................................... 356
Figure 3-144. LOSPCP Register............................................................................................................................................. 357
Figure 3-145. MCDCR Register...............................................................................................................................................358
Figure 3-146. X1CNT Register................................................................................................................................................ 360
Figure 3-147. XTALCR Register.............................................................................................................................................. 361
Figure 3-148. XTALCR2 Register............................................................................................................................................ 362
Figure 3-149. CLKFAILCFG Register...................................................................................................................................... 363

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Figure 3-150. CPUSYSLOCK1 Register................................................................................................................................. 366

Figure 3-151. CPUSYSLOCK2 Register................................................................................................................................. 369
Figure 3-152. PIEVERRADDR Register.................................................................................................................................. 371
Figure 3-153. PCLKCR0 Register........................................................................................................................................... 372
Figure 3-154. PCLKCR2 Register........................................................................................................................................... 374
Figure 3-155. PCLKCR3 Register........................................................................................................................................... 376
Figure 3-156. PCLKCR4 Register........................................................................................................................................... 377
Figure 3-157. PCLKCR7 Register........................................................................................................................................... 378
Figure 3-158. PCLKCR8 Register........................................................................................................................................... 379
Figure 3-159. PCLKCR9 Register........................................................................................................................................... 380
Figure 3-160. PCLKCR10 Register......................................................................................................................................... 381
Figure 3-161. PCLKCR11 Register..........................................................................................................................................382
Figure 3-162. PCLKCR12 Register......................................................................................................................................... 383
Figure 3-163. PCLKCR13 Register......................................................................................................................................... 384
Figure 3-164. PCLKCR14 Register......................................................................................................................................... 385
Figure 3-165. PCLKCR15 Register......................................................................................................................................... 386
Figure 3-166. PCLKCR16 Register......................................................................................................................................... 387
Figure 3-167. PCLKCR17 Register......................................................................................................................................... 388
Figure 3-168. PCLKCR18 Register......................................................................................................................................... 389
Figure 3-169. PCLKCR19 Register......................................................................................................................................... 390
Figure 3-170. PCLKCR20 Register......................................................................................................................................... 391
Figure 3-171. PCLKCR21 Register......................................................................................................................................... 392
Figure 3-172. PCLKCR26 Register......................................................................................................................................... 393
Figure 3-173. PCLKCR27 Register......................................................................................................................................... 394
Figure 3-174. SIMRESET Register..........................................................................................................................................395
Figure 3-175. LPMCR Register............................................................................................................................................... 396
Figure 3-176. GPIOLPMSEL0 Register...................................................................................................................................397
Figure 3-177. GPIOLPMSEL1 Register...................................................................................................................................400
Figure 3-178. TMR2CLKCTL Register.................................................................................................................................... 403
Figure 3-179. RESCCLR Register...........................................................................................................................................404
Figure 3-180. RESC Register.................................................................................................................................................. 406
Figure 3-181. CMPSSLPMSEL Register................................................................................................................................. 408
Figure 3-182. MCANRAMACC Register..................................................................................................................................410
Figure 3-183. MCANWAKESTATUS Register..........................................................................................................................411
Figure 3-184. MCANWAKESTATUSCLR Register.................................................................................................................. 412
Figure 3-185. CLKSTOPREQ Register....................................................................................................................................413
Figure 3-186. CLKSTOPACK Register.................................................................................................................................... 414
Figure 3-187. USER_REG1_SYSRSn Register...................................................................................................................... 415
Figure 3-188. USER_REG2_SYSRSn Register...................................................................................................................... 416
Figure 3-189. USER_REG1_XRSn Register...........................................................................................................................417
Figure 3-190. USER_REG2_XRSn Register...........................................................................................................................418
Figure 3-191. USER_REG1_PORESETn Register................................................................................................................. 419
Figure 3-192. USER_REG2_PORESETn Register................................................................................................................. 420
Figure 3-193. USER_REG3_PORESETn Register................................................................................................................. 421
Figure 3-194. USER_REG4_PORESETn Register................................................................................................................. 422
Figure 3-195. JTAG_MMR_REG Register...............................................................................................................................423
Figure 3-196. SYS_ERR_INT_FLG Register.......................................................................................................................... 425
Figure 3-197. SYS_ERR_INT_CLR Register.......................................................................................................................... 427
Figure 3-198. SYS_ERR_INT_SET Register.......................................................................................................................... 429
Figure 3-199. SYS_ERR_MASK Register............................................................................................................................... 431
Figure 3-200. ADCA_AC Register........................................................................................................................................... 435
Figure 3-201. ADCB_AC Register........................................................................................................................................... 436
Figure 3-202. ADCC_AC Register...........................................................................................................................................437
Figure 3-203. ADCD_AC Register...........................................................................................................................................438
Figure 3-204. ADCE_AC Register........................................................................................................................................... 439
Figure 3-205. CMPSS1_AC Register...................................................................................................................................... 440
Figure 3-206. CMPSS2_AC Register...................................................................................................................................... 441
Figure 3-207. CMPSS3_AC Register...................................................................................................................................... 442
Figure 3-208. CMPSS4_AC Register...................................................................................................................................... 443
Figure 3-209. DACA_AC Register........................................................................................................................................... 444
Figure 3-210. PGA1_AC Register........................................................................................................................................... 445

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Figure 3-211. PGA2_AC Register............................................................................................................................................446

Figure 3-212. PGA3_AC Register........................................................................................................................................... 447
Figure 3-213. EPWM1_AC Register........................................................................................................................................448
Figure 3-214. EPWM2_AC Register........................................................................................................................................449
Figure 3-215. EPWM3_AC Register........................................................................................................................................450
Figure 3-216. EPWM4_AC Register........................................................................................................................................451
Figure 3-217. EPWM5_AC Register........................................................................................................................................452
Figure 3-218. EPWM6_AC Register........................................................................................................................................453
Figure 3-219. EPWM7_AC Register........................................................................................................................................454
Figure 3-220. EPWM8_AC Register........................................................................................................................................455
Figure 3-221. EPWM9_AC Register........................................................................................................................................456
Figure 3-222. EPWM10_AC Register......................................................................................................................................457
Figure 3-223. EPWM11_AC Register...................................................................................................................................... 458
Figure 3-224. EPWM12_AC Register......................................................................................................................................459
Figure 3-225. EQEP1_AC Register......................................................................................................................................... 460
Figure 3-226. EQEP2_AC Register......................................................................................................................................... 461
Figure 3-227. EQEP3_AC Register......................................................................................................................................... 462
Figure 3-228. ECAP1_AC Register......................................................................................................................................... 463
Figure 3-229. ECAP2_AC Register......................................................................................................................................... 464
Figure 3-230. CLB1_AC Register............................................................................................................................................ 465
Figure 3-231. CLB2_AC Register............................................................................................................................................ 466
Figure 3-232. SCIA_AC Register.............................................................................................................................................467
Figure 3-233. SCIB_AC Register.............................................................................................................................................468
Figure 3-234. SCIC_AC Register............................................................................................................................................ 469
Figure 3-235. SPIA_AC Register.............................................................................................................................................470
Figure 3-236. SPIB_AC Register.............................................................................................................................................471
Figure 3-237. I2CA_AC Register............................................................................................................................................. 472
Figure 3-238. I2CB_AC Register............................................................................................................................................. 473
Figure 3-239. PMBUS_A_AC Register....................................................................................................................................474
Figure 3-240. LIN_A_AC Register........................................................................................................................................... 475
Figure 3-241. MCANA_AC Register........................................................................................................................................ 476
Figure 3-242. MCANB_AC Register........................................................................................................................................ 477
Figure 3-243. FSIATX_AC Register.........................................................................................................................................478
Figure 3-244. FSIARX_AC Register........................................................................................................................................ 479
Figure 3-245. USBA_AC Register........................................................................................................................................... 480
Figure 3-246. HRPWM_A_AC Register...................................................................................................................................481
Figure 3-247. AESA_AC Register........................................................................................................................................... 482
Figure 3-248. PERIPH_AC_LOCK Register............................................................................................................................483
Figure 3-249. DxLOCK Register..............................................................................................................................................486
Figure 3-250. DxCOMMIT Register......................................................................................................................................... 487
Figure 3-251. DxACCPROT0 Register.................................................................................................................................... 488
Figure 3-252. DxACCPROT1 Register.................................................................................................................................... 489
Figure 3-253. DxTEST Register.............................................................................................................................................. 490
Figure 3-254. DxINIT Register.................................................................................................................................................491
Figure 3-255. DxINITDONE Register...................................................................................................................................... 492
Figure 3-256. DxRAMTEST_LOCK Register...........................................................................................................................493
Figure 3-257. LSxLOCK Register............................................................................................................................................ 494
Figure 3-258. LSxCOMMIT Register....................................................................................................................................... 496
Figure 3-259. LSxMSEL Register............................................................................................................................................ 498
Figure 3-260. LSxCLAPGM Register.......................................................................................................................................500
Figure 3-261. LSxACCPROT0 Register.................................................................................................................................. 502
Figure 3-262. LSxACCPROT1 Register.................................................................................................................................. 504
Figure 3-263. LSxACCPROT2_y Register.............................................................................................................................. 506
Figure 3-264. LSxTEST Register.............................................................................................................................................507
Figure 3-265. LSxINIT Register............................................................................................................................................... 510
Figure 3-266. LSxINITDONE Register.....................................................................................................................................512
Figure 3-267. LSxRAMTEST_LOCK Register.........................................................................................................................513
Figure 3-268. GSxLOCK Register........................................................................................................................................... 514
Figure 3-269. GSxCOMMIT Register...................................................................................................................................... 516
Figure 3-270. GSxACCPROT0 Register................................................................................................................................. 518
Figure 3-271. GSxTEST Register............................................................................................................................................520

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 23

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Figure 3-272. GSxINIT Register.............................................................................................................................................. 522

Figure 3-273. GSxINITDONE Register....................................................................................................................................524
Figure 3-274. GSxRAMTEST_LOCK Register........................................................................................................................ 526
Figure 3-275. MSGxLOCK Register........................................................................................................................................ 527
Figure 3-276. MSGxCOMMIT Register................................................................................................................................... 529
Figure 3-277. MSGxTEST Register.........................................................................................................................................531
Figure 3-278. MSGxINIT Register........................................................................................................................................... 533
Figure 3-279. MSGxINITDONE Register.................................................................................................................................534
Figure 3-280. MSGxRAMTEST_LOCK Register..................................................................................................................... 535
Figure 3-281. ROM_LOCK Register........................................................................................................................................536
Figure 3-282. ROM_TEST Register........................................................................................................................................ 537
Figure 3-283. ROM_FORCE_ERROR Register...................................................................................................................... 538
Figure 3-284. NMAVFLG Register........................................................................................................................................... 541
Figure 3-285. NMAVSET Register........................................................................................................................................... 543
Figure 3-286. NMAVCLR Register...........................................................................................................................................545
Figure 3-287. NMAVINTEN Register....................................................................................................................................... 547
Figure 3-288. NMCPURDAVADDR Register........................................................................................................................... 549
Figure 3-289. NMCPUWRAVADDR Register.......................................................................................................................... 550
Figure 3-290. NMCPUFAVADDR Register.............................................................................................................................. 551
Figure 3-291. NMDMAWRAVADDR Register.......................................................................................................................... 552
Figure 3-292. NMCLA1RDAVADDR Register..........................................................................................................................553
Figure 3-293. NMCLA1WRAVADDR Register......................................................................................................................... 554
Figure 3-294. NMCLA1FAVADDR Register............................................................................................................................. 555
Figure 3-295. NMDMARDAVADDR Register...........................................................................................................................556
Figure 3-296. MAVFLG Register..............................................................................................................................................557
Figure 3-297. MAVSET Register..............................................................................................................................................558
Figure 3-298. MAVCLR Register............................................................................................................................................. 559
Figure 3-299. MAVINTEN Register..........................................................................................................................................560
Figure 3-300. MCPUFAVADDR Register................................................................................................................................. 561
Figure 3-301. MCPUWRAVADDR Register............................................................................................................................. 562
Figure 3-302. MDMAWRAVADDR Register.............................................................................................................................563
Figure 3-303. NMNPURDAVADDR Register........................................................................................................................... 564
Figure 3-304. NMNPUWRAVADDR Register.......................................................................................................................... 565
Figure 3-305. UCERRFLG Register........................................................................................................................................ 568
Figure 3-306. UCERRSET Register........................................................................................................................................ 569
Figure 3-307. UCERRCLR Register........................................................................................................................................ 570
Figure 3-308. UCCPUREADDR Register................................................................................................................................ 571
Figure 3-309. UCDMAREADDR Register................................................................................................................................572
Figure 3-310. UCCLA1READDR Register...............................................................................................................................573
Figure 3-311. UCNPUREADDR Register................................................................................................................................ 574
Figure 3-312. FLUCERRSTATUS Register............................................................................................................................. 575
Figure 3-313. FLCERRSTATUS Register................................................................................................................................ 576
Figure 3-314. CERRFLG Register...........................................................................................................................................578
Figure 3-315. CERRSET Register...........................................................................................................................................579
Figure 3-316. CERRCLR Register...........................................................................................................................................580
Figure 3-317. CCPUREADDR Register...................................................................................................................................581
Figure 3-318. CDMAREADDR Register.................................................................................................................................. 582
Figure 3-319. CCLA1READDR Register................................................................................................................................. 583
Figure 3-320. CERRCNT Register.......................................................................................................................................... 584
Figure 3-321. CERRTHRES Register......................................................................................................................................585
Figure 3-322. CEINTFLG Register.......................................................................................................................................... 586
Figure 3-323. CEINTCLR Register.......................................................................................................................................... 587
Figure 3-324. CEINTSET Register.......................................................................................................................................... 588
Figure 3-325. CEINTEN Register............................................................................................................................................ 589
Figure 3-326. CPU_RAM_TEST_ERROR_STS Register....................................................................................................... 591
Figure 3-327. CPU_RAM_TEST_ERROR_STS_CLR Register.............................................................................................. 592
Figure 3-328. CPU_RAM_TEST_ERROR_ADDR Register.................................................................................................... 593
Figure 3-329. UID_PSRAND0 Register...................................................................................................................................595
Figure 3-330. UID_PSRAND1 Register...................................................................................................................................596
Figure 3-331. UID_PSRAND2 Register...................................................................................................................................597
Figure 3-332. UID_PSRAND3 Register...................................................................................................................................598

24 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 3-333. UID_PSRAND4 Register...................................................................................................................................599

Figure 3-334. UID_UNIQUE0 Register....................................................................................................................................600
Figure 3-335. UID_UNIQUE1 Register....................................................................................................................................601
Figure 3-336. UID_CHECKSUM Register............................................................................................................................... 602
Figure 4-1. Device Boot Flow.................................................................................................................................................. 612
Figure 4-2. Emulation Boot Flow............................................................................................................................................. 613
Figure 4-3. CPU Standalone Boot Flow...................................................................................................................................614
Figure 4-4. Overview of SCI Bootloader Operation................................................................................................................. 626
Figure 4-5. Overview of SCI Boot Function............................................................................................................................. 627
Figure 4-6. Overview of SPI Bootloader Operation................................................................................................................. 628
Figure 4-7. Data Transfer from EEPROM Flow....................................................................................................................... 630
Figure 4-8. EEPROM Device at Address 0x50........................................................................................................................631
Figure 4-9. Overview of I2C Boot Function..............................................................................................................................632
Figure 4-10. Random Read..................................................................................................................................................... 633
Figure 4-11. Sequential Read.................................................................................................................................................. 633
Figure 4-12. Overview of Parallel GPIO Bootloader Operation............................................................................................... 634
Figure 4-13. Parallel GPIO Bootloader Handshake Protocol...................................................................................................635
Figure 4-14. Overview of Parallel GPIO Boot Function........................................................................................................... 635
Figure 4-15. Parallel GPIO Mode - Host Transfer Flow........................................................................................................... 636
Figure 4-16. 8-Bit Parallel GetWord Function.......................................................................................................................... 637
Figure 4-17. Overview of CAN-A Bootloader Operation.......................................................................................................... 638
Figure 4-18. USB Boot Flow.................................................................................................................................................... 641
Figure 5-1. Storage of Zone-Select Bits in OTP...................................................................................................................... 658
Figure 5-2. Location of Zone-Select Block Based on Link-Pointer.......................................................................................... 659
Figure 5-3. CSM Password Match Flow (PMF)....................................................................................................................... 664
Figure 5-4. ECSL Password Match Flow (PMF)......................................................................................................................666
Figure 5-5. Z1_LINKPOINTER Register..................................................................................................................................675
Figure 5-6. Z1_OTPSECLOCK Register................................................................................................................................. 676
Figure 5-7. Z1_JLM_ENABLE Register...................................................................................................................................677
Figure 5-8. Z1_LINKPOINTERERR Register.......................................................................................................................... 678
Figure 5-9. Z1_GPREG1 Register...........................................................................................................................................679
Figure 5-10. Z1_GPREG2 Register.........................................................................................................................................680
Figure 5-11. Z1_GPREG3 Register......................................................................................................................................... 681
Figure 5-12. Z1_GPREG4 Register.........................................................................................................................................682
Figure 5-13. Z1_CSMKEY0 Register.......................................................................................................................................683
Figure 5-14. Z1_CSMKEY1 Register.......................................................................................................................................684
Figure 5-15. Z1_CSMKEY2 Register.......................................................................................................................................685
Figure 5-16. Z1_CSMKEY3 Register.......................................................................................................................................686
Figure 5-17. Z1_CR Register...................................................................................................................................................687
Figure 5-18. Z1_GRABSECT1R Register............................................................................................................................... 689
Figure 5-19. Z1_GRABSECT2R Register............................................................................................................................... 693
Figure 5-20. Z1_GRABSECT3R Register............................................................................................................................... 697
Figure 5-21. Z1_GRABRAM1R Register................................................................................................................................. 699
Figure 5-22. Z1_EXEONLYSECT1R Register......................................................................................................................... 702
Figure 5-23. Z1_EXEONLYSECT2R Register......................................................................................................................... 708
Figure 5-24. Z1_EXEONLYRAM1R Register...........................................................................................................................710
Figure 5-25. Z1_JTAGKEY0 Register......................................................................................................................................712
Figure 5-26. Z1_JTAGKEY1 Register......................................................................................................................................713
Figure 5-27. Z1_JTAGKEY2 Register......................................................................................................................................714
Figure 5-28. Z1_JTAGKEY3 Register......................................................................................................................................715
Figure 5-29. Z1_CMACKEY0 Register.................................................................................................................................... 716
Figure 5-30. Z1_CMACKEY1 Register.................................................................................................................................... 717
Figure 5-31. Z1_CMACKEY2 Register.................................................................................................................................... 718
Figure 5-32. Z1_CMACKEY3 Register.................................................................................................................................... 719
Figure 5-33. Z1_DIAG Register............................................................................................................................................... 720
Figure 5-34. Z2_LINKPOINTER Register................................................................................................................................722
Figure 5-35. Z2_OTPSECLOCK Register............................................................................................................................... 723
Figure 5-36. Z2_LINKPOINTERERR Register........................................................................................................................ 724
Figure 5-37. Z2_GPREG1 Register.........................................................................................................................................725
Figure 5-38. Z2_GPREG2 Register.........................................................................................................................................726
Figure 5-39. Z2_GPREG3 Register.........................................................................................................................................727

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 25

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Figure 5-40. Z2_GPREG4 Register.........................................................................................................................................728

Figure 5-41. Z2_CSMKEY0 Register.......................................................................................................................................729
Figure 5-42. Z2_CSMKEY1 Register.......................................................................................................................................730
Figure 5-43. Z2_CSMKEY2 Register.......................................................................................................................................731
Figure 5-44. Z2_CSMKEY3 Register.......................................................................................................................................732
Figure 5-45. Z2_CR Register...................................................................................................................................................733
Figure 5-46. Z2_GRABSECT1R Register............................................................................................................................... 735
Figure 5-47. Z2_GRABSECT2R Register............................................................................................................................... 739
Figure 5-48. Z2_GRABSECT3R Register............................................................................................................................... 743
Figure 5-49. Z2_GRABRAM1R Register................................................................................................................................. 745
Figure 5-50. Z2_EXEONLYSECT1R Register......................................................................................................................... 748
Figure 5-51. Z2_EXEONLYSECT2R Register......................................................................................................................... 754
Figure 5-52. Z2_EXEONLYRAM1R Register...........................................................................................................................756
Figure 5-53. FLSEM Register.................................................................................................................................................. 759
Figure 5-54. SECTSTAT1 Register..........................................................................................................................................760
Figure 5-55. SECTSTAT2 Register..........................................................................................................................................763
Figure 5-56. SECTSTAT3 Register..........................................................................................................................................766
Figure 5-57. RAMSTAT1 Register........................................................................................................................................... 768
Figure 5-58. SECERRSTAT Register...................................................................................................................................... 770
Figure 5-59. SECERRCLR Register........................................................................................................................................771
Figure 5-60. SECERRFRC Register........................................................................................................................................772
Figure 5-61. DENYCODE Register..........................................................................................................................................773
Figure 5-62. UID_UNIQUE_31_0 Register..............................................................................................................................775
Figure 5-63. UID_UNIQUE_63_32 Register............................................................................................................................776
Figure 5-64. PARTIDH Register...............................................................................................................................................777
Figure 5-65. PERSEM1 Register.............................................................................................................................................778
Figure 5-66. Z1OTP_LINKPOINTER1 Register...................................................................................................................... 781
Figure 5-67. Z1OTP_LINKPOINTER2 Register...................................................................................................................... 782
Figure 5-68. Z1OTP_LINKPOINTER3 Register...................................................................................................................... 783
Figure 5-69. Z1OTP_JLM_ENABLE Register......................................................................................................................... 784
Figure 5-70. Z1OTP_GPREG1 Register................................................................................................................................. 785
Figure 5-71. Z1OTP_GPREG2 Register................................................................................................................................. 786
Figure 5-72. Z1OTP_GPREG3 Register................................................................................................................................. 787
Figure 5-73. Z1OTP_GPREG4 Register................................................................................................................................. 788
Figure 5-74. Z1OTP_PSWDLOCK Register............................................................................................................................789
Figure 5-75. Z1OTP_CRCLOCK Register...............................................................................................................................790
Figure 5-76. Z1OTP_JTAGPSWDH0 Register........................................................................................................................ 791
Figure 5-77. Z1OTP_JTAGPSWDH1 Register........................................................................................................................ 792
Figure 5-78. Z1OTP_CMACKEY0 Register.............................................................................................................................793
Figure 5-79. Z1OTP_CMACKEY1 Register.............................................................................................................................794
Figure 5-80. Z1OTP_CMACKEY2 Register.............................................................................................................................795
Figure 5-81. Z1OTP_CMACKEY3 Register.............................................................................................................................796
Figure 5-82. Z2OTP_LINKPOINTER1 Register...................................................................................................................... 798
Figure 5-83. Z2OTP_LINKPOINTER2 Register...................................................................................................................... 799
Figure 5-84. Z2OTP_LINKPOINTER3 Register...................................................................................................................... 800
Figure 5-85. Z2OTP_GPREG1 Register................................................................................................................................. 801
Figure 5-86. Z2OTP_GPREG2 Register................................................................................................................................. 802
Figure 5-87. Z2OTP_GPREG3 Register................................................................................................................................. 803
Figure 5-88. Z2OTP_GPREG4 Register................................................................................................................................. 804
Figure 5-89. Z2OTP_PSWDLOCK Register............................................................................................................................805
Figure 5-90. Z2OTP_CRCLOCK Register...............................................................................................................................806
Figure 6-1. Flash Interface Block Diagram.............................................................................................................................. 810
Figure 6-2. Flash Prefetch Mode............................................................................................................................................. 812
Figure 6-3. ECC Logic Inputs and Outputs..............................................................................................................................815
Figure 6-4. Testing ECC Logic.................................................................................................................................................818
Figure 6-5. FRDCNTL Register............................................................................................................................................... 823
Figure 6-6. FLPROT Register..................................................................................................................................................824
Figure 6-7. FRD_INTF_CTRL Register................................................................................................................................... 825
Figure 6-8. ECC_ENABLE Register........................................................................................................................................ 827
Figure 6-9. FECC_CTRL Register...........................................................................................................................................828
Figure 7-1. CLA Block Diagram............................................................................................................................................... 831

26 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 7-2. _MVECTBGRNDACTIVE Register....................................................................................................................... 990

Figure 7-3. _MPSACTL Register............................................................................................................................................. 991
Figure 7-4. _MPSA1 Register..................................................................................................................................................993
Figure 7-5. _MPSA2 Register..................................................................................................................................................994
Figure 7-6. SOFTINTEN Register............................................................................................................................................995
Figure 7-7. SOFTINTFRC Register......................................................................................................................................... 997
Figure 7-8. SOFTINTEN Register............................................................................................................................................999
Figure 7-9. SOFTINTFRC Register....................................................................................................................................... 1001
Figure 7-10. MVECT1 Register............................................................................................................................................. 1004
Figure 7-11. MVECT2 Register..............................................................................................................................................1005
Figure 7-12. MVECT3 Register............................................................................................................................................. 1006
Figure 7-13. MVECT4 Register............................................................................................................................................. 1007
Figure 7-14. MVECT5 Register............................................................................................................................................. 1008
Figure 7-15. MVECT6 Register............................................................................................................................................. 1009
Figure 7-16. MVECT7 Register............................................................................................................................................. 1010
Figure 7-17. MVECT8 Register..............................................................................................................................................1011
Figure 7-18. MCTL Register.................................................................................................................................................. 1012
Figure 7-19. _MVECTBGRNDACTIVE Register................................................................................................................... 1013
Figure 7-20. SOFTINTEN Register........................................................................................................................................1014
Figure 7-21. _MSTSBGRND Register................................................................................................................................... 1016
Figure 7-22. _MCTLBGRND Register................................................................................................................................... 1017
Figure 7-23. _MVECTBGRND Register................................................................................................................................ 1018
Figure 7-24. MIFR Register................................................................................................................................................... 1019
Figure 7-25. MIOVF Register.................................................................................................................................................1023
Figure 7-26. MIFRC Register.................................................................................................................................................1026
Figure 7-27. MICLR Register.................................................................................................................................................1028
Figure 7-28. MICLROVF Register......................................................................................................................................... 1030
Figure 7-29. MIER Register................................................................................................................................................... 1032
Figure 7-30. MIRUN Register................................................................................................................................................ 1035
Figure 7-31. _MPC Register.................................................................................................................................................. 1037
Figure 7-32. _MAR0 Register................................................................................................................................................ 1038
Figure 7-33. _MAR1 Register................................................................................................................................................ 1039
Figure 7-34. _MSTF Register................................................................................................................................................ 1040
Figure 7-35. _MR0 Register.................................................................................................................................................. 1043
Figure 7-36. _MR1 Register.................................................................................................................................................. 1044
Figure 7-37. _MR2 Register.................................................................................................................................................. 1045
Figure 7-38. _MR3 Register.................................................................................................................................................. 1046
Figure 7-39. _MPSACTL Register......................................................................................................................................... 1047
Figure 7-40. _MPSA1 Register..............................................................................................................................................1049
Figure 7-41. _MPSA2 Register..............................................................................................................................................1050
Figure 8-1. NPU Development Flow ..................................................................................................................................... 1052
Figure 9-1. DCC Module Overview........................................................................................................................................1054
Figure 9-2. DCC Operation....................................................................................................................................................1055
Figure 9-3. Counter Relationship...........................................................................................................................................1059
Figure 9-4. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting...............................................................1059
Figure 9-5. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting............................................................... 1060
Figure 9-6. Clock1 Not Present - Results in an Error and Stops Counting............................................................................1060
Figure 9-7. Clock0 Not Present - Results in an Error and Stops Counting............................................................................1061
Figure 9-8. DCCGCTRL Register.......................................................................................................................................... 1066
Figure 9-9. DCCCNTSEED0 Register................................................................................................................................... 1067
Figure 9-10. DCCVALIDSEED0 Register.............................................................................................................................. 1068
Figure 9-11. DCCCNTSEED1 Register................................................................................................................................. 1069
Figure 9-12. DCCSTATUS Register.......................................................................................................................................1070
Figure 9-13. DCCCNT0 Register...........................................................................................................................................1071
Figure 9-14. DCCVALID0 Register........................................................................................................................................ 1072
Figure 9-15. DCCCNT1 Register...........................................................................................................................................1073
Figure 9-16. DCCCLKSRC1 Register....................................................................................................................................1074
Figure 9-17. DCCCLKSRC0 Register....................................................................................................................................1075
Figure 10-1. GPIO Logic for a Single Pin.............................................................................................................................. 1078
Figure 10-2. Analog Subsystem Block Diagram with AGPIO Implementation.......................................................................1081
Figure 10-3. Input Qualification Using a Sampling Window...................................................................................................1084

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Figure 10-4. Input Qualifier Clock Cycles.............................................................................................................................. 1086

Figure 10-5. GPACTRL Register............................................................................................................................................1106
Figure 10-6. GPAQSEL1 Register......................................................................................................................................... 1107
Figure 10-7. GPAQSEL2 Register..........................................................................................................................................1110
Figure 10-8. GPAMUX1 Register........................................................................................................................................... 1113
Figure 10-9. GPAMUX2 Register........................................................................................................................................... 1115
Figure 10-10. GPADIR Register............................................................................................................................................. 1117
Figure 10-11. GPAPUD Register............................................................................................................................................ 1119
Figure 10-12. GPAINV Register............................................................................................................................................. 1121
Figure 10-13. GPAODR Register........................................................................................................................................... 1123
Figure 10-14. GPAAMSEL Register.......................................................................................................................................1125
Figure 10-15. GPAGMUX1 Register...................................................................................................................................... 1127
Figure 10-16. GPAGMUX2 Register...................................................................................................................................... 1129
Figure 10-17. GPACSEL1 Register........................................................................................................................................1131
Figure 10-18. GPACSEL2 Register........................................................................................................................................1132
Figure 10-19. GPACSEL3 Register........................................................................................................................................1133
Figure 10-20. GPACSEL4 Register........................................................................................................................................1134
Figure 10-21. GPALOCK Register......................................................................................................................................... 1135
Figure 10-22. GPACR Register..............................................................................................................................................1137
Figure 10-23. GPBCTRL Register......................................................................................................................................... 1139
Figure 10-24. GPBQSEL1 Register....................................................................................................................................... 1140
Figure 10-25. GPBQSEL2 Register....................................................................................................................................... 1142
Figure 10-26. GPBMUX1 Register.........................................................................................................................................1145
Figure 10-27. GPBMUX2 Register.........................................................................................................................................1146
Figure 10-28. GPBDIR Register.............................................................................................................................................1148
Figure 10-29. GPBPUD Register........................................................................................................................................... 1150
Figure 10-30. GPBINV Register.............................................................................................................................................1152
Figure 10-31. GPBODR Register...........................................................................................................................................1154
Figure 10-32. GPBAMSEL Register.......................................................................................................................................1156
Figure 10-33. GPBGMUX1 Register...................................................................................................................................... 1158
Figure 10-34. GPBGMUX2 Register...................................................................................................................................... 1159
Figure 10-35. GPBCSEL1 Register....................................................................................................................................... 1161
Figure 10-36. GPBCSEL2 Register....................................................................................................................................... 1162
Figure 10-37. GPBCSEL3 Register....................................................................................................................................... 1163
Figure 10-38. GPBCSEL4 Register....................................................................................................................................... 1164
Figure 10-39. GPBLOCK Register......................................................................................................................................... 1165
Figure 10-40. GPBCR Register..............................................................................................................................................1167
Figure 10-41. GPCCTRL Register......................................................................................................................................... 1169
Figure 10-42. GPCQSEL1 Register....................................................................................................................................... 1170
Figure 10-43. GPCQSEL2 Register....................................................................................................................................... 1173
Figure 10-44. GPCMUX1 Register.........................................................................................................................................1174
Figure 10-45. GPCMUX2 Register.........................................................................................................................................1176
Figure 10-46. GPCDIR Register............................................................................................................................................ 1177
Figure 10-47. GPCPUD Register........................................................................................................................................... 1179
Figure 10-48. GPCINV Register.............................................................................................................................................1181
Figure 10-49. GPCODR Register...........................................................................................................................................1183
Figure 10-50. GPCAMSEL Register...................................................................................................................................... 1185
Figure 10-51. GPCGMUX1 Register......................................................................................................................................1187
Figure 10-52. GPCGMUX2 Register......................................................................................................................................1189
Figure 10-53. GPCCSEL1 Register....................................................................................................................................... 1190
Figure 10-54. GPCCSEL2 Register....................................................................................................................................... 1191
Figure 10-55. GPCCSEL3 Register....................................................................................................................................... 1192
Figure 10-56. GPCLOCK Register.........................................................................................................................................1193
Figure 10-57. GPCCR Register............................................................................................................................................. 1195
Figure 10-58. GPGCTRL Register......................................................................................................................................... 1197
Figure 10-59. GPGQSEL2 Register.......................................................................................................................................1198
Figure 10-60. GPGMUX2 Register........................................................................................................................................ 1200
Figure 10-61. GPGDIR Register............................................................................................................................................1202
Figure 10-62. GPGPUD Register.......................................................................................................................................... 1204
Figure 10-63. GPGINV Register............................................................................................................................................ 1206
Figure 10-64. GPGODR Register.......................................................................................................................................... 1208

28 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 10-65. GPGAMSEL Register......................................................................................................................................1210

Figure 10-66. GPGGMUX2 Register..................................................................................................................................... 1213
Figure 10-67. GPGCSEL3 Register.......................................................................................................................................1215
Figure 10-68. GPGLOCK Register........................................................................................................................................ 1216
Figure 10-69. GPGCR Register.............................................................................................................................................1218
Figure 10-70. GPHCTRL Register.........................................................................................................................................1220
Figure 10-71. GPHQSEL1 Register.......................................................................................................................................1221
Figure 10-72. GPHQSEL2 Register.......................................................................................................................................1223
Figure 10-73. GPHMUX1 Register........................................................................................................................................ 1225
Figure 10-74. GPHMUX2 Register........................................................................................................................................ 1227
Figure 10-75. GPHDIR Register............................................................................................................................................ 1229
Figure 10-76. GPHPUD Register...........................................................................................................................................1231
Figure 10-77. GPHINV Register............................................................................................................................................ 1237
Figure 10-78. GPHODR Register.......................................................................................................................................... 1241
Figure 10-79. GPHAMSEL Register...................................................................................................................................... 1243
Figure 10-80. GPHGMUX1 Register..................................................................................................................................... 1249
Figure 10-81. GPHGMUX2 Register..................................................................................................................................... 1251
Figure 10-82. GPHCSEL1 Register.......................................................................................................................................1253
Figure 10-83. GPHCSEL2 Register.......................................................................................................................................1254
Figure 10-84. GPHCSEL3 Register.......................................................................................................................................1255
Figure 10-85. GPHCSEL4 Register.......................................................................................................................................1256
Figure 10-86. GPHLOCK Register........................................................................................................................................ 1257
Figure 10-87. GPHCR Register............................................................................................................................................. 1261
Figure 10-88. GPADAT Register............................................................................................................................................1266
Figure 10-89. GPASET Register............................................................................................................................................1268
Figure 10-90. GPACLEAR Register.......................................................................................................................................1270
Figure 10-91. GPATOGGLE Register.................................................................................................................................... 1272
Figure 10-92. GPBDAT Register............................................................................................................................................1274
Figure 10-93. GPBSET Register........................................................................................................................................... 1276
Figure 10-94. GPBCLEAR Register...................................................................................................................................... 1278
Figure 10-95. GPBTOGGLE Register....................................................................................................................................1280
Figure 10-96. GPCDAT Register........................................................................................................................................... 1282
Figure 10-97. GPCSET Register........................................................................................................................................... 1284
Figure 10-98. GPCCLEAR Register...................................................................................................................................... 1286
Figure 10-99. GPCTOGGLE Register................................................................................................................................... 1288
Figure 10-100. GPGDAT Register......................................................................................................................................... 1290
Figure 10-101. GPGSET Register......................................................................................................................................... 1292
Figure 10-102. GPGCLEAR Register.................................................................................................................................... 1294
Figure 10-103. GPGTOGGLE Register................................................................................................................................. 1296
Figure 10-104. GPHDAT Register......................................................................................................................................... 1298
Figure 10-105. GPHSET Register......................................................................................................................................... 1305
Figure 10-106. GPHCLEAR Register.................................................................................................................................... 1307
Figure 10-107. GPHTOGGLE Register................................................................................................................................. 1309
Figure 10-108. GPADAT_R Register..................................................................................................................................... 1312
Figure 10-109. GPBDAT_R Register..................................................................................................................................... 1313
Figure 10-110. GPCDAT_R Register..................................................................................................................................... 1314
Figure 10-111. GPGDAT_R Register..................................................................................................................................... 1315
Figure 10-112. GPHDAT_R Register..................................................................................................................................... 1316
Figure 11-1. Input X-BAR.......................................................................................................................................................1319
Figure 11-2. ePWM X-BAR Architecture - Single Output.......................................................................................................1322
Figure 11-3. CLB X-BAR Architecture - Single Output...........................................................................................................1324
Figure 11-4. GPIO to CLB Tile Connections.......................................................................................................................... 1325
Figure 11-5. GPIO Output X-BAR Architecture......................................................................................................................1327
Figure 11-6. X-BAR Input Sources.........................................................................................................................................1329
Figure 11-7. INPUT1SELECT Register..................................................................................................................................1338
Figure 11-8. INPUT2SELECT Register..................................................................................................................................1339
Figure 11-9. INPUT3SELECT Register..................................................................................................................................1340
Figure 11-10. INPUT4SELECT Register................................................................................................................................1341
Figure 11-11. INPUT5SELECT Register................................................................................................................................1342
Figure 11-12. INPUT6SELECT Register................................................................................................................................1343
Figure 11-13. INPUT7SELECT Register................................................................................................................................1344

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Figure 11-14. INPUT8SELECT Register................................................................................................................................1345

Figure 11-15. INPUT9SELECT Register................................................................................................................................1346
Figure 11-16. INPUT10SELECT Register..............................................................................................................................1347
Figure 11-17. INPUT11SELECT Register..............................................................................................................................1348
Figure 11-18. INPUT12SELECT Register..............................................................................................................................1349
Figure 11-19. INPUT13SELECT Register..............................................................................................................................1350
Figure 11-20. INPUT14SELECT Register..............................................................................................................................1351
Figure 11-21. INPUT15SELECT Register..............................................................................................................................1352
Figure 11-22. INPUT16SELECT Register..............................................................................................................................1353
Figure 11-23. INPUTSELECTLOCK Register........................................................................................................................1354
Figure 11-24. XBARFLG1 Register........................................................................................................................................1357
Figure 11-25. XBARFLG2 Register........................................................................................................................................1360
Figure 11-26. XBARFLG3 Register........................................................................................................................................1365
Figure 11-27. XBARFLG4 Register........................................................................................................................................1368
Figure 11-28. XBARCLR1 Register....................................................................................................................................... 1371
Figure 11-29. XBARCLR2 Register....................................................................................................................................... 1373
Figure 11-30. XBARCLR3 Register....................................................................................................................................... 1376
Figure 11-31. XBARCLR4 Register....................................................................................................................................... 1378
Figure 11-32. TRIP4MUX0TO15CFG Register......................................................................................................................1382
Figure 11-33. TRIP4MUX16TO31CFG Register....................................................................................................................1385
Figure 11-34. TRIP5MUX0TO15CFG Register......................................................................................................................1388
Figure 11-35. TRIP5MUX16TO31CFG Register....................................................................................................................1391
Figure 11-36. TRIP7MUX0TO15CFG Register......................................................................................................................1394
Figure 11-37. TRIP7MUX16TO31CFG Register....................................................................................................................1397
Figure 11-38. TRIP8MUX0TO15CFG Register......................................................................................................................1400
Figure 11-39. TRIP8MUX16TO31CFG Register....................................................................................................................1403
Figure 11-40. TRIP9MUX0TO15CFG Register......................................................................................................................1406
Figure 11-41. TRIP9MUX16TO31CFG Register....................................................................................................................1409
Figure 11-42. TRIP10MUX0TO15CFG Register....................................................................................................................1412
Figure 11-43. TRIP10MUX16TO31CFG Register..................................................................................................................1415
Figure 11-44. TRIP11MUX0TO15CFG Register....................................................................................................................1418
Figure 11-45. TRIP11MUX16TO31CFG Register..................................................................................................................1421
Figure 11-46. TRIP12MUX0TO15CFG Register....................................................................................................................1424
Figure 11-47. TRIP12MUX16TO31CFG Register..................................................................................................................1427
Figure 11-48. TRIP4MUXENABLE Register.......................................................................................................................... 1430
Figure 11-49. TRIP5MUXENABLE Register.......................................................................................................................... 1435
Figure 11-50. TRIP7MUXENABLE Register.......................................................................................................................... 1440
Figure 11-51. TRIP8MUXENABLE Register.......................................................................................................................... 1445
Figure 11-52. TRIP9MUXENABLE Register.......................................................................................................................... 1450
Figure 11-53. TRIP10MUXENABLE Register........................................................................................................................ 1455
Figure 11-54. TRIP11MUXENABLE Register........................................................................................................................ 1460
Figure 11-55. TRIP12MUXENABLE Register........................................................................................................................ 1465
Figure 11-56. TRIPOUTINV Register.....................................................................................................................................1470
Figure 11-57. TRIPLOCK Register........................................................................................................................................ 1472
Figure 11-58. AUXSIG0MUX0TO15CFG Register................................................................................................................ 1475
Figure 11-59. AUXSIG0MUX16TO31CFG Register.............................................................................................................. 1478
Figure 11-60. AUXSIG1MUX0TO15CFG Register................................................................................................................ 1481
Figure 11-61. AUXSIG1MUX16TO31CFG Register.............................................................................................................. 1484
Figure 11-62. AUXSIG2MUX0TO15CFG Register................................................................................................................ 1487
Figure 11-63. AUXSIG2MUX16TO31CFG Register.............................................................................................................. 1490
Figure 11-64. AUXSIG3MUX0TO15CFG Register................................................................................................................ 1493
Figure 11-65. AUXSIG3MUX16TO31CFG Register.............................................................................................................. 1496
Figure 11-66. AUXSIG4MUX0TO15CFG Register................................................................................................................ 1499
Figure 11-67. AUXSIG4MUX16TO31CFG Register.............................................................................................................. 1502
Figure 11-68. AUXSIG5MUX0TO15CFG Register................................................................................................................ 1505
Figure 11-69. AUXSIG5MUX16TO31CFG Register.............................................................................................................. 1508
Figure 11-70. AUXSIG6MUX0TO15CFG Register................................................................................................................ 1511
Figure 11-71. AUXSIG6MUX16TO31CFG Register.............................................................................................................. 1514
Figure 11-72. AUXSIG7MUX0TO15CFG Register................................................................................................................ 1517
Figure 11-73. AUXSIG7MUX16TO31CFG Register.............................................................................................................. 1520
Figure 11-74. AUXSIG0MUXENABLE Register.....................................................................................................................1523

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Figure 11-75. AUXSIG1MUXENABLE Register.....................................................................................................................1528

Figure 11-76. AUXSIG2MUXENABLE Register.....................................................................................................................1533
Figure 11-77. AUXSIG3MUXENABLE Register.....................................................................................................................1538
Figure 11-78. AUXSIG4MUXENABLE Register.....................................................................................................................1543
Figure 11-79. AUXSIG5MUXENABLE Register.....................................................................................................................1548
Figure 11-80. AUXSIG6MUXENABLE Register.....................................................................................................................1553
Figure 11-81. AUXSIG7MUXENABLE Register.....................................................................................................................1558
Figure 11-82. AUXSIGOUTINV Register............................................................................................................................... 1563
Figure 11-83. AUXSIGLOCK Register................................................................................................................................... 1565
Figure 11-84. OUTPUT1MUX0TO15CFG Register............................................................................................................... 1568
Figure 11-85. OUTPUT1MUX16TO31CFG Register............................................................................................................. 1571
Figure 11-86. OUTPUT2MUX0TO15CFG Register............................................................................................................... 1574
Figure 11-87. OUTPUT2MUX16TO31CFG Register............................................................................................................. 1577
Figure 11-88. OUTPUT3MUX0TO15CFG Register............................................................................................................... 1580
Figure 11-89. OUTPUT3MUX16TO31CFG Register............................................................................................................. 1583
Figure 11-90. OUTPUT4MUX0TO15CFG Register............................................................................................................... 1586
Figure 11-91. OUTPUT4MUX16TO31CFG Register............................................................................................................. 1589
Figure 11-92. OUTPUT5MUX0TO15CFG Register............................................................................................................... 1592
Figure 11-93. OUTPUT5MUX16TO31CFG Register............................................................................................................. 1595
Figure 11-94. OUTPUT6MUX0TO15CFG Register............................................................................................................... 1598
Figure 11-95. OUTPUT6MUX16TO31CFG Register............................................................................................................. 1601
Figure 11-96. OUTPUT7MUX0TO15CFG Register............................................................................................................... 1604
Figure 11-97. OUTPUT7MUX16TO31CFG Register............................................................................................................. 1607
Figure 11-98. OUTPUT8MUX0TO15CFG Register............................................................................................................... 1610
Figure 11-99. OUTPUT8MUX16TO31CFG Register............................................................................................................. 1613
Figure 11-100. OUTPUT1MUXENABLE Register................................................................................................................. 1616
Figure 11-101. OUTPUT2MUXENABLE Register................................................................................................................. 1621
Figure 11-102. OUTPUT3MUXENABLE Register................................................................................................................. 1626
Figure 11-103. OUTPUT4MUXENABLE Register................................................................................................................. 1631
Figure 11-104. OUTPUT5MUXENABLE Register................................................................................................................. 1636
Figure 11-105. OUTPUT6MUXENABLE Register................................................................................................................. 1641
Figure 11-106. OUTPUT7MUXENABLE Register................................................................................................................. 1646
Figure 11-107. OUTPUT8MUXENABLE Register................................................................................................................. 1651
Figure 11-108. OUTPUTLATCH Register.............................................................................................................................. 1656
Figure 11-109. OUTPUTLATCHCLR Register.......................................................................................................................1658
Figure 11-110. OUTPUTLATCHFRC Register.......................................................................................................................1660
Figure 11-111. OUTPUTLATCHENABLE Register................................................................................................................ 1662
Figure 11-112. OUTPUTINV Register....................................................................................................................................1664
Figure 11-113. OUTPUTLOCK Register................................................................................................................................ 1666
Figure 11-114. OUTPUT1MUX0TO15CFG Register............................................................................................................. 1669
Figure 11-115. OUTPUT1MUX16TO31CFG Register........................................................................................................... 1672
Figure 11-116. OUTPUT2MUX0TO15CFG Register............................................................................................................. 1675
Figure 11-117. OUTPUT2MUX16TO31CFG Register........................................................................................................... 1678
Figure 11-118. OUTPUT3MUX0TO15CFG Register............................................................................................................. 1681
Figure 11-119. OUTPUT3MUX16TO31CFG Register........................................................................................................... 1684
Figure 11-120. OUTPUT4MUX0TO15CFG Register............................................................................................................. 1687
Figure 11-121. OUTPUT4MUX16TO31CFG Register........................................................................................................... 1690
Figure 11-122. OUTPUT5MUX0TO15CFG Register............................................................................................................. 1693
Figure 11-123. OUTPUT5MUX16TO31CFG Register........................................................................................................... 1696
Figure 11-124. OUTPUT6MUX0TO15CFG Register............................................................................................................. 1699
Figure 11-125. OUTPUT6MUX16TO31CFG Register........................................................................................................... 1702
Figure 11-126. OUTPUT7MUX0TO15CFG Register............................................................................................................. 1705
Figure 11-127. OUTPUT7MUX16TO31CFG Register........................................................................................................... 1708
Figure 11-128. OUTPUT8MUX0TO15CFG Register............................................................................................................. 1711
Figure 11-129. OUTPUT8MUX16TO31CFG Register........................................................................................................... 1714
Figure 11-130. OUTPUT1MUXENABLE Register................................................................................................................. 1717
Figure 11-131. OUTPUT2MUXENABLE Register................................................................................................................. 1722
Figure 11-132. OUTPUT3MUXENABLE Register................................................................................................................. 1727
Figure 11-133. OUTPUT4MUXENABLE Register................................................................................................................. 1732
Figure 11-134. OUTPUT5MUXENABLE Register................................................................................................................. 1737
Figure 11-135. OUTPUT6MUXENABLE Register................................................................................................................. 1742

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Figure 11-136. OUTPUT7MUXENABLE Register................................................................................................................. 1747

Figure 11-137. OUTPUT8MUXENABLE Register................................................................................................................. 1752
Figure 11-138. OUTPUTLATCH Register.............................................................................................................................. 1757
Figure 11-139. OUTPUTLATCHCLR Register.......................................................................................................................1759
Figure 11-140. OUTPUTLATCHFRC Register.......................................................................................................................1761
Figure 11-141. OUTPUTLATCHENABLE Register................................................................................................................1763
Figure 11-142. OUTPUTINV Register....................................................................................................................................1765
Figure 11-143. OUTPUTLOCK Register................................................................................................................................1767
Figure 12-1. DMA Block Diagram.......................................................................................................................................... 1770
Figure 12-2. DMA Trigger Architecture.................................................................................................................................. 1772
Figure 12-3. Peripheral Interrupt Trigger Input Diagram........................................................................................................1773
Figure 12-4. DMA State Diagram.......................................................................................................................................... 1781
Figure 12-5. 3-Stage Pipeline DMA Transfer.........................................................................................................................1782
Figure 12-6. 3-stage Pipeline with One Read Stall................................................................................................................1782
Figure 12-7. Overrun Detection Logic....................................................................................................................................1785
Figure 12-8. DMACTRL Register...........................................................................................................................................1790
Figure 12-9. DEBUGCTRL Register......................................................................................................................................1791
Figure 12-10. PRIORITYCTRL1 Register..............................................................................................................................1792
Figure 12-11. PRIORITYSTAT Register.................................................................................................................................1793
Figure 12-12. MODE Register............................................................................................................................................... 1795
Figure 12-13. CONTROL Register........................................................................................................................................ 1797
Figure 12-14. BURST_SIZE Register....................................................................................................................................1799
Figure 12-15. BURST_COUNT Register............................................................................................................................... 1800
Figure 12-16. SRC_BURST_STEP Register.........................................................................................................................1801
Figure 12-17. DST_BURST_STEP Register......................................................................................................................... 1802
Figure 12-18. TRANSFER_SIZE Register.............................................................................................................................1803
Figure 12-19. TRANSFER_COUNT Register........................................................................................................................1804
Figure 12-20. SRC_TRANSFER_STEP Register..................................................................................................................1805
Figure 12-21. DST_TRANSFER_STEP Register.................................................................................................................. 1806
Figure 12-22. SRC_WRAP_SIZE Register............................................................................................................................1807
Figure 12-23. SRC_WRAP_COUNT Register.......................................................................................................................1808
Figure 12-24. SRC_WRAP_STEP Register.......................................................................................................................... 1809
Figure 12-25. DST_WRAP_SIZE Register............................................................................................................................ 1810
Figure 12-26. DST_WRAP_COUNT Register........................................................................................................................1811
Figure 12-27. DST_WRAP_STEP Register...........................................................................................................................1812
Figure 12-28. SRC_BEG_ADDR_SHADOW Register.......................................................................................................... 1813
Figure 12-29. SRC_ADDR_SHADOW Register.................................................................................................................... 1814
Figure 12-30. SRC_BEG_ADDR_ACTIVE Register..............................................................................................................1815
Figure 12-31. SRC_ADDR_ACTIVE Register....................................................................................................................... 1816
Figure 12-32. DST_BEG_ADDR_SHADOW Register...........................................................................................................1817
Figure 12-33. DST_ADDR_SHADOW Register.................................................................................................................... 1818
Figure 12-34. DST_BEG_ADDR_ACTIVE Register.............................................................................................................. 1819
Figure 12-35. DST_ADDR_ACTIVE Register........................................................................................................................1820
Figure 13-1. ERAD Overview................................................................................................................................................ 1822
Figure 13-2. EBC Units Event Masking................................................................................................................................. 1824
Figure 13-3. System Event Counter Inputs............................................................................................................................1826
Figure 13-4. Event Masking and Exporting for CRC Qualifiers............................................................................................. 1834
Figure 13-5. PC Trace Operation...........................................................................................................................................1836
Figure 13-6. PC Trace Block Diagram................................................................................................................................... 1837
Figure 13-7. Trace Qualifier Input Conditioning Circuit..........................................................................................................1843
Figure 13-8. GLBL_EVENT_STAT Register.......................................................................................................................... 1857
Figure 13-9. GLBL_HALT_STAT Register............................................................................................................................. 1859
Figure 13-10. GLBL_ENABLE Register.................................................................................................................................1861
Figure 13-11. GLBL_CTM_RESET Register......................................................................................................................... 1863
Figure 13-12. GLBL_NMI_CTL Register............................................................................................................................... 1864
Figure 13-13. GLBL_OWNER Register................................................................................................................................. 1866
Figure 13-14. GLBL_EVENT_AND_MASK Register............................................................................................................. 1867
Figure 13-15. GLBL_EVENT_OR_MASK Register............................................................................................................... 1872
Figure 13-16. GLBL_AND_EVENT_INT_MASK Register..................................................................................................... 1877
Figure 13-17. GLBL_OR_EVENT_INT_MASK Register....................................................................................................... 1878
Figure 13-18. HWBP_MASK Register................................................................................................................................... 1880

32 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 13-19. HWBP_REF Register...................................................................................................................................... 1881

Figure 13-20. HWBP_CLEAR Register................................................................................................................................. 1882
Figure 13-21. HWBP_CNTL Register....................................................................................................................................1883
Figure 13-22. HWBP_STATUS Register................................................................................................................................1885
Figure 13-23. CTM_CNTL Register.......................................................................................................................................1887
Figure 13-24. CTM_STATUS Register...................................................................................................................................1889
Figure 13-25. CTM_REF Register......................................................................................................................................... 1890
Figure 13-26. CTM_COUNT Register................................................................................................................................... 1891
Figure 13-27. CTM_MAX_COUNT Register..........................................................................................................................1892
Figure 13-28. CTM_INPUT_SEL Register.............................................................................................................................1893
Figure 13-29. CTM_CLEAR Register.................................................................................................................................... 1894
Figure 13-30. CTM_INPUT_SEL_2 Register.........................................................................................................................1895
Figure 13-31. CTM_INPUT_COND Register.........................................................................................................................1896
Figure 13-32. CRC_GLOBAL_CTRL Register...................................................................................................................... 1898
Figure 13-33. CRC_CURRENT Register...............................................................................................................................1901
Figure 13-34. CRC_SEED Register...................................................................................................................................... 1902
Figure 13-35. CRC_QUALIFIER Register............................................................................................................................. 1903
Figure 13-36. PCTRACE_GLOBAL Register........................................................................................................................ 1905
Figure 13-37. PCTRACE_BUFFER Register........................................................................................................................ 1906
Figure 13-38. PCTRACE_QUAL1 Register........................................................................................................................... 1907
Figure 13-39. PCTRACE_QUAL2 Register........................................................................................................................... 1908
Figure 13-40. PCTRACE_LOGPC_SOFTENABLE Register................................................................................................ 1909
Figure 13-41. PCTRACE_LOGPC_SOFTDISABLE Register............................................................................................... 1910
Figure 13-42. PCTRACE_BUFFER_BASE_y Register......................................................................................................... 1912
Figure 14-1. Analog Subsystem Block Diagram (128/80/64/56- Pins).................................................................................. 1915
Figure 14-2. Analog Subsystem Block Diagram (100-Pin QFP)............................................................................................1916
Figure 14-3. Analog Group Connections............................................................................................................................... 1917
Figure 14-4. Analog Subsystem Block Diagram with AGPIO Implementation.......................................................................1921
Figure 14-5. ADCOSDETECT Register.................................................................................................................................1931
Figure 14-6. REFCONFIGB Register.................................................................................................................................... 1932
Figure 14-7. INTERNALTESTCTL Register...........................................................................................................................1934
Figure 14-8. CONFIGLOCK Register.................................................................................................................................... 1936
Figure 14-9. TSNSCTL Register............................................................................................................................................1937
Figure 14-10. ANAREFPCTL Register.................................................................................................................................. 1938
Figure 14-11. ANAREFNCTL Register.................................................................................................................................. 1940
Figure 14-12. VMONCTL Register........................................................................................................................................ 1941
Figure 14-13. CMPHPMXSEL Register.................................................................................................................................1942
Figure 14-14. CMPLPMXSEL Register................................................................................................................................. 1943
Figure 14-15. CMPHNMXSEL Register.................................................................................................................................1944
Figure 14-16. CMPLNMXSEL Register................................................................................................................................. 1945
Figure 14-17. ADCDACLOOPBACK Register....................................................................................................................... 1946
Figure 14-18. CMPSSCTL Register...................................................................................................................................... 1948
Figure 14-19. CMPSSDACBUFCONFIG Register................................................................................................................ 1949
Figure 14-20. LOCK Register................................................................................................................................................ 1950
Figure 14-21. AGPIOCTRLA Register...................................................................................................................................1952
Figure 14-22. AGPIOCTRLB Register...................................................................................................................................1954
Figure 14-23. AGPIOCTRLG Register.................................................................................................................................. 1956
Figure 14-24. AGPIOCTRLH Register...................................................................................................................................1958
Figure 14-25. GPIOINENACTRL Register.............................................................................................................................1960
Figure 14-26. IO_DRVSEL Register...................................................................................................................................... 1961
Figure 14-27. IO_MODESEL Register...................................................................................................................................1962
Figure 14-28. ADCSOCFRCGB Register.............................................................................................................................. 1963
Figure 14-29. ADCSOCFRCGBSEL Register....................................................................................................................... 1965
Figure 15-1. ADC Module Block Diagram..............................................................................................................................1969
Figure 15-2. SOC Block Diagram.......................................................................................................................................... 1973
Figure 15-3. ADC Trigger Repeater Block Diagram.............................................................................................................. 1975
Figure 15-4. Oversampled ADC Trigger Example................................................................................................................. 1976
Figure 15-5. Undersampled ADC Trigger Example............................................................................................................... 1977
Figure 15-6. Oversampled ADC Trigger Example with Phase Delay.................................................................................... 1978
Figure 15-7. ADC Trigger Example with Phase Delay...........................................................................................................1978
Figure 15-8. ADC Interleaved Trigger Example (12 Samples Across 3 ADCs)..................................................................... 1979

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Figure 15-9. ADC Repeated Trigger Example with Sample Spread......................................................................................1980

Figure 15-10. Trigger Repeater Repeat Logic....................................................................................................................... 1982
Figure 15-11. Single-Ended Input Model............................................................................................................................... 1983
Figure 15-12. ADC with External Input Mux.......................................................................................................................... 1985
Figure 15-13. ADC with Multiple External Input Muxes and Shared Selection......................................................................1986
Figure 15-14. ADC External Channel Select Timing Example...............................................................................................1987
Figure 15-15. ADC External Channel Timing Example in Preselect Mode............................................................................1988
Figure 15-16. ADC External Channel Select Timing Example with Asynchronous Trigger................................................... 1989
Figure 15-17. ADC External Channel Timing Example in Preselect Mode with Asynchronous Trigger................................ 1990
Figure 15-18. Round Robin Priority Example........................................................................................................................ 1994
Figure 15-19. High Priority Example......................................................................................................................................1995
Figure 15-20. Burst Priority Example.....................................................................................................................................1997
Figure 15-21. ADC EOC Interrupts........................................................................................................................................1998
Figure 15-22. ADC PPB Block Diagram................................................................................................................................ 2001
Figure 15-23. ADC PPB Interrupt Event................................................................................................................................ 2004
Figure 15-24. ADC PPB Limit Compare and Zero-Crossing Logic........................................................................................2004
Figure 15-25. ADC PPB Limit Filter Logic............................................................................................................................. 2005
Figure 15-26. Opens/Shorts Detection Circuit....................................................................................................................... 2008
Figure 15-27. Input Circuit Equivalent with OSDETECT Enabled......................................................................................... 2009
Figure 15-28. ADC Timings for 12-bit Mode in Early Interrupt Mode.....................................................................................2012
Figure 15-29. ADC Timings for 12-bit Mode in Late Interrupt Mode...................................................................................... 2013
Figure 15-30. Example: Basic Synchronous Operation.........................................................................................................2017
Figure 15-31. Example: Synchronous Operation with Multiple Trigger Sources................................................................... 2018
Figure 15-32. Example: Synchronous Operation with Uneven SOC Numbers..................................................................... 2019
Figure 15-33. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow..................................... 2019
Figure 15-34. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions........................................ 2020
Figure 15-35. ADC Reference System.................................................................................................................................. 2023
Figure 15-36. CMPSS to ADC Loopback Connection........................................................................................................... 2024
Figure 15-37. ADCRESULT0 Register...................................................................................................................................2042
Figure 15-38. ADCRESULT1 Register...................................................................................................................................2043
Figure 15-39. ADCRESULT2 Register...................................................................................................................................2044
Figure 15-40. ADCRESULT3 Register...................................................................................................................................2045
Figure 15-41. ADCRESULT4 Register...................................................................................................................................2046
Figure 15-42. ADCRESULT5 Register...................................................................................................................................2047
Figure 15-43. ADCRESULT6 Register...................................................................................................................................2048
Figure 15-44. ADCRESULT7 Register...................................................................................................................................2049
Figure 15-45. ADCRESULT8 Register...................................................................................................................................2050
Figure 15-46. ADCRESULT9 Register...................................................................................................................................2051
Figure 15-47. ADCRESULT10 Register.................................................................................................................................2052
Figure 15-48. ADCRESULT11 Register.................................................................................................................................2053
Figure 15-49. ADCRESULT12 Register.................................................................................................................................2054
Figure 15-50. ADCRESULT13 Register.................................................................................................................................2055
Figure 15-51. ADCRESULT14 Register.................................................................................................................................2056
Figure 15-52. ADCRESULT15 Register.................................................................................................................................2057
Figure 15-53. ADCPPB1RESULT Register........................................................................................................................... 2058
Figure 15-54. ADCPPB2RESULT Register........................................................................................................................... 2059
Figure 15-55. ADCPPB3RESULT Register........................................................................................................................... 2060
Figure 15-56. ADCPPB4RESULT Register........................................................................................................................... 2061
Figure 15-57. ADCPPB1SUM Register................................................................................................................................. 2062
Figure 15-58. ADCPPB1COUNT Register............................................................................................................................ 2063
Figure 15-59. ADCPPB2SUM Register................................................................................................................................. 2064
Figure 15-60. ADCPPB2COUNT Register............................................................................................................................ 2065
Figure 15-61. ADCPPB3SUM Register................................................................................................................................. 2066
Figure 15-62. ADCPPB3COUNT Register............................................................................................................................ 2067
Figure 15-63. ADCPPB4SUM Register................................................................................................................................. 2068
Figure 15-64. ADCPPB4COUNT Register............................................................................................................................ 2069
Figure 15-65. ADCPPB1MAX Register................................................................................................................................. 2070
Figure 15-66. ADCPPB1MAXI Register................................................................................................................................ 2071
Figure 15-67. ADCPPB1MIN Register...................................................................................................................................2072
Figure 15-68. ADCPPB1MINI Register..................................................................................................................................2073
Figure 15-69. ADCPPB2MAX Register................................................................................................................................. 2074

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Figure 15-70. ADCPPB2MAXI Register................................................................................................................................ 2075

Figure 15-71. ADCPPB2MIN Register...................................................................................................................................2076
Figure 15-72. ADCPPB2MINI Register..................................................................................................................................2077
Figure 15-73. ADCPPB3MAX Register................................................................................................................................. 2078
Figure 15-74. ADCPPB3MAXI Register................................................................................................................................ 2079
Figure 15-75. ADCPPB3MIN Register...................................................................................................................................2080
Figure 15-76. ADCPPB3MINI Register..................................................................................................................................2081
Figure 15-77. ADCPPB4MAX Register................................................................................................................................. 2082
Figure 15-78. ADCPPB4MAXI Register................................................................................................................................ 2083
Figure 15-79. ADCPPB4MIN Register...................................................................................................................................2084
Figure 15-80. ADCPPB4MINI Register..................................................................................................................................2085
Figure 15-81. ADCCTL1 Register..........................................................................................................................................2090
Figure 15-82. ADCCTL2 Register..........................................................................................................................................2092
Figure 15-83. ADCBURSTCTL Register............................................................................................................................... 2093
Figure 15-84. ADCINTFLG Register......................................................................................................................................2095
Figure 15-85. ADCINTFLGCLR Register.............................................................................................................................. 2098
Figure 15-86. ADCINTOVF Register..................................................................................................................................... 2099
Figure 15-87. ADCINTOVFCLR Register.............................................................................................................................. 2100
Figure 15-88. ADCINTSEL1N2 Register............................................................................................................................... 2101
Figure 15-89. ADCINTSEL3N4 Register............................................................................................................................... 2103
Figure 15-90. ADCSOCPRICTL Register..............................................................................................................................2105
Figure 15-91. ADCINTSOCSEL1 Register............................................................................................................................ 2107
Figure 15-92. ADCSOCFLG1 Register.................................................................................................................................. 2110
Figure 15-93. ADCSOCFRC1 Register..................................................................................................................................2114
Figure 15-94. ADCSOCOVF1 Register..................................................................................................................................2119
Figure 15-95. ADCSOCOVFCLR1 Register.......................................................................................................................... 2122
Figure 15-96. ADCSOC0CTL Register..................................................................................................................................2125
Figure 15-97. ADCSOC1CTL Register..................................................................................................................................2128
Figure 15-98. ADCSOC2CTL Register..................................................................................................................................2131
Figure 15-99. ADCSOC3CTL Register..................................................................................................................................2134
Figure 15-100. ADCSOC4CTL Register................................................................................................................................2137
Figure 15-101. ADCSOC5CTL Register................................................................................................................................2140
Figure 15-102. ADCSOC6CTL Register................................................................................................................................2143
Figure 15-103. ADCSOC7CTL Register................................................................................................................................2146
Figure 15-104. ADCSOC8CTL Register................................................................................................................................2149
Figure 15-105. ADCSOC9CTL Register................................................................................................................................2152
Figure 15-106. ADCSOC10CTL Register..............................................................................................................................2155
Figure 15-107. ADCSOC11CTL Register.............................................................................................................................. 2158
Figure 15-108. ADCSOC12CTL Register..............................................................................................................................2161
Figure 15-109. ADCSOC13CTL Register..............................................................................................................................2164
Figure 15-110. ADCSOC14CTL Register.............................................................................................................................. 2167
Figure 15-111. ADCSOC15CTL Register.............................................................................................................................. 2170
Figure 15-112. ADCEVTSTAT Register................................................................................................................................. 2173
Figure 15-113. ADCEVTCLR Register...................................................................................................................................2176
Figure 15-114. ADCEVTSEL Register................................................................................................................................... 2178
Figure 15-115. ADCEVTINTSEL Register............................................................................................................................. 2180
Figure 15-116. ADCCOUNTER Register............................................................................................................................... 2182
Figure 15-117. ADCREV Register......................................................................................................................................... 2183
Figure 15-118. ADCOFFTRIM Register.................................................................................................................................2184
Figure 15-119. ADCCONFIG2 Register.................................................................................................................................2185
Figure 15-120. ADCPPB1CONFIG Register......................................................................................................................... 2186
Figure 15-121. ADCPPB1STAMP Register........................................................................................................................... 2188
Figure 15-122. ADCPPB1OFFCAL Register......................................................................................................................... 2189
Figure 15-123. ADCPPB1OFFREF Register.........................................................................................................................2190
Figure 15-124. ADCPPB1TRIPHI Register........................................................................................................................... 2191
Figure 15-125. ADCPPB1TRIPLO Register.......................................................................................................................... 2192
Figure 15-126. ADCPPBTRIP1FILCTL Register................................................................................................................... 2193
Figure 15-127. ADCPPBTRIP1FILCLKCTL Register............................................................................................................ 2194
Figure 15-128. ADCPPB2CONFIG Register......................................................................................................................... 2195
Figure 15-129. ADCPPB2STAMP Register........................................................................................................................... 2197
Figure 15-130. ADCPPB2OFFCAL Register......................................................................................................................... 2198

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 35

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Figure 15-131. ADCPPB2OFFREF Register.........................................................................................................................2199

Figure 15-132. ADCPPB2TRIPHI Register........................................................................................................................... 2200
Figure 15-133. ADCPPB2TRIPLO Register.......................................................................................................................... 2201
Figure 15-134. ADCPPBTRIP2FILCTL Register................................................................................................................... 2202
Figure 15-135. ADCPPBTRIP2FILCLKCTL Register............................................................................................................ 2203
Figure 15-136. ADCPPB3CONFIG Register......................................................................................................................... 2204
Figure 15-137. ADCPPB3STAMP Register........................................................................................................................... 2206
Figure 15-138. ADCPPB3OFFCAL Register......................................................................................................................... 2207
Figure 15-139. ADCPPB3OFFREF Register.........................................................................................................................2208
Figure 15-140. ADCPPB3TRIPHI Register........................................................................................................................... 2209
Figure 15-141. ADCPPB3TRIPLO Register.......................................................................................................................... 2210
Figure 15-142. ADCPPBTRIP3FILCTL Register................................................................................................................... 2211
Figure 15-143. ADCPPBTRIP3FILCLKCTL Register............................................................................................................ 2212
Figure 15-144. ADCPPB4CONFIG Register......................................................................................................................... 2213
Figure 15-145. ADCPPB4STAMP Register........................................................................................................................... 2215
Figure 15-146. ADCPPB4OFFCAL Register......................................................................................................................... 2216
Figure 15-147. ADCPPB4OFFREF Register.........................................................................................................................2217
Figure 15-148. ADCPPB4TRIPHI Register........................................................................................................................... 2218
Figure 15-149. ADCPPB4TRIPLO Register.......................................................................................................................... 2219
Figure 15-150. ADCPPBTRIP4FILCTL Register................................................................................................................... 2220
Figure 15-151. ADCPPBTRIP4FILCLKCTL Register............................................................................................................ 2221
Figure 15-152. ADCINTCYCLE Register...............................................................................................................................2222
Figure 15-153. ADCINLTRIM1 Register................................................................................................................................ 2223
Figure 15-154. ADCINLTRIM2 Register................................................................................................................................ 2224
Figure 15-155. ADCINLTRIM3 Register................................................................................................................................ 2225
Figure 15-156. ADCINLTRIM4 Register................................................................................................................................ 2226
Figure 15-157. ADCINLTRIM5 Register................................................................................................................................ 2227
Figure 15-158. ADCINLTRIM6 Register................................................................................................................................ 2228
Figure 15-159. ADCREV2 Register....................................................................................................................................... 2229
Figure 15-160. REP1CTL Register........................................................................................................................................2230
Figure 15-161. REP1N Register............................................................................................................................................ 2233
Figure 15-162. REP1PHASE Register.................................................................................................................................. 2234
Figure 15-163. REP1SPREAD Register................................................................................................................................2235
Figure 15-164. REP1FRC Register....................................................................................................................................... 2236
Figure 15-165. REP2CTL Register........................................................................................................................................2237
Figure 15-166. REP2N Register............................................................................................................................................ 2240
Figure 15-167. REP2PHASE Register.................................................................................................................................. 2241
Figure 15-168. REP2SPREAD Register................................................................................................................................2242
Figure 15-169. REP2FRC Register....................................................................................................................................... 2243
Figure 15-170. ADCPPB1LIMIT Register.............................................................................................................................. 2244
Figure 15-171. ADCPPBP1PCOUNT Register......................................................................................................................2245
Figure 15-172. ADCPPB1CONFIG2 Register....................................................................................................................... 2246
Figure 15-173. ADCPPB1PSUM Register.............................................................................................................................2248
Figure 15-174. ADCPPB1PMAX Register............................................................................................................................. 2249
Figure 15-175. ADCPPB1PMAXI Register............................................................................................................................ 2250
Figure 15-176. ADCPPB1PMIN Register.............................................................................................................................. 2251
Figure 15-177. ADCPPB1PMINI Register............................................................................................................................. 2252
Figure 15-178. ADCPPB1TRIPLO2 Register........................................................................................................................ 2253
Figure 15-179. ADCPPB2LIMIT Register.............................................................................................................................. 2254
Figure 15-180. ADCPPBP2PCOUNT Register......................................................................................................................2255
Figure 15-181. ADCPPB2CONFIG2 Register....................................................................................................................... 2256
Figure 15-182. ADCPPB2PSUM Register.............................................................................................................................2258
Figure 15-183. ADCPPB2PMAX Register............................................................................................................................. 2259
Figure 15-184. ADCPPB2PMAXI Register............................................................................................................................ 2260
Figure 15-185. ADCPPB2PMIN Register.............................................................................................................................. 2261
Figure 15-186. ADCPPB2PMINI Register............................................................................................................................. 2262
Figure 15-187. ADCPPB2TRIPLO2 Register........................................................................................................................ 2263
Figure 15-188. ADCPPB3LIMIT Register.............................................................................................................................. 2264
Figure 15-189. ADCPPBP3PCOUNT Register......................................................................................................................2265
Figure 15-190. ADCPPB3CONFIG2 Register....................................................................................................................... 2266
Figure 15-191. ADCPPB3PSUM Register.............................................................................................................................2268

36 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 15-192. ADCPPB3PMAX Register............................................................................................................................. 2269

Figure 15-193. ADCPPB3PMAXI Register............................................................................................................................ 2270
Figure 15-194. ADCPPB3PMIN Register.............................................................................................................................. 2271
Figure 15-195. ADCPPB3PMINI Register............................................................................................................................. 2272
Figure 15-196. ADCPPB3TRIPLO2 Register........................................................................................................................ 2273
Figure 15-197. ADCPPB4LIMIT Register.............................................................................................................................. 2274
Figure 15-198. ADCPPBP4PCOUNT Register......................................................................................................................2275
Figure 15-199. ADCPPB4CONFIG2 Register....................................................................................................................... 2276
Figure 15-200. ADCPPB4PSUM Register.............................................................................................................................2278
Figure 15-201. ADCPPB4PMAX Register............................................................................................................................. 2279
Figure 15-202. ADCPPB4PMAXI Register............................................................................................................................ 2280
Figure 15-203. ADCPPB4PMIN Register.............................................................................................................................. 2281
Figure 15-204. ADCPPB4PMINI Register............................................................................................................................. 2282
Figure 15-205. ADCPPB4TRIPLO2 Register........................................................................................................................ 2283
Figure 16-1. DAC Module Block Diagram..............................................................................................................................2285
Figure 16-2. DACREV Register............................................................................................................................................. 2291
Figure 16-3. DACCTL Register..............................................................................................................................................2292
Figure 16-4. DACVALA Register............................................................................................................................................2293
Figure 16-5. DACVALS Register............................................................................................................................................2294
Figure 16-6. DACOUTEN Register........................................................................................................................................2295
Figure 16-7. DACLOCK Register...........................................................................................................................................2296
Figure 16-8. DACTRIM Register............................................................................................................................................2297
Figure 17-1. CMPSS Module Block Diagram........................................................................................................................ 2300
Figure 17-2. Comparator Block Diagram............................................................................................................................... 2300
Figure 17-3. Reference DAC Block Diagram.........................................................................................................................2301
Figure 17-4. Ramp Generator Block Diagram....................................................................................................................... 2303
Figure 17-5. Ramp Generator Behavior................................................................................................................................ 2305
Figure 17-6. Digital Filter Behavior........................................................................................................................................ 2306
Figure 17-7. COMPCTL Register.......................................................................................................................................... 2316
Figure 17-8. COMPHYSCTL Register................................................................................................................................... 2318
Figure 17-9. COMPSTS Register.......................................................................................................................................... 2319
Figure 17-10. COMPSTSCLR Register................................................................................................................................. 2320
Figure 17-11. COMPDACHCTL Register...............................................................................................................................2321
Figure 17-12. COMPDACHCTL2 Register............................................................................................................................ 2323
Figure 17-13. DACHVALS Register....................................................................................................................................... 2324
Figure 17-14. DACHVALA Register....................................................................................................................................... 2325
Figure 17-15. RAMPHREFA Register....................................................................................................................................2326
Figure 17-16. RAMPHREFS Register................................................................................................................................... 2327
Figure 17-17. RAMPHSTEPVALA Register...........................................................................................................................2328
Figure 17-18. RAMPHCTLA Register....................................................................................................................................2329
Figure 17-19. RAMPHSTEPVALS Register...........................................................................................................................2330
Figure 17-20. RAMPHCTLS Register....................................................................................................................................2331
Figure 17-21. RAMPHSTS Register...................................................................................................................................... 2332
Figure 17-22. DACLVALS Register........................................................................................................................................2333
Figure 17-23. DACLVALA Register........................................................................................................................................2334
Figure 17-24. RAMPHDLYA Register.................................................................................................................................... 2335
Figure 17-25. RAMPHDLYS Register.................................................................................................................................... 2336
Figure 17-26. CTRIPLFILCTL Register................................................................................................................................. 2337
Figure 17-27. CTRIPLFILCLKCTL Register.......................................................................................................................... 2338
Figure 17-28. CTRIPHFILCTL Register.................................................................................................................................2339
Figure 17-29. CTRIPHFILCLKCTL Register..........................................................................................................................2340
Figure 17-30. COMPLOCK Register..................................................................................................................................... 2341
Figure 17-31. COMPDACLCTL Register...............................................................................................................................2342
Figure 17-32. COMPDACLCTL2 Register.............................................................................................................................2344
Figure 17-33. RAMPLREFA Register.................................................................................................................................... 2345
Figure 17-34. RAMPLREFS Register.................................................................................................................................... 2346
Figure 17-35. RAMPLSTEPVALA Register........................................................................................................................... 2347
Figure 17-36. RAMPLCTLA Register.................................................................................................................................... 2348
Figure 17-37. RAMPLSTEPVALS Register........................................................................................................................... 2349
Figure 17-38. RAMPLCTLS Register.................................................................................................................................... 2350
Figure 17-39. RAMPLSTS Register.......................................................................................................................................2351

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 37

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Figure 17-40. RAMPLDLYA Register.....................................................................................................................................2352

Figure 17-41. RAMPLDLYS Register.....................................................................................................................................2353
Figure 17-42. CTRIPLFILCLKCTL2 Register........................................................................................................................ 2354
Figure 17-43. CTRIPHFILCLKCTL2 Register........................................................................................................................2355
Figure 18-1. PGA Block Diagram.......................................................................................................................................... 2357
Figure 18-2. Buffer Mode.......................................................................................................................................................2359
Figure 18-3. Standalone Mode.............................................................................................................................................. 2360
Figure 18-4. Non-inverting Mode........................................................................................................................................... 2361
Figure 18-5. Subtractor Mode................................................................................................................................................2362
Figure 18-6. Low-Pass Filter Using External Capacitor.........................................................................................................2364
Figure 18-7. PGA Offset Trim................................................................................................................................................ 2365
Figure 18-8. PGA Gain Error................................................................................................................................................. 2365
Figure 18-9. General Chopping Technique............................................................................................................................2366
Figure 18-10. ADC-Assisted Chopping Block Diagram......................................................................................................... 2366
Figure 18-11. Level Shifting Using Internal DAC................................................................................................................... 2368
Figure 18-12. Sharing PGA_NEG Pin Between PGA Modules............................................................................................. 2370
Figure 18-13. Three-phase Current Sensing Using PGA_NEG_SHARED Feature.............................................................. 2370
Figure 18-14. PGA Pin Alternate Functions...........................................................................................................................2371
Figure 18-15. Signal Conditioning Using Non-inverting Mode...............................................................................................2372
Figure 18-16. Buffer Mode Example...................................................................................................................................... 2372
Figure 18-17. PGA Shunt Current Example.......................................................................................................................... 2373
Figure 18-18. Bidirectional Current Sensing..........................................................................................................................2374
Figure 18-19. PGACTL Register............................................................................................................................................2378
Figure 18-20. MUXSEL Register........................................................................................................................................... 2379
Figure 18-21. OFFSETTRIM Register................................................................................................................................... 2380
Figure 18-22. PGATYPE Register......................................................................................................................................... 2381
Figure 18-23. PGALOCK Register.........................................................................................................................................2382
Figure 19-1. Multiple ePWM Modules....................................................................................................................................2387
Figure 19-2. Submodules and Signal Connections for an ePWM Module.............................................................................2388
Figure 19-3. ePWM Modules and Critical Internal Signal Interconnects............................................................................... 2390
Figure 19-4. Time-Base Submodule...................................................................................................................................... 2393
Figure 19-5. Time-Base Submodule Signals and Registers.................................................................................................. 2394
Figure 19-6. Time-Base Frequency and Period.....................................................................................................................2396
Figure 19-7. Time-Base Counter Synchronization Scheme...................................................................................................2398
Figure 19-8. ePWM External SYNC Output...........................................................................................................................2399
Figure 19-9. Time-Base Up-Count Mode Waveforms............................................................................................................2402
Figure 19-10. Time-Base Down-Count Mode Waveforms..................................................................................................... 2403
Figure 19-11. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event....... 2404
Figure 19-12. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event............2405
Figure 19-13. Global Load: Signals and Registers................................................................................................................ 2406
Figure 19-14. One-Shot Sync Mode...................................................................................................................................... 2407
Figure 19-15. Counter-Compare Submodule........................................................................................................................ 2408
Figure 19-16. Detailed View of the Counter-Compare Submodule........................................................................................2409
Figure 19-17. Counter-Compare Event Waveforms in Up-Count Mode................................................................................ 2412
Figure 19-18. Counter-Compare Events in Down-Count Mode.............................................................................................2412
Figure 19-19. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event....................................................................................................................................................... 2413
Figure 19-20. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event.................................................................................................................................................................................. 2413
Figure 19-21. Action-Qualifier Submodule.............................................................................................................................2414
Figure 19-22. Action-Qualifier Submodule Inputs and Outputs............................................................................................. 2415
Figure 19-23. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs..........................................................2416
Figure 19-24. AQCTL[SHDWAQAMODE]............................................................................................................................. 2419
Figure 19-25. AQCTL[SHDWAQBMODE]............................................................................................................................. 2419
Figure 19-26. Up-Down Count Mode Symmetrical Waveform...............................................................................................2421
Figure 19-27. Up, Single Edge Asymmetric Waveform, with Independent Modulation on EPWMxA and EPWMxB—
Active High......................................................................................................................................................................... 2422
Figure 19-28. Up, Single Edge Asymmetric Waveform with Independent Modulation on EPWMxA and EPWMxB—
Active Low..........................................................................................................................................................................2423
Figure 19-29. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA..................2424

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Figure 19-30. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Active Low.....................................................................................................................................................2424
Figure 19-31. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Complementary.............................................................................................................................................2425
Figure 19-32. Up-Down Count, Dual-Edge Asymmetric Waveform, with Independent Modulation on EPWMxA—Active
Low.....................................................................................................................................................................................2425
Figure 19-33. Up-Down Count, PWM Waveform Generation Utilizing T1 and T2 Events..................................................... 2426
Figure 19-34. Dead_Band Submodule.................................................................................................................................. 2427
Figure 19-35. Configuration Options for the Dead-Band Submodule.................................................................................... 2430
Figure 19-36. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)..................................................................... 2432
Figure 19-37. PWM Chopper Submodule..............................................................................................................................2434
Figure 19-38. PWM Chopper Submodule Operational Details.............................................................................................. 2435
Figure 19-39. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only............................................ 2435
Figure 19-40. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses........... 2436
Figure 19-41. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses 2437
Figure 19-42. Trip-Zone Submodule......................................................................................................................................2438
Figure 19-43. Trip-Zone Submodule Mode Control Logic......................................................................................................2442
Figure 19-44. Trip-Zone Submodule Interrupt Logic..............................................................................................................2443
Figure 19-45. Event-Trigger Submodule................................................................................................................................2444
Figure 19-46. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs...................................................... 2445
Figure 19-47. Event-Trigger Interrupt Generator................................................................................................................... 2447
Figure 19-48. Event-Trigger SOCA Pulse Generator............................................................................................................ 2448
Figure 19-49. Event-Trigger SOCB Pulse Generator............................................................................................................ 2448
Figure 19-50. Digital-Compare Submodule High-Level Block Diagram.................................................................................2449
Figure 19-51. GPIO MUX-to-Trip Input Connectivity............................................................................................................. 2450
Figure 19-52. DCxEVT1 Event Triggering............................................................................................................................. 2453
Figure 19-53. DCxEVT2 Event Triggering............................................................................................................................. 2454
Figure 19-54. Event Filtering................................................................................................................................................. 2455
Figure 19-55. Blanking Window Timing Diagram...................................................................................................................2456
Figure 19-56. Valley Switching...............................................................................................................................................2458
Figure 19-57. ePWM X-BAR..................................................................................................................................................2459
Figure 19-58. Simplified ePWM Module................................................................................................................................ 2460
Figure 19-59. EPWM1 Configured as a Typical Sync Source, EPWM2 Configured as a Sync Receiver ............................ 2461
Figure 19-60. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ............................................................. 2462
Figure 19-61. Buck Waveforms for Control of Four Buck Stages (Note: Only three bucks shown here).............................. 2463
Figure 19-62. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1).............................................................................. 2464
Figure 19-63. Buck Waveforms for Control of Four Buck Stages (Note: FPWM2 = FPWM1).................................................... 2465
Figure 19-64. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1)............................................................................ 2466
Figure 19-65. Half-H Bridge Waveforms for Control of Two Half-H Bridge Stages (Note: Here FPWM2 = FPWM1)................. 2467
Figure 19-66. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control..........................................2468
Figure 19-67. 3-Phase Inverter Waveforms for Control of Dual 3-Phase Inverter Stages (Only One Inverter Shown)......... 2469
Figure 19-68. Configuring Two PWM Modules for Phase Control......................................................................................... 2470
Figure 19-69. Timing Waveforms Associated with Phase Control Between Two Modules....................................................2471
Figure 19-70. Control of 3-Phase Interleaved DC/DC Converter.......................................................................................... 2472
Figure 19-71. 3-Phase Interleaved DC/DC Converter Waveforms for Control of 3-Phase Interleaved DC/DC Converter....2473
Figure 19-72. Control of Full-H Bridge Stage (FPWM2 = FPWM1)............................................................................................ 2474
Figure 19-73. ZVS Full-H Bridge Waveforms........................................................................................................................ 2475
Figure 19-74. Peak Current Mode Control of Buck Converter...............................................................................................2476
Figure 19-75. Peak Current Mode Control Waveforms for Control of Buck Converter.......................................................... 2476
Figure 19-76. Control of Two Resonant Converter Stages....................................................................................................2477
Figure 19-77. H-Bridge LLC Resonant Converter PWM Waveforms.....................................................................................2477
Figure 19-78. HRPWM Block Diagram.................................................................................................................................. 2479
Figure 19-79. Resolution Calculations for Conventionally Generated PWM......................................................................... 2480
Figure 19-80. Operating Logic Using MEP............................................................................................................................ 2481
Figure 19-81. HRPWM Extension Registers and Memory Configuration.............................................................................. 2482
Figure 19-82. HRPWM System Interface.............................................................................................................................. 2483
Figure 19-83. HRPWM and HRCAL Source Clock................................................................................................................2484
Figure 19-84. Required PWM Waveform for a Requested Duty = 40.5%..............................................................................2487
Figure 19-85. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................ 2490
Figure 19-86. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................2491
Figure 19-87. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 1)........................................................2491

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Figure 19-88. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 1)..............................................2491
Figure 19-89. Simple Buck Controlled Converter Using a Single PWM................................................................................ 2498
Figure 19-90. PWM Waveform Generated for Simple Buck Controlled Converter................................................................ 2498
Figure 19-91. Simple Reconstruction Filter for a PWM-based DAC......................................................................................2500
Figure 19-92. PWM Waveform Generated for the PWM DAC Function................................................................................ 2500
Figure 19-93. TBCTL Register...............................................................................................................................................2528
Figure 19-94. TBCTL2 Register.............................................................................................................................................2530
Figure 19-95. EPWMSYNCINSEL Register.......................................................................................................................... 2531
Figure 19-96. TBCTR Register.............................................................................................................................................. 2532
Figure 19-97. TBSTS Register.............................................................................................................................................. 2533
Figure 19-98. EPWMSYNCOUTEN Register........................................................................................................................ 2534
Figure 19-99. TBCTL3 Register.............................................................................................................................................2536
Figure 19-100. CMPCTL Register......................................................................................................................................... 2537
Figure 19-101. CMPCTL2 Register....................................................................................................................................... 2539
Figure 19-102. DBCTL Register............................................................................................................................................ 2541
Figure 19-103. DBCTL2 Register.......................................................................................................................................... 2544
Figure 19-104. AQCTL Register............................................................................................................................................ 2545
Figure 19-105. AQTSRCSEL Register.................................................................................................................................. 2547
Figure 19-106. PCCTL Register............................................................................................................................................ 2548
Figure 19-107. VCAPCTL Register....................................................................................................................................... 2550
Figure 19-108. VCNTCFG Register.......................................................................................................................................2552
Figure 19-109. HRCNFG Register.........................................................................................................................................2554
Figure 19-110. HRPWR Register...........................................................................................................................................2556
Figure 19-111. HRMSTEP Register....................................................................................................................................... 2557
Figure 19-112. HRCNFG2 Register....................................................................................................................................... 2558
Figure 19-113. HRPCTL Register.......................................................................................................................................... 2559
Figure 19-114. TRREM Register............................................................................................................................................2561
Figure 19-115. GLDCTL Register.......................................................................................................................................... 2562
Figure 19-116. GLDCFG Register......................................................................................................................................... 2564
Figure 19-117. EPWMXLINK Register...................................................................................................................................2566
Figure 19-118. AQCTLA Register.......................................................................................................................................... 2568
Figure 19-119. AQCTLA2 Register........................................................................................................................................ 2570
Figure 19-120. AQCTLB Register..........................................................................................................................................2571
Figure 19-121. AQCTLB2 Register........................................................................................................................................2573
Figure 19-122. AQSFRC Register......................................................................................................................................... 2574
Figure 19-123. AQCSFRC Register...................................................................................................................................... 2575
Figure 19-124. DBREDHR Register...................................................................................................................................... 2576
Figure 19-125. DBRED Register........................................................................................................................................... 2577
Figure 19-126. DBFEDHR Register.......................................................................................................................................2578
Figure 19-127. DBFED Register............................................................................................................................................2579
Figure 19-128. TBPHS Register............................................................................................................................................ 2580
Figure 19-129. TBPRDHR Register.......................................................................................................................................2581
Figure 19-130. TBPRD Register............................................................................................................................................2582
Figure 19-131. CMPA Register.............................................................................................................................................. 2583
Figure 19-132. CMPB Register..............................................................................................................................................2584
Figure 19-133. CMPC Register............................................................................................................................................. 2585
Figure 19-134. CMPD Register............................................................................................................................................. 2586
Figure 19-135. GLDCTL2 Register........................................................................................................................................2587
Figure 19-136. SWVDELVAL Register...................................................................................................................................2588
Figure 19-137. TZSEL Register.............................................................................................................................................2589
Figure 19-138. TZDCSEL Register........................................................................................................................................2591
Figure 19-139. TZCTL Register.............................................................................................................................................2592
Figure 19-140. TZCTL2 Register...........................................................................................................................................2594
Figure 19-141. TZCTLDCA Register..................................................................................................................................... 2596
Figure 19-142. TZCTLDCB Register..................................................................................................................................... 2598
Figure 19-143. TZEINT Register........................................................................................................................................... 2600
Figure 19-144. TZFLG Register.............................................................................................................................................2601
Figure 19-145. TZCBCFLG Register..................................................................................................................................... 2603
Figure 19-146. TZOSTFLG Register..................................................................................................................................... 2605
Figure 19-147. TZCLR Register............................................................................................................................................ 2607
Figure 19-148. TZCBCCLR Register.....................................................................................................................................2609

40 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 19-149. TZOSTCLR Register..................................................................................................................................... 2610

Figure 19-150. TZFRC Register.............................................................................................................................................2611
Figure 19-151. ETSEL Register.............................................................................................................................................2612
Figure 19-152. ETPS Register...............................................................................................................................................2615
Figure 19-153. ETFLG Register............................................................................................................................................ 2618
Figure 19-154. ETCLR Register............................................................................................................................................ 2619
Figure 19-155. ETFRC Register............................................................................................................................................ 2620
Figure 19-156. ETINTPS Register.........................................................................................................................................2621
Figure 19-157. ETSOCPS Register.......................................................................................................................................2622
Figure 19-158. ETCNTINITCTL Register.............................................................................................................................. 2624
Figure 19-159. ETCNTINIT Register..................................................................................................................................... 2625
Figure 19-160. DCTRIPSEL Register....................................................................................................................................2626
Figure 19-161. DCACTL Register..........................................................................................................................................2628
Figure 19-162. DCBCTL Register..........................................................................................................................................2630
Figure 19-163. DCFCTL Register..........................................................................................................................................2632
Figure 19-164. DCCAPCTL Register.....................................................................................................................................2634
Figure 19-165. DCFOFFSET Register.................................................................................................................................. 2636
Figure 19-166. DCFOFFSETCNT Register........................................................................................................................... 2637
Figure 19-167. DCFWINDOW Register.................................................................................................................................2638
Figure 19-168. DCFWINDOWCNT Register..........................................................................................................................2639
Figure 19-169. BLANKPULSEMIXSEL Register................................................................................................................... 2640
Figure 19-170. DCCAP Register........................................................................................................................................... 2642
Figure 19-171. DCAHTRIPSEL Register...............................................................................................................................2643
Figure 19-172. DCALTRIPSEL Register................................................................................................................................2645
Figure 19-173. DCBHTRIPSEL Register...............................................................................................................................2647
Figure 19-174. DCBLTRIPSEL Register................................................................................................................................2649
Figure 19-175. EPWMLOCK Register................................................................................................................................... 2651
Figure 19-176. HWVDELVAL Register.................................................................................................................................. 2653
Figure 19-177. VCNTVAL Register........................................................................................................................................2654
Figure 20-1. Capture and APWM Modes of Operation..........................................................................................................2661
Figure 20-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode....................................................... 2662
Figure 20-3. eCAP Block Diagram.........................................................................................................................................2663
Figure 20-4. Event Prescale Control......................................................................................................................................2664
Figure 20-5. Prescale Function Waveforms...........................................................................................................................2664
Figure 20-6. Details of the Continuous/One-shot Block.........................................................................................................2665
Figure 20-7. Details of the Counter and Synchronization Block............................................................................................ 2666
Figure 20-8. eCAP Synchronization Scheme........................................................................................................................ 2667
Figure 20-9. Interrupts in eCAP Module................................................................................................................................ 2668
Figure 20-10. PWM Waveform Details Of APWM Mode Operation.......................................................................................2669
Figure 20-11. Time-Base Frequency and Period Calculation................................................................................................ 2670
Figure 20-12. Capture Sequence for Absolute Time-stamp and Rising-Edge Detect........................................................... 2671
Figure 20-13. Capture Sequence for Absolute Time-stamp with Rising- and Falling-Edge Detect....................................... 2672
Figure 20-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect....................................................... 2673
Figure 20-15. Capture Sequence for Delta Mode Time-stamp with Rising- and Falling-Edge Detect...................................2674
Figure 20-16. PWM Waveform Details of APWM Mode Operation....................................................................................... 2675
Figure 20-17. TSCTR Register.............................................................................................................................................. 2680
Figure 20-18. CTRPHS Register........................................................................................................................................... 2681
Figure 20-19. CAP1 Register.................................................................................................................................................2682
Figure 20-20. CAP2 Register.................................................................................................................................................2683
Figure 20-21. CAP3 Register.................................................................................................................................................2684
Figure 20-22. CAP4 Register.................................................................................................................................................2685
Figure 20-23. ECCTL0 Register............................................................................................................................................ 2686
Figure 20-24. ECCTL1 Register............................................................................................................................................ 2687
Figure 20-25. ECCTL2 Register............................................................................................................................................ 2689
Figure 20-26. ECEINT Register.............................................................................................................................................2691
Figure 20-27. ECFLG Register.............................................................................................................................................. 2693
Figure 20-28. ECCLR Register..............................................................................................................................................2695
Figure 20-29. ECFRC Register..............................................................................................................................................2696
Figure 20-30. ECAPSYNCINSEL Register............................................................................................................................2697
Figure 21-1. Optical Encoder Disk.........................................................................................................................................2699
Figure 21-2. QEP Encoder Output Signal for Forward/Reverse Movement.......................................................................... 2699

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Figure 21-3. Index Pulse Example.........................................................................................................................................2700

Figure 21-4. Using eQEP to Decode Signals from SinCos Transducer.................................................................................2703
Figure 21-5. Functional Block Diagram of the eQEP Peripheral........................................................................................... 2705
Figure 21-6. Functional Block Diagram of Decoder Unit....................................................................................................... 2707
Figure 21-7. Quadrature Decoder State Machine..................................................................................................................2708
Figure 21-8. Quadrature-clock and Direction Decoding........................................................................................................ 2709
Figure 21-9. Position Counter Reset by Index Pulse for 1000-Line Encoder (QPOSMAX = 3999 or 0xF9F)....................... 2711
Figure 21-10. Position Counter Underflow/Overflow (QPOSMAX = 4)..................................................................................2712
Figure 21-11. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)..................................................................2714
Figure 21-12. Strobe Event Latch (QEPCTL[SEL] = 1)......................................................................................................... 2714
Figure 21-13. Latching Position Counter on ADCSOCA/ADCSOCB Event.......................................................................... 2715
Figure 21-14. eQEP Position-compare Unit.......................................................................................................................... 2716
Figure 21-15. eQEP Position-compare Event Generation Points..........................................................................................2717
Figure 21-16. eQEP Position-compare Sync Output Pulse Stretcher................................................................................... 2717
Figure 21-17. eQEP Edge Capture Unit................................................................................................................................ 2719
Figure 21-18. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)...............................................2720
Figure 21-19. eQEP Edge Capture Unit - Timing Details...................................................................................................... 2720
Figure 21-20. eQEP Watchdog Timer....................................................................................................................................2722
Figure 21-21. eQEP Unit Timer Base.................................................................................................................................... 2722
Figure 21-22. QMA Module Block Diagram........................................................................................................................... 2723
Figure 21-23. QMA Mode-1................................................................................................................................................... 2724
Figure 21-24. QMA Mode-2................................................................................................................................................... 2725
Figure 21-25. eQEP Interrupt Generation..............................................................................................................................2726
Figure 21-26. QPOSCNT Register........................................................................................................................................ 2734
Figure 21-27. QPOSINIT Register.........................................................................................................................................2735
Figure 21-28. QPOSMAX Register........................................................................................................................................2736
Figure 21-29. QPOSCMP Register........................................................................................................................................2737
Figure 21-30. QPOSILAT Register........................................................................................................................................ 2738
Figure 21-31. QPOSSLAT Register....................................................................................................................................... 2739
Figure 21-32. QPOSLAT Register......................................................................................................................................... 2740
Figure 21-33. QUTMR Register.............................................................................................................................................2741
Figure 21-34. QUPRD Register............................................................................................................................................. 2742
Figure 21-35. QWDTMR Register......................................................................................................................................... 2743
Figure 21-36. QWDPRD Register..........................................................................................................................................2744
Figure 21-37. QDECCTL Register.........................................................................................................................................2745
Figure 21-38. QEPCTL Register............................................................................................................................................2747
Figure 21-39. QCAPCTL Register......................................................................................................................................... 2749
Figure 21-40. QPOSCTL Register.........................................................................................................................................2750
Figure 21-41. QEINT Register............................................................................................................................................... 2751
Figure 21-42. QFLG Register................................................................................................................................................ 2753
Figure 21-43. QCLR Register................................................................................................................................................ 2755
Figure 21-44. QFRC Register................................................................................................................................................2757
Figure 21-45. QEPSTS Register........................................................................................................................................... 2759
Figure 21-46. QCTMR Register.............................................................................................................................................2761
Figure 21-47. QCPRD Register............................................................................................................................................. 2762
Figure 21-48. QCTMRLAT Register.......................................................................................................................................2763
Figure 21-49. QCPRDLAT Register.......................................................................................................................................2764
Figure 21-50. REV Register...................................................................................................................................................2765
Figure 21-51. QEPSTROBESEL Register.............................................................................................................................2766
Figure 21-52. QMACTRL Register........................................................................................................................................ 2767
Figure 21-53. QEPSRCSEL Register.................................................................................................................................... 2768
Figure 22-1. SPI CPU Interface............................................................................................................................................. 2772
Figure 22-2. SPI Interrupt Flags and Enable Logic Generation.............................................................................................2775
Figure 22-3. SPI DMA Trigger Diagram.................................................................................................................................2776
Figure 22-4. SPI Controller/Peripheral Connection............................................................................................................... 2777
Figure 22-5. SPI Module Controller Configuration.................................................................................................................2779
Figure 22-6. SPI Module Peripheral Configuration................................................................................................................ 2780
Figure 22-7. SPICLK Signal Options..................................................................................................................................... 2783
Figure 22-8. SPI: SPICLK-LSPCLK Characteristic when (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1.................. 2784
Figure 22-9. SPI 3-wire Controller Mode............................................................................................................................... 2786
Figure 22-10. SPI 3-wire Peripheral Mode............................................................................................................................ 2787

42 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 22-11. Five Bits per Character.................................................................................................................................... 2790

Figure 22-12. SPI Digital Audio Receiver Configuration Using Two SPIs............................................................................. 2793
Figure 22-13. Standard Right-Justified Digital Audio Data Format........................................................................................2793
Figure 22-14. SPICCR Register............................................................................................................................................ 2800
Figure 22-15. SPICTL Register............................................................................................................................................. 2802
Figure 22-16. SPISTS Register............................................................................................................................................. 2804
Figure 22-17. SPIBRR Register.............................................................................................................................................2806
Figure 22-18. SPIRXEMU Register....................................................................................................................................... 2807
Figure 22-19. SPIRXBUF Register........................................................................................................................................ 2808
Figure 22-20. SPITXBUF Register........................................................................................................................................ 2809
Figure 22-21. SPIDAT Register............................................................................................................................................. 2810
Figure 22-22. SPIFFTX Register............................................................................................................................................2811
Figure 22-23. SPIFFRX Register...........................................................................................................................................2813
Figure 22-24. SPIFFCT Register........................................................................................................................................... 2815
Figure 22-25. SPIPRI Register.............................................................................................................................................. 2816
Figure 23-1. SCI CPU Interface.............................................................................................................................................2819
Figure 23-2. Serial Communications Interface (SCI) Module Block Diagram........................................................................2821
Figure 23-3. Typical SCI Data Frame Formats...................................................................................................................... 2823
Figure 23-4. Idle-Line Multiprocessor Communication Format..............................................................................................2825
Figure 23-5. Double-Buffered WUT and TXSHF................................................................................................................... 2826
Figure 23-6. Address-Bit Multiprocessor Communication Format......................................................................................... 2827
Figure 23-7. SCI Asynchronous Communications Format.................................................................................................... 2828
Figure 23-8. SCI RX Signals in Communication Modes........................................................................................................ 2829
Figure 23-9. SCI TX Signals in Communications Mode........................................................................................................ 2830
Figure 23-10. SCI FIFO Interrupt Flags and Enable Logic.................................................................................................... 2834
Figure 23-11. SCICCR Register.............................................................................................................................................2842
Figure 23-12. SCICTL1 Register........................................................................................................................................... 2844
Figure 23-13. SCIHBAUD Register....................................................................................................................................... 2846
Figure 23-14. SCILBAUD Register........................................................................................................................................ 2847
Figure 23-15. SCICTL2 Register........................................................................................................................................... 2848
Figure 23-16. SCIRXST Register.......................................................................................................................................... 2850
Figure 23-17. SCIRXEMU Register....................................................................................................................................... 2853
Figure 23-18. SCIRXBUF Register........................................................................................................................................2854
Figure 23-19. SCITXBUF Register........................................................................................................................................ 2856
Figure 23-20. SCIFFTX Register........................................................................................................................................... 2857
Figure 23-21. SCIFFRX Register...........................................................................................................................................2859
Figure 23-22. SCIFFCT Register...........................................................................................................................................2861
Figure 23-23. SCIPRI Register.............................................................................................................................................. 2862
Figure 24-1. USB Block Diagram...........................................................................................................................................2865
Figure 24-2. USB Scheme.....................................................................................................................................................2866
Figure 24-3. USBFADDR Register........................................................................................................................................ 2904
Figure 24-4. USBPOWER Register....................................................................................................................................... 2905
Figure 24-5. USBTXIS Register.............................................................................................................................................2906
Figure 24-6. USBRXIS Register............................................................................................................................................ 2907
Figure 24-7. USBTXIE Register.............................................................................................................................................2908
Figure 24-8. USBRXIE Register............................................................................................................................................ 2909
Figure 24-9. USBIS Register................................................................................................................................................. 2910
Figure 24-10. USBIE Register................................................................................................................................................2911
Figure 24-11. USBFRAME Register...................................................................................................................................... 2912
Figure 24-12. USBEPIDX Register........................................................................................................................................2913
Figure 24-13. USBTEST Register......................................................................................................................................... 2914
Figure 24-14. USBFIFO0 Register........................................................................................................................................ 2915
Figure 24-15. USBFIFO1 Register........................................................................................................................................ 2916
Figure 24-16. USBFIFO2 Register........................................................................................................................................ 2917
Figure 24-17. USBFIFO3 Register........................................................................................................................................ 2918
Figure 24-18. USBDEVCTL Register.................................................................................................................................... 2919
Figure 24-19. USBTXFIFOSZ Register................................................................................................................................. 2921
Figure 24-20. USBRXFIFOSZ Register.................................................................................................................................2922
Figure 24-21. USBTXFIFOADD Register.............................................................................................................................. 2923
Figure 24-22. USBRXFIFOADD Register..............................................................................................................................2932
Figure 24-23. USBCONTIM Register.................................................................................................................................... 2941

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Figure 24-24. USBFSEOF Register.......................................................................................................................................2942

Figure 24-25. USBLSEOF Register.......................................................................................................................................2943
Figure 24-26. USBTXFUNCADDR0 Register........................................................................................................................2944
Figure 24-27. USBTXHUBADDR0 Register.......................................................................................................................... 2945
Figure 24-28. USBTXHUBPORT0 Register...........................................................................................................................2946
Figure 24-29. USBTXFUNCADDR1 Register........................................................................................................................2947
Figure 24-30. USBTXHUBADDR1 Register.......................................................................................................................... 2948
Figure 24-31. USBTXHUBPORT1 Register...........................................................................................................................2949
Figure 24-32. USBRXFUNCADDR1 Register....................................................................................................................... 2950
Figure 24-33. USBRXHUBADDR1 Register..........................................................................................................................2951
Figure 24-34. USBRXHUBPORT1 Register.......................................................................................................................... 2952
Figure 24-35. USBTXFUNCADDR2 Register........................................................................................................................2953
Figure 24-36. USBTXHUBADDR2 Register.......................................................................................................................... 2954
Figure 24-37. USBTXHUBPORT2 Register...........................................................................................................................2955
Figure 24-38. USBRXFUNCADDR2 Register....................................................................................................................... 2956
Figure 24-39. USBRXHUBADDR2 Register..........................................................................................................................2957
Figure 24-40. USBRXHUBPORT2 Register.......................................................................................................................... 2958
Figure 24-41. USBTXFUNCADDR3 Register........................................................................................................................2959
Figure 24-42. USBTXHUBADDR3 Register.......................................................................................................................... 2960
Figure 24-43. USBTXHUBPORT3 Register...........................................................................................................................2961
Figure 24-44. USBRXFUNCADDR3 Register....................................................................................................................... 2962
Figure 24-45. USBRXHUBADDR3 Register..........................................................................................................................2963
Figure 24-46. USBRXHUBPORT3 Register.......................................................................................................................... 2964
Figure 24-47. USBCSRL0 Register....................................................................................................................................... 2965
Figure 24-48. USBCSRH0 Register...................................................................................................................................... 2967
Figure 24-49. USBCOUNT0 Register....................................................................................................................................2968
Figure 24-50. USBTYPE0 Register....................................................................................................................................... 2969
Figure 24-51. USBNAKLMT Register.................................................................................................................................... 2970
Figure 24-52. USBTXMAXP1 Register..................................................................................................................................2971
Figure 24-53. USBTXCSRL1 Register.................................................................................................................................. 2972
Figure 24-54. USBTXCSRH1 Register..................................................................................................................................2974
Figure 24-55. USBRXMAXP1 Register................................................................................................................................. 2976
Figure 24-56. USBRXCSRL1 Register.................................................................................................................................. 2977
Figure 24-57. USBRXCSRH1 Register................................................................................................................................. 2979
Figure 24-58. USBRXCOUNT1 Register...............................................................................................................................2981
Figure 24-59. USBTXTYPE1 Register...................................................................................................................................2982
Figure 24-60. USBTXINTERVAL1 Register...........................................................................................................................2983
Figure 24-61. USBRXTYPE1 Register.................................................................................................................................. 2984
Figure 24-62. USBRXINTERVAL1 Register.......................................................................................................................... 2985
Figure 24-63. USBTXMAXP2 Register..................................................................................................................................2986
Figure 24-64. USBTXCSRL2 Register.................................................................................................................................. 2987
Figure 24-65. USBTXCSRH2 Register..................................................................................................................................2989
Figure 24-66. USBRXMAXP2 Register................................................................................................................................. 2991
Figure 24-67. USBRXCSRL2 Register.................................................................................................................................. 2992
Figure 24-68. USBRXCSRH2 Register................................................................................................................................. 2994
Figure 24-69. USBRXCOUNT2 Register...............................................................................................................................2996
Figure 24-70. USBTXTYPE2 Register...................................................................................................................................2997
Figure 24-71. USBTXINTERVAL2 Register...........................................................................................................................2998
Figure 24-72. USBRXTYPE2 Register.................................................................................................................................. 2999
Figure 24-73. USBRXINTERVAL2 Register.......................................................................................................................... 3000
Figure 24-74. USBTXMAXP3 Register..................................................................................................................................3001
Figure 24-75. USBTXCSRL3 Register.................................................................................................................................. 3002
Figure 24-76. USBTXCSRH3 Register..................................................................................................................................3004
Figure 24-77. USBRXMAXP3 Register................................................................................................................................. 3006
Figure 24-78. USBRXCSRL3 Register.................................................................................................................................. 3007
Figure 24-79. USBRXCSRH3 Register................................................................................................................................. 3009
Figure 24-80. USBRXCOUNT3 Register............................................................................................................................... 3011
Figure 24-81. USBTXTYPE3 Register...................................................................................................................................3012
Figure 24-82. USBTXINTERVAL3 Register...........................................................................................................................3013
Figure 24-83. USBRXTYPE3 Register.................................................................................................................................. 3014
Figure 24-84. USBRXINTERVAL3 Register.......................................................................................................................... 3015

44 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 24-85. USBRQPKTCOUNT1 Register....................................................................................................................... 3016

Figure 24-86. USBRQPKTCOUNT2 Register....................................................................................................................... 3017
Figure 24-87. USBRQPKTCOUNT3 Register....................................................................................................................... 3018
Figure 24-88. USBRXDPKTBUFDIS Register.......................................................................................................................3019
Figure 24-89. USBTXDPKTBUFDIS Register....................................................................................................................... 3020
Figure 24-90. USBEPC Register........................................................................................................................................... 3021
Figure 24-91. USBEPCRIS Register..................................................................................................................................... 3023
Figure 24-92. USBEPCIM Register....................................................................................................................................... 3024
Figure 24-93. USBEPCISC Register..................................................................................................................................... 3025
Figure 24-94. USBDRRIS Register....................................................................................................................................... 3026
Figure 24-95. USBDRIM Register......................................................................................................................................... 3027
Figure 24-96. USBDRISC Register....................................................................................................................................... 3028
Figure 24-97. USBGPCS Register........................................................................................................................................ 3029
Figure 24-98. USBVDC Register........................................................................................................................................... 3030
Figure 24-99. USBVDCRIS Register..................................................................................................................................... 3031
Figure 24-100. USBVDCIM Register..................................................................................................................................... 3032
Figure 24-101. USBVDCISC Register................................................................................................................................... 3033
Figure 24-102. USBIDVRIS Register.....................................................................................................................................3034
Figure 24-103. USBIDVIM Register.......................................................................................................................................3035
Figure 24-104. USBIDVISC Register.....................................................................................................................................3036
Figure 24-105. USBDMASEL Register..................................................................................................................................3037
Figure 24-106. USB_GLB_INT_EN Register.........................................................................................................................3039
Figure 24-107. USB_GLB_INT_FLG Register.......................................................................................................................3040
Figure 24-108. USB_GLB_INT_FLG_CLR Register............................................................................................................. 3041
Figure 24-109. USBDMARIS Register...................................................................................................................................3042
Figure 24-110. USBDMAIM Register..................................................................................................................................... 3043
Figure 24-111. USBDMAISC Register................................................................................................................................... 3045
Figure 25-1. FSI Transmitter (FSITX) CPU Interface.............................................................................................................3049
Figure 25-2. FSI Receiver (FSIRX) CPU Interface with CLB.................................................................................................3050
Figure 25-3. FSI Transmitter Block Diagram......................................................................................................................... 3057
Figure 25-4. FSI Transmitter Core Block Diagram.................................................................................................................3058
Figure 25-5. FSI Receiver Block Diagram............................................................................................................................. 3063
Figure 25-6. FSI Receiver Core Block Diagram.................................................................................................................... 3064
Figure 25-7. Delay Line Control Circuit..................................................................................................................................3067
Figure 25-8. Flush Sequence Signals....................................................................................................................................3073
Figure 25-9. FSI with Internal Loopback................................................................................................................................3074
Figure 25-10. FSI Multi-Node TDM Configuration................................................................................................................. 3077
Figure 25-11. FSI Transmitter Multi-Node TDM Multiplexing.................................................................................................3077
Figure 25-12. Generated Signals for FSI Multi-Node TDM Configuration............................................................................. 3078
Figure 25-13. RX_TRIGx FSI Trigger.................................................................................................................................... 3079
Figure 25-14. FSITX as SPI Controller, Transmit Only..........................................................................................................3081
Figure 25-15. FSIRX as SPI Peripheral, Receive Only......................................................................................................... 3082
Figure 25-16. FSITX and FSIRX as SPI Controller, Full Duplex........................................................................................... 3083
Figure 25-17. Point to Point Connection................................................................................................................................3084
Figure 25-18. TX_MAIN_CTRL Register............................................................................................................................... 3100
Figure 25-19. TX_CLK_CTRL Register................................................................................................................................. 3101
Figure 25-20. TX_OPER_CTRL_LO Register....................................................................................................................... 3102
Figure 25-21. TX_OPER_CTRL_HI Register........................................................................................................................ 3104
Figure 25-22. TX_FRAME_CTRL Register........................................................................................................................... 3105
Figure 25-23. TX_FRAME_TAG_UDATA Register................................................................................................................ 3106
Figure 25-24. TX_BUF_PTR_LOAD Register....................................................................................................................... 3107
Figure 25-25. TX_BUF_PTR_STS Register.......................................................................................................................... 3108
Figure 25-26. TX_PING_CTRL Register............................................................................................................................... 3109
Figure 25-27. TX_PING_TAG Register..................................................................................................................................3110
Figure 25-28. TX_PING_TO_REF Register........................................................................................................................... 3111
Figure 25-29. TX_PING_TO_CNT Register...........................................................................................................................3112
Figure 25-30. TX_INT_CTRL Register...................................................................................................................................3113
Figure 25-31. TX_DMA_CTRL Register................................................................................................................................ 3115
Figure 25-32. TX_LOCK_CTRL Register...............................................................................................................................3116
Figure 25-33. TX_EVT_STS Register....................................................................................................................................3117
Figure 25-34. TX_EVT_CLR Register....................................................................................................................................3118

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Figure 25-35. TX_EVT_FRC Register................................................................................................................................... 3119

Figure 25-36. TX_USER_CRC Register................................................................................................................................3120
Figure 25-37. TX_ECC_DATA Register.................................................................................................................................3121
Figure 25-38. TX_ECC_VAL Register................................................................................................................................... 3122
Figure 25-39. TX_DLYLINE_CTRL Register......................................................................................................................... 3123
Figure 25-40. TX_BUF_BASE_y Register.............................................................................................................................3124
Figure 25-41. RX_MAIN_CTRL Register...............................................................................................................................3127
Figure 25-42. RX_OPER_CTRL Register............................................................................................................................. 3129
Figure 25-43. RX_FRAME_INFO Register............................................................................................................................3131
Figure 25-44. RX_FRAME_TAG_UDATA Register................................................................................................................3132
Figure 25-45. RX_DMA_CTRL Register................................................................................................................................3133
Figure 25-46. RX_EVT_STS Register................................................................................................................................... 3134
Figure 25-47. RX_CRC_INFO Register.................................................................................................................................3137
Figure 25-48. RX_EVT_CLR Register...................................................................................................................................3138
Figure 25-49. RX_EVT_FRC Register...................................................................................................................................3140
Figure 25-50. RX_BUF_PTR_LOAD Register.......................................................................................................................3143
Figure 25-51. RX_BUF_PTR_STS Register..........................................................................................................................3144
Figure 25-52. RX_FRAME_WD_CTRL Register................................................................................................................... 3145
Figure 25-53. RX_FRAME_WD_REF Register..................................................................................................................... 3146
Figure 25-54. RX_FRAME_WD_CNT Register..................................................................................................................... 3147
Figure 25-55. RX_PING_WD_CTRL Register.......................................................................................................................3148
Figure 25-56. RX_PING_TAG Register................................................................................................................................. 3149
Figure 25-57. RX_PING_WD_REF Register......................................................................................................................... 3150
Figure 25-58. RX_PING_WD_CNT Register.........................................................................................................................3151
Figure 25-59. RX_INT1_CTRL Register................................................................................................................................3152
Figure 25-60. RX_INT2_CTRL Register................................................................................................................................3155
Figure 25-61. RX_LOCK_CTRL Register..............................................................................................................................3158
Figure 25-62. RX_ECC_DATA Register................................................................................................................................ 3159
Figure 25-63. RX_ECC_VAL Register................................................................................................................................... 3160
Figure 25-64. RX_ECC_SEC_DATA Register....................................................................................................................... 3161
Figure 25-65. RX_ECC_LOG Register..................................................................................................................................3162
Figure 25-66. RX_FRAME_TAG_CMP Register................................................................................................................... 3163
Figure 25-67. RX_PING_TAG_CMP Register....................................................................................................................... 3164
Figure 25-68. RX_TRIG_CTRL_0 Register........................................................................................................................... 3165
Figure 25-69. RX_TRIG_WIDTH_0 Register.........................................................................................................................3166
Figure 25-70. RX_DLYLINE_CTRL Register......................................................................................................................... 3167
Figure 25-71. RX_TRIG_CTRL_1 Register........................................................................................................................... 3168
Figure 25-72. RX_TRIG_CTRL_2 Register........................................................................................................................... 3169
Figure 25-73. RX_TRIG_CTRL_3 Register........................................................................................................................... 3170
Figure 25-74. RX_VIS_1 Register......................................................................................................................................... 3171
Figure 25-75. RX_UDATA_FILTER Register......................................................................................................................... 3172
Figure 25-76. RX_BUF_BASE_y Register............................................................................................................................ 3173
Figure 26-1. Multiple I2C Modules Connected...................................................................................................................... 3175
Figure 26-2. I2C Module Conceptual Block Diagram............................................................................................................ 3178
Figure 26-3. Clocking Diagram for the I2C Module............................................................................................................... 3178
Figure 26-4. Roles of the Clock Divide-Down Values (ICCL and ICCH)................................................................................3179
Figure 26-5. Bit Transfer on the I2C bus................................................................................................................................3180
Figure 26-6. I2C Target TX / RX Flowchart............................................................................................................................3183
Figure 26-7. I2C Controller TX / RX Flowchart...................................................................................................................... 3184
Figure 26-8. I2C Module START and STOP Conditions........................................................................................................3185
Figure 26-9. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)......................................... 3186
Figure 26-10. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR).............................................................. 3187
Figure 26-11. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR).............................................................3187
Figure 26-12. I2C Module Free Data Format (FDF = 1 in I2CMDR)......................................................................................3188
Figure 26-13. Repeated START Condition (in This Case, 7-Bit Addressing Format)............................................................ 3188
Figure 26-14. Synchronization of Two I2C Clock Generators During Arbitration...................................................................3189
Figure 26-15. Automatic Clock Stretching............................................................................................................................. 3190
Figure 26-16. Extended Automatic Clock Stretching............................................................................................................. 3191
Figure 26-17. Arbitration Procedure Between Two Controller-Transmitters.......................................................................... 3192
Figure 26-18. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit.....................................................3193
Figure 26-19. Enable Paths of the I2C Interrupt Requests....................................................................................................3196

46 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 26-20. I2C FIFO Interrupt........................................................................................................................................... 3197

Figure 26-21. I2COAR Register.............................................................................................................................................3204
Figure 26-22. I2CIER Register.............................................................................................................................................. 3205
Figure 26-23. I2CSTR Register............................................................................................................................................. 3206
Figure 26-24. I2CCLKL Register........................................................................................................................................... 3210
Figure 26-25. I2CCLKH Register........................................................................................................................................... 3211
Figure 26-26. I2CCNT Register............................................................................................................................................. 3212
Figure 26-27. I2CDRR Register.............................................................................................................................................3213
Figure 26-28. I2CTAR Register..............................................................................................................................................3214
Figure 26-29. I2CDXR Register.............................................................................................................................................3215
Figure 26-30. I2CMDR Register............................................................................................................................................ 3216
Figure 26-31. I2CISRC Register............................................................................................................................................3220
Figure 26-32. I2CEMDR Register..........................................................................................................................................3221
Figure 26-33. I2CPSC Register............................................................................................................................................. 3223
Figure 26-34. I2CFFTX Register........................................................................................................................................... 3224
Figure 26-35. I2CFFRX Register........................................................................................................................................... 3226
Figure 27-1. PMBus Module Block Diagram..........................................................................................................................3229
Figure 27-2. Quick Command Message................................................................................................................................ 3231
Figure 27-3. Send Byte Message With and Without PEC..................................................................................................... 3232
Figure 27-4. Receive Byte Message With and Without PEC.................................................................................................3232
Figure 27-5. Write Byte and Write Word Messages With and Without PEC..........................................................................3233
Figure 27-6. Read Byte and Read Word Messages With and Without PEC......................................................................... 3234
Figure 27-7. Process Call Message With and Without PEC..................................................................................................3235
Figure 27-8. Block Write Message With and Without PEC.................................................................................................... 3235
Figure 27-9. Block Read Message With and Without PEC....................................................................................................3236
Figure 27-10. Block Write-Block Read Process Call Message With and Without PEC......................................................... 3237
Figure 27-11. Alert Response Message.................................................................................................................................3237
Figure 27-12. Extended Command Write Byte and Write Word Messages With and Without PEC...................................... 3238
Figure 27-13. Extended Command Read Byte and Read Word Messages With and Without PEC......................................3239
Figure 27-14. Group Command Message With and Without PEC........................................................................................ 3240
Figure 27-15. Quick Command Message.............................................................................................................................. 3241
Figure 27-16. Send Byte Message With and Without PEC................................................................................................... 3242
Figure 27-17. Receive Byte Message With and Without PEC...............................................................................................3242
Figure 27-18. Write Byte and Write Word Messages With and Without PEC........................................................................3243
Figure 27-19. Read Byte and Read Word Messages With and Without PEC....................................................................... 3244
Figure 27-20. Process Call Message With and Without PEC................................................................................................3245
Figure 27-21. Block Write Message With and Without PEC.................................................................................................. 3246
Figure 27-22. Block Read Message With and Without PEC..................................................................................................3247
Figure 27-23. Block Write-Block Read Process Call Message With and Without PEC......................................................... 3248
Figure 27-24. Alert Response Message................................................................................................................................ 3248
Figure 27-25. Extended Command Write Byte and Write Word Messages With and Without PEC...................................... 3249
Figure 27-26. Extended Command Read Byte and Read Word Messages With and Without PEC......................................3250
Figure 27-27. Group Command Message With and Without PEC........................................................................................ 3251
Figure 27-28. PMBCCR Register.......................................................................................................................................... 3255
Figure 27-29. PMBTXBUF Register...................................................................................................................................... 3257
Figure 27-30. PMBRXBUF Register...................................................................................................................................... 3258
Figure 27-31. PMBACK Register...........................................................................................................................................3259
Figure 27-32. PMBSTS Register........................................................................................................................................... 3260
Figure 27-33. PMBINTM Register......................................................................................................................................... 3262
Figure 27-34. PMBTCR Register...........................................................................................................................................3264
Figure 27-35. PMBHTA Register........................................................................................................................................... 3266
Figure 27-36. PMBCTRL Register.........................................................................................................................................3267
Figure 27-37. PMBTIMCTL Register..................................................................................................................................... 3269
Figure 27-38. PMBTIMCLK Register..................................................................................................................................... 3270
Figure 27-39. PMBTIMSTSETUP Register........................................................................................................................... 3271
Figure 27-40. PMBTIMBIDLE Register..................................................................................................................................3272
Figure 27-41. PMBTIMLOWTIMOUT Register...................................................................................................................... 3273
Figure 27-42. PMBTIMHIGHTIMOUT Register..................................................................................................................... 3274
Figure 28-1. MCAN Module Overview................................................................................................................................... 3276
Figure 28-2. MCAN Typical Bus Wiring................................................................................................................................. 3277
Figure 28-3. MCAN Integration..............................................................................................................................................3279

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Figure 28-4. MCAN Block Diagram....................................................................................................................................... 3281

Figure 28-5. CAN FD Frame..................................................................................................................................................3284
Figure 28-6. CAN Bit Timing.................................................................................................................................................. 3286
Figure 28-7. Transmitter Delay Measurement....................................................................................................................... 3287
Figure 28-8. Connection of Signals in Bus Monitoring Mode.................................................................................................3288
Figure 28-9. Auto Wakeup Enabled Exit from Power Down.................................................................................................. 3291
Figure 28-10. External Loop Back Mode............................................................................................................................... 3292
Figure 28-11. Internal Loop Back Mode.................................................................................................................................3293
Figure 28-12. External Timestamp Counter Interrupt............................................................................................................ 3294
Figure 28-13. Standard Message ID Filter Path.................................................................................................................... 3299
Figure 28-14. Extended Message ID Filter Path....................................................................................................................3300
Figure 28-15. Rx FIFO Status................................................................................................................................................3301
Figure 28-16. Rx FIFO Overflow Handling............................................................................................................................ 3302
Figure 28-17. Mixed Dedicated Tx Buffers /Tx FIFO (example)............................................................................................ 3306
Figure 28-18. Mixed Dedicated Tx Buffers /Tx Queue (example)..........................................................................................3306
Figure 28-19. Message RAM Configuration.......................................................................................................................... 3308
Figure 28-20. Rx Buffer/Rx FIFO Element Structure............................................................................................................. 3309
Figure 28-21. Tx Buffer Element Structure............................................................................................................................ 3311
Figure 28-22. Tx Event FIFO Element Structure................................................................................................................... 3313
Figure 28-23. Standard Message ID Filter Element Structure...............................................................................................3314
Figure 28-24. Extended Message ID Filter Element Structure.............................................................................................. 3316
Figure 28-25. MCANSS_PID Register...................................................................................................................................3327
Figure 28-26. MCANSS_CTRL Register............................................................................................................................... 3328
Figure 28-27. MCANSS_STAT Register................................................................................................................................ 3329
Figure 28-28. MCANSS_ICS Register...................................................................................................................................3330
Figure 28-29. MCANSS_IRS Register...................................................................................................................................3331
Figure 28-30. MCANSS_IECS Register................................................................................................................................ 3332
Figure 28-31. MCANSS_IE Register..................................................................................................................................... 3333
Figure 28-32. MCANSS_IES Register...................................................................................................................................3334
Figure 28-33. MCANSS_EOI Register.................................................................................................................................. 3335
Figure 28-34. MCANSS_EXT_TS_PRESCALER Register................................................................................................... 3336
Figure 28-35. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register........................................................................... 3337
Figure 28-36. MCAN_CREL Register....................................................................................................................................3340
Figure 28-37. MCAN_ENDN Register................................................................................................................................... 3341
Figure 28-38. MCAN_DBTP Register....................................................................................................................................3342
Figure 28-39. MCAN_TEST Register.................................................................................................................................... 3344
Figure 28-40. MCAN_RWD Register..................................................................................................................................... 3345
Figure 28-41. MCAN_CCCR Register................................................................................................................................... 3346
Figure 28-42. MCAN_NBTP Register....................................................................................................................................3349
Figure 28-43. MCAN_TSCC Register....................................................................................................................................3351
Figure 28-44. MCAN_TSCV Register....................................................................................................................................3352
Figure 28-45. MCAN_TOCC Register................................................................................................................................... 3353
Figure 28-46. MCAN_TOCV Register....................................................................................................................................3354
Figure 28-47. MCAN_ECR Register......................................................................................................................................3355
Figure 28-48. MCAN_PSR Register...................................................................................................................................... 3356
Figure 28-49. MCAN_TDCR Register................................................................................................................................... 3359
Figure 28-50. MCAN_IR Register..........................................................................................................................................3360
Figure 28-51. MCAN_IE Register.......................................................................................................................................... 3364
Figure 28-52. MCAN_ILS Register........................................................................................................................................ 3366
Figure 28-53. MCAN_ILE Register........................................................................................................................................ 3369
Figure 28-54. MCAN_GFC Register......................................................................................................................................3370
Figure 28-55. MCAN_SIDFC Register...................................................................................................................................3371
Figure 28-56. MCAN_XIDFC Register...................................................................................................................................3372
Figure 28-57. MCAN_XIDAM Register.................................................................................................................................. 3373
Figure 28-58. MCAN_HPMS Register................................................................................................................................... 3374
Figure 28-59. MCAN_NDAT1 Register.................................................................................................................................. 3375
Figure 28-60. MCAN_NDAT2 Register.................................................................................................................................. 3378
Figure 28-61. MCAN_RXF0C Register..................................................................................................................................3381
Figure 28-62. MCAN_RXF0S Register..................................................................................................................................3382
Figure 28-63. MCAN_RXF0A Register..................................................................................................................................3383
Figure 28-64. MCAN_RXBC Register................................................................................................................................... 3384

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Figure 28-65. MCAN_RXF1C Register..................................................................................................................................3385

Figure 28-66. MCAN_RXF1S Register..................................................................................................................................3386
Figure 28-67. MCAN_RXF1A Register..................................................................................................................................3387
Figure 28-68. MCAN_RXESC Register................................................................................................................................. 3388
Figure 28-69. MCAN_TXBC Register....................................................................................................................................3390
Figure 28-70. MCAN_TXFQS Register................................................................................................................................. 3392
Figure 28-71. MCAN_TXESC Register................................................................................................................................. 3393
Figure 28-72. MCAN_TXBRP Register................................................................................................................................. 3394
Figure 28-73. MCAN_TXBAR Register................................................................................................................................. 3397
Figure 28-74. MCAN_TXBCR Register................................................................................................................................. 3399
Figure 28-75. MCAN_TXBTO Register..................................................................................................................................3401
Figure 28-76. MCAN_TXBCF Register..................................................................................................................................3403
Figure 28-77. MCAN_TXBTIE Register.................................................................................................................................3405
Figure 28-78. MCAN_TXBCIE Register................................................................................................................................ 3409
Figure 28-79. MCAN_TXEFC Register..................................................................................................................................3413
Figure 28-80. MCAN_TXEFS Register..................................................................................................................................3414
Figure 28-81. MCAN_TXEFA Register.................................................................................................................................. 3415
Figure 28-82. MCANERR_REV Register.............................................................................................................................. 3418
Figure 28-83. MCANERR_VECTOR Register....................................................................................................................... 3419
Figure 28-84. MCANERR_STAT Register............................................................................................................................. 3420
Figure 28-85. MCANERR_WRAP_REV Register..................................................................................................................3421
Figure 28-86. MCANERR_CTRL Register............................................................................................................................ 3422
Figure 28-87. MCANERR_ERR_CTRL1 Register.................................................................................................................3424
Figure 28-88. MCANERR_ERR_CTRL2 Register.................................................................................................................3425
Figure 28-89. MCANERR_ERR_STAT1 Register..................................................................................................................3426
Figure 28-90. MCANERR_ERR_STAT2 Register..................................................................................................................3428
Figure 28-91. MCANERR_ERR_STAT3 Register..................................................................................................................3429
Figure 28-92. MCANERR_SEC_EOI Register...................................................................................................................... 3430
Figure 28-93. MCANERR_SEC_STATUS Register...............................................................................................................3431
Figure 28-94. MCANERR_SEC_ENABLE_SET Register..................................................................................................... 3432
Figure 28-95. MCANERR_SEC_ENABLE_CLR Register..................................................................................................... 3433
Figure 28-96. MCANERR_DED_EOI Register...................................................................................................................... 3434
Figure 28-97. MCANERR_DED_STATUS Register...............................................................................................................3435
Figure 28-98. MCANERR_DED_ENABLE_SET Register..................................................................................................... 3436
Figure 28-99. MCANERR_DED_ENABLE_CLR Register.....................................................................................................3437
Figure 28-100. MCANERR_AGGR_ENABLE_SET Register................................................................................................ 3438
Figure 28-101. MCANERR_AGGR_ENABLE_CLR Register................................................................................................3439
Figure 28-102. MCANERR_AGGR_STATUS_SET Register.................................................................................................3440
Figure 28-103. MCANERR_AGGR_STATUS_CLR Register................................................................................................ 3441
Figure 29-1. SCI Block Diagram............................................................................................................................................ 3446
Figure 29-2. SCI/LIN Block Diagram..................................................................................................................................... 3447
Figure 29-3. Typical SCI Data Frame Formats...................................................................................................................... 3448
Figure 29-4. Asynchronous Communication Bit Timing.........................................................................................................3449
Figure 29-5. Superfractional Divider Example....................................................................................................................... 3452
Figure 29-6. Idle-Line Multiprocessor Communication Format..............................................................................................3454
Figure 29-7. Address-Bit Multiprocessor Communication Format......................................................................................... 3455
Figure 29-8. Receive Buffers................................................................................................................................................. 3456
Figure 29-9. Transmit Buffers................................................................................................................................................ 3457
Figure 29-10. General Interrupt Scheme............................................................................................................................... 3458
Figure 29-11. Interrupt Generation for Given Flags............................................................................................................... 3459
Figure 29-12. LIN Protocol Message Frame Format: Commander Header and Responder Peripheral Response.............. 3467
Figure 29-13. Header 3 Fields: Synch Break, Synch, and ID................................................................................................ 3467
Figure 29-14. Response Format of LIN Message Frame...................................................................................................... 3468
Figure 29-15. Message Header in Terms of Tbit ................................................................................................................... 3471
Figure 29-16. ID Field............................................................................................................................................................ 3472
Figure 29-17. Measurements for Synchronization.................................................................................................................3474
Figure 29-18. Synchronization Validation Process and Baud Rate Adjustment.................................................................... 3475
Figure 29-19. Optional Embedded Checksum in Response for Extended Frames............................................................... 3476
Figure 29-20. Checksum Compare and Send for Extended Frames.....................................................................................3477
Figure 29-21. TXRX Error Detector....................................................................................................................................... 3479
Figure 29-22. Classic Checksum Generation at Transmitting Node......................................................................................3480

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Figure 29-23. LIN 2.0-Compliant Checksum Generation at Transmitting Node.................................................................... 3480

Figure 29-24. ID Reception, Filtering, and Validation............................................................................................................ 3481
Figure 29-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence................................................................ 3485
Figure 29-26. Wakeup Signal Generation..............................................................................................................................3489
Figure 29-27. SCIGCR0 Register.......................................................................................................................................... 3499
Figure 29-28. SCIGCR1 Register.......................................................................................................................................... 3500
Figure 29-29. SCIGCR2 Register.......................................................................................................................................... 3505
Figure 29-30. SCISETINT Register....................................................................................................................................... 3507
Figure 29-31. SCICLEARINT Register...................................................................................................................................3511
Figure 29-32. SCISETINTLVL Register................................................................................................................................. 3514
Figure 29-33. SCICLEARINTLVL Register............................................................................................................................ 3517
Figure 29-34. SCIFLR Register............................................................................................................................................. 3520
Figure 29-35. SCIINTVECT0 Register...................................................................................................................................3528
Figure 29-36. SCIINTVECT1 Register...................................................................................................................................3529
Figure 29-37. SCIFORMAT Register..................................................................................................................................... 3530
Figure 29-38. BRSR Register................................................................................................................................................ 3531
Figure 29-39. SCIED Register............................................................................................................................................... 3533
Figure 29-40. SCIRD Register...............................................................................................................................................3534
Figure 29-41. SCITD Register............................................................................................................................................... 3535
Figure 29-42. SCIPIO0 Register............................................................................................................................................3536
Figure 29-43. SCIPIO2 Register............................................................................................................................................3537
Figure 29-44. LINCOMP Register..........................................................................................................................................3538
Figure 29-45. LINRD0 Register............................................................................................................................................. 3539
Figure 29-46. LINRD1 Register............................................................................................................................................. 3540
Figure 29-47. LINMASK Register.......................................................................................................................................... 3541
Figure 29-48. LINID Register.................................................................................................................................................3542
Figure 29-49. LINTD0 Register..............................................................................................................................................3543
Figure 29-50. LINTD1 Register..............................................................................................................................................3544
Figure 29-51. MBRSR Register............................................................................................................................................. 3545
Figure 29-52. IODFTCTRL Register......................................................................................................................................3546
Figure 29-53. LIN_GLB_INT_EN Register............................................................................................................................ 3549
Figure 29-54. LIN_GLB_INT_FLG Register.......................................................................................................................... 3550
Figure 29-55. LIN_GLB_INT_CLR Register.......................................................................................................................... 3551
Figure 30-1. Block Diagram of the CLB Subsystem in the Device........................................................................................ 3554
Figure 30-2. Block Diagram of a CLB Tile and CPU Interface...............................................................................................3554
Figure 30-3. CLB Clocking.....................................................................................................................................................3555
Figure 30-4. CLB Clock Prescalar......................................................................................................................................... 3556
Figure 30-5. GPIO to CLB Tile Connections..........................................................................................................................3557
Figure 30-6. CLB Input Mux and Filter...................................................................................................................................3558
Figure 30-7. CLB Input Synchronization Example.................................................................................................................3558
Figure 30-8. CLB Input Pipelining Example...........................................................................................................................3559
Figure 30-9. CLB Outputs......................................................................................................................................................3566
Figure 30-10. CLB Output Signal Multiplexer........................................................................................................................ 3567
Figure 30-11. CLB Tile Submodules...................................................................................................................................... 3570
Figure 30-12. Counter Block..................................................................................................................................................3573
Figure 30-13. LFSR Modes................................................................................................................................................... 3576
Figure 30-14. FSM Block....................................................................................................................................................... 3577
Figure 30-15. FSM LUT Block............................................................................................................................................... 3578
Figure 30-16. LUT4 Block......................................................................................................................................................3579
Figure 30-17. Output LUT Block............................................................................................................................................ 3579
Figure 30-18. AOC Block.......................................................................................................................................................3581
Figure 30-19. AOC Block and The CLB TILE........................................................................................................................ 3582
Figure 30-20. High Level Controller Block............................................................................................................................. 3583
Figure 30-21. CLB Control of SPI RX Buffer..........................................................................................................................3590
Figure 30-22. CLB_COUNT_RESET Register...................................................................................................................... 3603
Figure 30-23. CLB_COUNT_MODE_1 Register................................................................................................................... 3604
Figure 30-24. CLB_COUNT_MODE_0 Register................................................................................................................... 3605
Figure 30-25. CLB_COUNT_EVENT Register...................................................................................................................... 3606
Figure 30-26. CLB_FSM_EXTRA_IN0 Register....................................................................................................................3607
Figure 30-27. CLB_FSM_EXTERNAL_IN0 Register.............................................................................................................3608
Figure 30-28. CLB_FSM_EXTERNAL_IN1 Register.............................................................................................................3609

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Figure 30-29. CLB_FSM_EXTRA_IN1 Register....................................................................................................................3610

Figure 30-30. CLB_LUT4_IN0 Register................................................................................................................................. 3611
Figure 30-31. CLB_LUT4_IN1 Register.................................................................................................................................3612
Figure 30-32. CLB_LUT4_IN2 Register.................................................................................................................................3613
Figure 30-33. CLB_LUT4_IN3 Register.................................................................................................................................3614
Figure 30-34. CLB_FSM_LUT_FN1_0 Register....................................................................................................................3615
Figure 30-35. CLB_FSM_LUT_FN2 Register........................................................................................................................3616
Figure 30-36. CLB_LUT4_FN1_0 Register........................................................................................................................... 3617
Figure 30-37. CLB_LUT4_FN2 Register............................................................................................................................... 3618
Figure 30-38. CLB_FSM_NEXT_STATE_0 Register.............................................................................................................3619
Figure 30-39. CLB_FSM_NEXT_STATE_1 Register.............................................................................................................3620
Figure 30-40. CLB_FSM_NEXT_STATE_2 Register.............................................................................................................3621
Figure 30-41. CLB_MISC_CONTROL Register.................................................................................................................... 3622
Figure 30-42. CLB_OUTPUT_LUT_0 Register..................................................................................................................... 3625
Figure 30-43. CLB_OUTPUT_LUT_1 Register..................................................................................................................... 3626
Figure 30-44. CLB_OUTPUT_LUT_2 Register..................................................................................................................... 3627
Figure 30-45. CLB_OUTPUT_LUT_3 Register..................................................................................................................... 3628
Figure 30-46. CLB_OUTPUT_LUT_4 Register..................................................................................................................... 3629
Figure 30-47. CLB_OUTPUT_LUT_5 Register..................................................................................................................... 3630
Figure 30-48. CLB_OUTPUT_LUT_6 Register..................................................................................................................... 3631
Figure 30-49. CLB_OUTPUT_LUT_7 Register..................................................................................................................... 3632
Figure 30-50. CLB_HLC_EVENT_SEL Register................................................................................................................... 3633
Figure 30-51. CLB_COUNT_MATCH_TAP_SEL Register.................................................................................................... 3634
Figure 30-52. CLB_OUTPUT_COND_CTRL_0 Register...................................................................................................... 3635
Figure 30-53. CLB_OUTPUT_COND_CTRL_1 Register...................................................................................................... 3637
Figure 30-54. CLB_OUTPUT_COND_CTRL_2 Register...................................................................................................... 3639
Figure 30-55. CLB_OUTPUT_COND_CTRL_3 Register...................................................................................................... 3641
Figure 30-56. CLB_OUTPUT_COND_CTRL_4 Register...................................................................................................... 3643
Figure 30-57. CLB_OUTPUT_COND_CTRL_5 Register...................................................................................................... 3645
Figure 30-58. CLB_OUTPUT_COND_CTRL_6 Register...................................................................................................... 3647
Figure 30-59. CLB_OUTPUT_COND_CTRL_7 Register...................................................................................................... 3649
Figure 30-60. CLB_MISC_ACCESS_CTRL Register............................................................................................................3651
Figure 30-61. CLB_SPI_DATA_CTRL_HI Register............................................................................................................... 3652
Figure 30-62. CLB_LOAD_EN Register................................................................................................................................ 3655
Figure 30-63. CLB_LOAD_ADDR Register........................................................................................................................... 3656
Figure 30-64. CLB_LOAD_DATA Register............................................................................................................................ 3657
Figure 30-65. CLB_INPUT_FILTER Register........................................................................................................................ 3658
Figure 30-66. CLB_IN_MUX_SEL_0 Register.......................................................................................................................3661
Figure 30-67. CLB_LCL_MUX_SEL_1 Register....................................................................................................................3663
Figure 30-68. CLB_LCL_MUX_SEL_2 Register....................................................................................................................3664
Figure 30-69. CLB_BUF_PTR Register.................................................................................................................................3665
Figure 30-70. CLB_GP_REG Register.................................................................................................................................. 3666
Figure 30-71. CLB_OUT_EN Register.................................................................................................................................. 3668
Figure 30-72. CLB_GLBL_MUX_SEL_1 Register................................................................................................................. 3669
Figure 30-73. CLB_GLBL_MUX_SEL_2 Register................................................................................................................. 3670
Figure 30-74. CLB_PRESCALE_CTRL Register.................................................................................................................. 3671
Figure 30-75. CLB_INTR_TAG_REG Register......................................................................................................................3672
Figure 30-76. CLB_LOCK Register....................................................................................................................................... 3673
Figure 30-77. CLB_HLC_INSTR_READ_PTR Register........................................................................................................3674
Figure 30-78. CLB_HLC_INSTR_VALUE Register................................................................................................................3675
Figure 30-79. CLB_DBG_OUT_2 Register............................................................................................................................3676
Figure 30-80. CLB_DBG_R0 Register...................................................................................................................................3677
Figure 30-81. CLB_DBG_R1 Register...................................................................................................................................3678
Figure 30-82. CLB_DBG_R2 Register...................................................................................................................................3679
Figure 30-83. CLB_DBG_R3 Register...................................................................................................................................3680
Figure 30-84. CLB_DBG_C0 Register...................................................................................................................................3681
Figure 30-85. CLB_DBG_C1 Register...................................................................................................................................3682
Figure 30-86. CLB_DBG_C2 Register...................................................................................................................................3683
Figure 30-87. CLB_DBG_OUT Register................................................................................................................................3684
Figure 30-88. CLB_PUSH Register....................................................................................................................................... 3687
Figure 30-89. CLB_PULL Register........................................................................................................................................ 3688

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 51

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Figure 31-1. AES Block Diagram...........................................................................................................................................3690

Figure 31-2. AES - GCM Operation.......................................................................................................................................3694
Figure 31-3. AES - CCM Operation....................................................................................................................................... 3695
Figure 31-4. AES - XTS Operation........................................................................................................................................ 3696
Figure 31-5. AES - ECB Feedback Mode..............................................................................................................................3697
Figure 31-6. AES - CBC Feedback Mode..............................................................................................................................3698
Figure 31-7. AES Encryption With CTR/ICM Mode............................................................................................................... 3699
Figure 31-8. AES - CFB Feedback Mode.............................................................................................................................. 3700
Figure 31-9. AES - F8 Mode..................................................................................................................................................3701
Figure 31-10. AES - F9 Operation......................................................................................................................................... 3702
Figure 31-11. AES - CBC-MAC Authentication Mode............................................................................................................3703
Figure 31-12. AES Polling Mode........................................................................................................................................... 3707
Figure 31-13. AES Interrupt Service......................................................................................................................................3709
Figure 31-14. AES_KEY2_6 Register....................................................................................................................................3717
Figure 31-15. AES_KEY2_7 Register....................................................................................................................................3718
Figure 31-16. AES_KEY2_4 Register....................................................................................................................................3719
Figure 31-17. AES_KEY2_5 Register....................................................................................................................................3720
Figure 31-18. AES_KEY2_2 Register....................................................................................................................................3721
Figure 31-19. AES_KEY2_3 Register....................................................................................................................................3722
Figure 31-20. AES_KEY2_0 Register....................................................................................................................................3723
Figure 31-21. AES_KEY2_1 Register....................................................................................................................................3724
Figure 31-22. AES_KEY1_6 Register....................................................................................................................................3725
Figure 31-23. AES_KEY1_7 Register....................................................................................................................................3726
Figure 31-24. AES_KEY1_4 Register....................................................................................................................................3727
Figure 31-25. AES_KEY1_5 Register....................................................................................................................................3728
Figure 31-26. AES_KEY1_2 Register....................................................................................................................................3729
Figure 31-27. AES_KEY1_3 Register....................................................................................................................................3730
Figure 31-28. AES_KEY1_0 Register....................................................................................................................................3731
Figure 31-29. AES_KEY1_1 Register....................................................................................................................................3732
Figure 31-30. AES_IV_IN_OUT_0 Register.......................................................................................................................... 3733
Figure 31-31. AES_IV_IN_OUT_1 Register.......................................................................................................................... 3734
Figure 31-32. AES_IV_IN_OUT_2 Register.......................................................................................................................... 3735
Figure 31-33. AES_IV_IN_OUT_3 Register.......................................................................................................................... 3736
Figure 31-34. AES_CTRL Register....................................................................................................................................... 3737
Figure 31-35. AES_C_LENGTH_0 Register..........................................................................................................................3741
Figure 31-36. AES_C_LENGTH_1 Register..........................................................................................................................3742
Figure 31-37. AES_AUTH_LENGTH Register...................................................................................................................... 3743
Figure 31-38. AES_DATA_IN_OUT_0 Register.....................................................................................................................3744
Figure 31-39. AES_DATA_IN_OUT_1 Register.....................................................................................................................3745
Figure 31-40. AES_DATA_IN_OUT_2 Register.....................................................................................................................3746
Figure 31-41. AES_DATA_IN_OUT_3 Register.....................................................................................................................3747
Figure 31-42. AES_TAG_OUT_0 Register............................................................................................................................ 3748
Figure 31-43. AES_TAG_OUT_1 Register............................................................................................................................ 3749
Figure 31-44. AES_TAG_OUT_2 Register............................................................................................................................ 3750
Figure 31-45. AES_TAG_OUT_3 Register............................................................................................................................ 3751
Figure 31-46. AES_REV Register......................................................................................................................................... 3752
Figure 31-47. AES_SYSCONFIG Register............................................................................................................................3753
Figure 31-48. AES_SYSSTATUS Register............................................................................................................................ 3755
Figure 31-49. AES_IRQSTATUS Register.............................................................................................................................3756
Figure 31-50. AES_IRQENABLE Register............................................................................................................................ 3757
Figure 31-51. AES_DIRTY_BITS Register............................................................................................................................ 3758
Figure 31-52. AES_GLB_INT_FLG Register.........................................................................................................................3760
Figure 31-53. AES_GLB_INT_CLR Register.........................................................................................................................3761
Figure 32-1. EPG Overview Block Diagram.......................................................................................................................... 3763
Figure 32-2. EPG Detailed Block Diagram............................................................................................................................ 3764
Figure 32-3. EPG Clock Generator........................................................................................................................................3765
Figure 32-4. EPG Clock Stop................................................................................................................................................ 3766
Figure 32-5. EPG Signal Generator Detailed Overview........................................................................................................ 3768
Figure 32-6. EPG Peripheral Signal Muxing..........................................................................................................................3771
Figure 32-7. EPG Interrupt.................................................................................................................................................... 3776
Figure 32-8. GCTL0 Register................................................................................................................................................ 3782

52 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 32-9. GCTL1 Register................................................................................................................................................ 3784

Figure 32-10. GCTL2 Register.............................................................................................................................................. 3785
Figure 32-11. GCTL3 Register...............................................................................................................................................3787
Figure 32-12. EPGLOCK Register.........................................................................................................................................3791
Figure 32-13. EPGCOMMIT Register....................................................................................................................................3792
Figure 32-14. GINTSTS Register.......................................................................................................................................... 3793
Figure 32-15. GINTEN Register............................................................................................................................................ 3794
Figure 32-16. GINTCLR Register.......................................................................................................................................... 3795
Figure 32-17. GINTFRC Register.......................................................................................................................................... 3796
Figure 32-18. CLKDIV0_CTL0 Register................................................................................................................................ 3797
Figure 32-19. CLKDIV0_CLKOFFSET Register....................................................................................................................3798
Figure 32-20. CLKDIV1_CTL0 Register................................................................................................................................ 3799
Figure 32-21. CLKDIV1_CLKOFFSET Register....................................................................................................................3800
Figure 32-22. SIGGEN0_CTL0 Register............................................................................................................................... 3801
Figure 32-23. SIGGEN0_CTL1 Register............................................................................................................................... 3803
Figure 32-24. SIGGEN0_DATA0 Register............................................................................................................................. 3804
Figure 32-25. SIGGEN0_DATA1 Register............................................................................................................................. 3805
Figure 32-26. SIGGEN0_DATA0_ACTIVE Register.............................................................................................................. 3806
Figure 32-27. SIGGEN0_DATA1_ACTIVE Register.............................................................................................................. 3807
Figure 32-28. REVISION Register.........................................................................................................................................3808
Figure 32-29. EPGMXSEL0 Register.................................................................................................................................... 3810
Figure 32-30. EPGMXSELLOCK Register............................................................................................................................ 3813
Figure 32-31. EPGMXSELCOMMIT Register........................................................................................................................3814

List of Tables
Table 1-1. C2000Ware Root Directories.................................................................................................................................... 92
Table 2-1. TMU Supported Instructions..................................................................................................................................... 96
Table 3-1. Access to EALLOW-Protected Registers................................................................................................................100
Table 3-2. Reset Signals..........................................................................................................................................................100
Table 3-3. PIE Channel Mapping............................................................................................................................................. 108
Table 3-4. CPU Interrupt Vectors..............................................................................................................................................111
Table 3-5. PIE Interrupt Vectors............................................................................................................................................... 112
Table 3-6. ALT Modes.............................................................................................................................................................. 123
Table 3-7. Clock Connections Sorted by Clock Domain.......................................................................................................... 126
Table 3-8. Clock Connections Sorted by Module Name.......................................................................................................... 127
Table 3-9. Clock Source (OSCCLK) Failure Detection............................................................................................................ 131
Table 3-10. Example Watchdog Key Sequences.....................................................................................................................135
Table 3-11. Effect of Clock-Gating Low-Power Modes on the Device......................................................................................137
Table 3-12. Local Shared RAM................................................................................................................................................141
Table 3-13. Global Shared RAM.............................................................................................................................................. 141
Table 3-14. Addressable Memory Range for MCAN Message RAMs..................................................................................... 142
Table 3-15. Error Handling in Different Scenarios....................................................................................................................146
Table 3-16. Mapping of ECC Bits in Read Data from ECC/Parity Address Map..................................................................... 147
Table 3-17. Mapping of Parity Bits in Read Data from ECC/Parity Address Map....................................................................147
Table 3-18. System Control Registers Impacted..................................................................................................................... 153
Table 3-19. SYSCTL Registers to Driverlib Functions............................................................................................................. 154
Table 3-20. CPUTIMER Registers to Driverlib Functions........................................................................................................ 163
Table 3-21. MEMCFG Registers to Driverlib Functions........................................................................................................... 164
Table 3-22. PIE Registers to Driverlib Functions..................................................................................................................... 168
Table 3-23. NMI Registers to Driverlib Functions.................................................................................................................... 169
Table 3-24. XINT Registers to Driverlib Functions...................................................................................................................170
Table 3-25. WWD Registers to Driverlib Functions..................................................................................................................171
Table 3-26. SYSCTRL Base Address Table............................................................................................................................ 178
Table 3-27. CPUTIMER_REGS Registers...............................................................................................................................179
Table 3-28. CPUTIMER_REGS Access Type Codes.............................................................................................................. 179
Table 3-29. TIM Register Field Descriptions............................................................................................................................180
Table 3-30. PRD Register Field Descriptions.......................................................................................................................... 181
Table 3-31. TCR Register Field Descriptions...........................................................................................................................182
Table 3-32. TPR Register Field Descriptions...........................................................................................................................184
Table 3-33. TPRH Register Field Descriptions........................................................................................................................ 185

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 53

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Table 3-34. PIE_CTRL_REGS Registers................................................................................................................................ 186

Table 3-35. PIE_CTRL_REGS Access Type Codes................................................................................................................186
Table 3-36. PIECTRL Register Field Descriptions...................................................................................................................188
Table 3-37. PIEACK Register Field Descriptions.....................................................................................................................189
Table 3-38. PIEIER1 Register Field Descriptions.................................................................................................................... 190
Table 3-39. PIEIFR1 Register Field Descriptions.................................................................................................................... 192
Table 3-40. PIEIER2 Register Field Descriptions.................................................................................................................... 194
Table 3-41. PIEIFR2 Register Field Descriptions.................................................................................................................... 196
Table 3-42. PIEIER3 Register Field Descriptions.................................................................................................................... 198
Table 3-43. PIEIFR3 Register Field Descriptions.................................................................................................................... 200
Table 3-44. PIEIER4 Register Field Descriptions.................................................................................................................... 202
Table 3-45. PIEIFR4 Register Field Descriptions.................................................................................................................... 204
Table 3-46. PIEIER5 Register Field Descriptions.................................................................................................................... 206
Table 3-47. PIEIFR5 Register Field Descriptions.................................................................................................................... 208
Table 3-48. PIEIER6 Register Field Descriptions.................................................................................................................... 210
Table 3-49. PIEIFR6 Register Field Descriptions.................................................................................................................... 212
Table 3-50. PIEIER7 Register Field Descriptions.................................................................................................................... 214
Table 3-51. PIEIFR7 Register Field Descriptions.................................................................................................................... 216
Table 3-52. PIEIER8 Register Field Descriptions.................................................................................................................... 218
Table 3-53. PIEIFR8 Register Field Descriptions.................................................................................................................... 220
Table 3-54. PIEIER9 Register Field Descriptions.................................................................................................................... 222
Table 3-55. PIEIFR9 Register Field Descriptions.................................................................................................................... 224
Table 3-56. PIEIER10 Register Field Descriptions.................................................................................................................. 226
Table 3-57. PIEIFR10 Register Field Descriptions.................................................................................................................. 228
Table 3-58. PIEIER11 Register Field Descriptions...................................................................................................................230
Table 3-59. PIEIFR11 Register Field Descriptions...................................................................................................................232
Table 3-60. PIEIER12 Register Field Descriptions.................................................................................................................. 234
Table 3-61. PIEIFR12 Register Field Descriptions.................................................................................................................. 236
Table 3-62. NMI_INTRUPT_REGS Registers......................................................................................................................... 238
Table 3-63. NMI_INTRUPT_REGS Access Type Codes.........................................................................................................238
Table 3-64. NMICFG Register Field Descriptions....................................................................................................................239
Table 3-65. NMIFLG Register Field Descriptions.................................................................................................................... 240
Table 3-66. NMIFLGCLR Register Field Descriptions............................................................................................................. 242
Table 3-67. NMIFLGFRC Register Field Descriptions............................................................................................................. 244
Table 3-68. NMIWDCNT Register Field Descriptions.............................................................................................................. 245
Table 3-69. NMIWDPRD Register Field Descriptions..............................................................................................................246
Table 3-70. NMISHDFLG Register Field Descriptions.............................................................................................................247
Table 3-71. ERRORSTS Register Field Descriptions.............................................................................................................. 249
Table 3-72. ERRORSTSCLR Register Field Descriptions.......................................................................................................250
Table 3-73. ERRORSTSFRC Register Field Descriptions.......................................................................................................251
Table 3-74. ERRORCTL Register Field Descriptions.............................................................................................................. 252
Table 3-75. ERRORLOCK Register Field Descriptions........................................................................................................... 253
Table 3-76. XINT_REGS Registers......................................................................................................................................... 254
Table 3-77. XINT_REGS Access Type Codes.........................................................................................................................254
Table 3-78. XINT1CR Register Field Descriptions...................................................................................................................255
Table 3-79. XINT2CR Register Field Descriptions...................................................................................................................256
Table 3-80. XINT3CR Register Field Descriptions...................................................................................................................257
Table 3-81. XINT4CR Register Field Descriptions...................................................................................................................258
Table 3-82. XINT5CR Register Field Descriptions...................................................................................................................259
Table 3-83. XINT1CTR Register Field Descriptions................................................................................................................ 260
Table 3-84. XINT2CTR Register Field Descriptions................................................................................................................ 261
Table 3-85. XINT3CTR Register Field Descriptions................................................................................................................ 262
Table 3-86. SYNC_SOC_REGS Registers..............................................................................................................................263
Table 3-87. SYNC_SOC_REGS Access Type Codes............................................................................................................. 263
Table 3-88. SYNCSELECT Register Field Descriptions.......................................................................................................... 264
Table 3-89. ADCSOCOUTSELECT Register Field Descriptions............................................................................................. 266
Table 3-90. SYNCSOCLOCK Register Field Descriptions...................................................................................................... 269
Table 3-91. DMA_CLA_SRC_SEL_REGS Registers.............................................................................................................. 270
Table 3-92. DMA_CLA_SRC_SEL_REGS Access Type Codes..............................................................................................270
Table 3-93. CLA1TASKSRCSELLOCK Register Field Descriptions........................................................................................271
Table 3-94. DMACHSRCSELLOCK Register Field Descriptions.............................................................................................272

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Table 3-95. CLA1TASKSRCSEL1 Register Field Descriptions................................................................................................273

Table 3-96. CLA1TASKSRCSEL2 Register Field Descriptions................................................................................................274
Table 3-97. DMACHSRCSEL1 Register Field Descriptions.................................................................................................... 275
Table 3-98. DMACHSRCSEL2 Register Field Descriptions.................................................................................................... 276
Table 3-99. LFU_REGS Registers...........................................................................................................................................277
Table 3-100. LFU_REGS Access Type Codes........................................................................................................................ 277
Table 3-101. LFUConfig Register Field Descriptions...............................................................................................................278
Table 3-102. LFUStatus Register Field Descriptions............................................................................................................... 279
Table 3-103. LFU_LOCK Register Field Descriptions............................................................................................................. 280
Table 3-104. LFU_COMMIT Register Field Descriptions.........................................................................................................281
Table 3-105. DEV_CFG_REGS Registers...............................................................................................................................283
Table 3-106. DEV_CFG_REGS Access Type Codes.............................................................................................................. 284
Table 3-107. PARTIDL Register Field Descriptions................................................................................................................. 285
Table 3-108. PARTIDH Register Field Descriptions.................................................................................................................287
Table 3-109. REVID Register Field Descriptions..................................................................................................................... 288
Table 3-110. TRIMERRSTS Register Field Descriptions......................................................................................................... 289
Table 3-111. SOFTPRES0 Register Field Descriptions........................................................................................................... 290
Table 3-112. SOFTPRES2 Register Field Descriptions........................................................................................................... 291
Table 3-113. SOFTPRES3 Register Field Descriptions........................................................................................................... 293
Table 3-114. SOFTPRES4 Register Field Descriptions........................................................................................................... 294
Table 3-115. SOFTPRES7 Register Field Descriptions........................................................................................................... 295
Table 3-116. SOFTPRES8 Register Field Descriptions........................................................................................................... 296
Table 3-117. SOFTPRES9 Register Field Descriptions........................................................................................................... 297
Table 3-118. SOFTPRES10 Register Field Descriptions......................................................................................................... 298
Table 3-119. SOFTPRES11 Register Field Descriptions......................................................................................................... 299
Table 3-120. SOFTPRES13 Register Field Descriptions.........................................................................................................300
Table 3-121. SOFTPRES14 Register Field Descriptions.........................................................................................................301
Table 3-122. SOFTPRES15 Register Field Descriptions.........................................................................................................302
Table 3-123. SOFTPRES16 Register Field Descriptions.........................................................................................................303
Table 3-124. SOFTPRES17 Register Field Descriptions.........................................................................................................304
Table 3-125. SOFTPRES18 Register Field Descriptions.........................................................................................................305
Table 3-126. SOFTPRES19 Register Field Descriptions.........................................................................................................306
Table 3-127. SOFTPRES20 Register Field Descriptions.........................................................................................................307
Table 3-128. SOFTPRES21 Register Field Descriptions.........................................................................................................308
Table 3-129. SOFTPRES26 Register Field Descriptions.........................................................................................................309
Table 3-130. SOFTPRES27 Register Field Descriptions.........................................................................................................310
Table 3-131. SOFTPRES28 Register Field Descriptions......................................................................................................... 311
Table 3-132. SOFTPRES30 Register Field Descriptions.........................................................................................................312
Table 3-133. SOFTPRES40 Register Field Descriptions.........................................................................................................313
Table 3-134. TAP_STATUS Register Field Descriptions..........................................................................................................314
Table 3-135. TAP_CONTROL Register Field Descriptions......................................................................................................315
Table 3-136. USBTYPE Register Field Descriptions............................................................................................................... 316
Table 3-137. ECAPTYPE Register Field Descriptions.............................................................................................................317
Table 3-138. MCUCNF3 Register Field Descriptions.............................................................................................................. 318
Table 3-139. MCUCNF8 Register Field Descriptions.............................................................................................................. 320
Table 3-140. MCUCNF11 Register Field Descriptions.............................................................................................................321
Table 3-141. MCUCNF12 Register Field Descriptions............................................................................................................ 322
Table 3-142. MCUCNF14 Register Field Descriptions............................................................................................................ 323
Table 3-143. MCUCNF16 Register Field Descriptions............................................................................................................ 324
Table 3-144. MCUCNF18 Register Field Descriptions............................................................................................................ 325
Table 3-145. MCUCNF20 Register Field Descriptions............................................................................................................ 327
Table 3-146. MCUCNF21 Register Field Descriptions............................................................................................................ 329
Table 3-147. MCUCNF23 Register Field Descriptions............................................................................................................ 330
Table 3-148. MCUCNF31 Register Field Descriptions............................................................................................................ 331
Table 3-149. MCUCNF32 Register Field Descriptions............................................................................................................ 333
Table 3-150. MCUCNF33 Register Field Descriptions............................................................................................................ 335
Table 3-151. MCUCNF34 Register Field Descriptions............................................................................................................ 337
Table 3-152. MCUCNF35 Register Field Descriptions............................................................................................................ 339
Table 3-153. MCUCNFLOCK Register Field Descriptions.......................................................................................................340
Table 3-154. CLK_CFG_REGS Registers............................................................................................................................... 341
Table 3-155. CLK_CFG_REGS Access Type Codes.............................................................................................................. 341

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Table 3-156. CLKCFGLOCK1 Register Field Descriptions......................................................................................................343

Table 3-157. CLKSRCCTL1 Register Field Descriptions.........................................................................................................345
Table 3-158. CLKSRCCTL2 Register Field Descriptions.........................................................................................................347
Table 3-159. CLKSRCCTL3 Register Field Descriptions.........................................................................................................348
Table 3-160. SYSPLLCTL1 Register Field Descriptions..........................................................................................................349
Table 3-161. SYSPLLMULT Register Field Descriptions......................................................................................................... 350
Table 3-162. SYSPLLSTS Register Field Descriptions........................................................................................................... 351
Table 3-163. SYSCLKDIVSEL Register Field Descriptions..................................................................................................... 352
Table 3-164. AUXCLKDIVSEL Register Field Descriptions.....................................................................................................353
Table 3-165. PERCLKDIVSEL Register Field Descriptions.....................................................................................................354
Table 3-166. XCLKOUTDIVSEL Register Field Descriptions.................................................................................................. 355
Table 3-167. CLBCLKCTL Register Field Descriptions........................................................................................................... 356
Table 3-168. LOSPCP Register Field Descriptions................................................................................................................. 357
Table 3-169. MCDCR Register Field Descriptions...................................................................................................................358
Table 3-170. X1CNT Register Field Descriptions.................................................................................................................... 360
Table 3-171. XTALCR Register Field Descriptions.................................................................................................................. 361
Table 3-172. XTALCR2 Register Field Descriptions................................................................................................................ 362
Table 3-173. CLKFAILCFG Register Field Descriptions.......................................................................................................... 363
Table 3-174. CPU_SYS_REGS Registers...............................................................................................................................364
Table 3-175. CPU_SYS_REGS Access Type Codes.............................................................................................................. 365
Table 3-176. CPUSYSLOCK1 Register Field Descriptions..................................................................................................... 366
Table 3-177. CPUSYSLOCK2 Register Field Descriptions..................................................................................................... 369
Table 3-178. PIEVERRADDR Register Field Descriptions...................................................................................................... 371
Table 3-179. PCLKCR0 Register Field Descriptions............................................................................................................... 372
Table 3-180. PCLKCR2 Register Field Descriptions............................................................................................................... 374
Table 3-181. PCLKCR3 Register Field Descriptions............................................................................................................... 376
Table 3-182. PCLKCR4 Register Field Descriptions............................................................................................................... 377
Table 3-183. PCLKCR7 Register Field Descriptions............................................................................................................... 378
Table 3-184. PCLKCR8 Register Field Descriptions............................................................................................................... 379
Table 3-185. PCLKCR9 Register Field Descriptions............................................................................................................... 380
Table 3-186. PCLKCR10 Register Field Descriptions............................................................................................................. 381
Table 3-187. PCLKCR11 Register Field Descriptions..............................................................................................................382
Table 3-188. PCLKCR12 Register Field Descriptions............................................................................................................. 383
Table 3-189. PCLKCR13 Register Field Descriptions............................................................................................................. 384
Table 3-190. PCLKCR14 Register Field Descriptions............................................................................................................. 385
Table 3-191. PCLKCR15 Register Field Descriptions............................................................................................................. 386
Table 3-192. PCLKCR16 Register Field Descriptions............................................................................................................. 387
Table 3-193. PCLKCR17 Register Field Descriptions............................................................................................................. 388
Table 3-194. PCLKCR18 Register Field Descriptions............................................................................................................. 389
Table 3-195. PCLKCR19 Register Field Descriptions............................................................................................................. 390
Table 3-196. PCLKCR20 Register Field Descriptions............................................................................................................. 391
Table 3-197. PCLKCR21 Register Field Descriptions............................................................................................................. 392
Table 3-198. PCLKCR26 Register Field Descriptions............................................................................................................. 393
Table 3-199. PCLKCR27 Register Field Descriptions............................................................................................................. 394
Table 3-200. SIMRESET Register Field Descriptions..............................................................................................................395
Table 3-201. LPMCR Register Field Descriptions................................................................................................................... 396
Table 3-202. GPIOLPMSEL0 Register Field Descriptions.......................................................................................................397
Table 3-203. GPIOLPMSEL1 Register Field Descriptions.......................................................................................................400
Table 3-204. TMR2CLKCTL Register Field Descriptions........................................................................................................ 403
Table 3-205. RESCCLR Register Field Descriptions...............................................................................................................404
Table 3-206. RESC Register Field Descriptions...................................................................................................................... 406
Table 3-207. CMPSSLPMSEL Register Field Descriptions..................................................................................................... 408
Table 3-208. MCANRAMACC Register Field Descriptions......................................................................................................410
Table 3-209. MCANWAKESTATUS Register Field Descriptions..............................................................................................411
Table 3-210. MCANWAKESTATUSCLR Register Field Descriptions...................................................................................... 412
Table 3-211. CLKSTOPREQ Register Field Descriptions........................................................................................................413
Table 3-212. CLKSTOPACK Register Field Descriptions........................................................................................................ 414
Table 3-213. USER_REG1_SYSRSn Register Field Descriptions.......................................................................................... 415
Table 3-214. USER_REG2_SYSRSn Register Field Descriptions.......................................................................................... 416
Table 3-215. USER_REG1_XRSn Register Field Descriptions...............................................................................................417
Table 3-216. USER_REG2_XRSn Register Field Descriptions...............................................................................................418

56 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 3-217. USER_REG1_PORESETn Register Field Descriptions..................................................................................... 419

Table 3-218. USER_REG2_PORESETn Register Field Descriptions..................................................................................... 420
Table 3-219. USER_REG3_PORESETn Register Field Descriptions..................................................................................... 421
Table 3-220. USER_REG4_PORESETn Register Field Descriptions..................................................................................... 422
Table 3-221. JTAG_MMR_REG Register Field Descriptions...................................................................................................423
Table 3-222. SYS_STATUS_REGS Registers.........................................................................................................................424
Table 3-223. SYS_STATUS_REGS Access Type Codes........................................................................................................ 424
Table 3-224. SYS_ERR_INT_FLG Register Field Descriptions.............................................................................................. 425
Table 3-225. SYS_ERR_INT_CLR Register Field Descriptions.............................................................................................. 427
Table 3-226. SYS_ERR_INT_SET Register Field Descriptions.............................................................................................. 429
Table 3-227. SYS_ERR_MASK Register Field Descriptions................................................................................................... 431
Table 3-228. PERIPH_AC_REGS Registers........................................................................................................................... 433
Table 3-229. PERIPH_AC_REGS Access Type Codes...........................................................................................................434
Table 3-230. ADCA_AC Register Field Descriptions............................................................................................................... 435
Table 3-231. ADCB_AC Register Field Descriptions............................................................................................................... 436
Table 3-232. ADCC_AC Register Field Descriptions...............................................................................................................437
Table 3-233. ADCD_AC Register Field Descriptions...............................................................................................................438
Table 3-234. ADCE_AC Register Field Descriptions............................................................................................................... 439
Table 3-235. CMPSS1_AC Register Field Descriptions.......................................................................................................... 440
Table 3-236. CMPSS2_AC Register Field Descriptions.......................................................................................................... 441
Table 3-237. CMPSS3_AC Register Field Descriptions.......................................................................................................... 442
Table 3-238. CMPSS4_AC Register Field Descriptions.......................................................................................................... 443
Table 3-239. DACA_AC Register Field Descriptions............................................................................................................... 444
Table 3-240. PGA1_AC Register Field Descriptions............................................................................................................... 445
Table 3-241. PGA2_AC Register Field Descriptions............................................................................................................... 446
Table 3-242. PGA3_AC Register Field Descriptions............................................................................................................... 447
Table 3-243. EPWM1_AC Register Field Descriptions............................................................................................................448
Table 3-244. EPWM2_AC Register Field Descriptions............................................................................................................449
Table 3-245. EPWM3_AC Register Field Descriptions............................................................................................................450
Table 3-246. EPWM4_AC Register Field Descriptions............................................................................................................451
Table 3-247. EPWM5_AC Register Field Descriptions............................................................................................................452
Table 3-248. EPWM6_AC Register Field Descriptions............................................................................................................453
Table 3-249. EPWM7_AC Register Field Descriptions............................................................................................................454
Table 3-250. EPWM8_AC Register Field Descriptions............................................................................................................455
Table 3-251. EPWM9_AC Register Field Descriptions............................................................................................................456
Table 3-252. EPWM10_AC Register Field Descriptions..........................................................................................................457
Table 3-253. EPWM11_AC Register Field Descriptions.......................................................................................................... 458
Table 3-254. EPWM12_AC Register Field Descriptions..........................................................................................................459
Table 3-255. EQEP1_AC Register Field Descriptions............................................................................................................. 460
Table 3-256. EQEP2_AC Register Field Descriptions............................................................................................................. 461
Table 3-257. EQEP3_AC Register Field Descriptions............................................................................................................. 462
Table 3-258. ECAP1_AC Register Field Descriptions............................................................................................................. 463
Table 3-259. ECAP2_AC Register Field Descriptions............................................................................................................. 464
Table 3-260. CLB1_AC Register Field Descriptions................................................................................................................ 465
Table 3-261. CLB2_AC Register Field Descriptions................................................................................................................ 466
Table 3-262. SCIA_AC Register Field Descriptions.................................................................................................................467
Table 3-263. SCIB_AC Register Field Descriptions.................................................................................................................468
Table 3-264. SCIC_AC Register Field Descriptions................................................................................................................ 469
Table 3-265. SPIA_AC Register Field Descriptions.................................................................................................................470
Table 3-266. SPIB_AC Register Field Descriptions.................................................................................................................471
Table 3-267. I2CA_AC Register Field Descriptions................................................................................................................. 472
Table 3-268. I2CB_AC Register Field Descriptions................................................................................................................. 473
Table 3-269. PMBUS_A_AC Register Field Descriptions........................................................................................................474
Table 3-270. LIN_A_AC Register Field Descriptions............................................................................................................... 475
Table 3-271. MCANA_AC Register Field Descriptions............................................................................................................ 476
Table 3-272. MCANB_AC Register Field Descriptions............................................................................................................ 477
Table 3-273. FSIATX_AC Register Field Descriptions.............................................................................................................478
Table 3-274. FSIARX_AC Register Field Descriptions............................................................................................................ 479
Table 3-275. USBA_AC Register Field Descriptions............................................................................................................... 480
Table 3-276. HRPWM_A_AC Register Field Descriptions.......................................................................................................481
Table 3-277. AESA_AC Register Field Descriptions............................................................................................................... 482

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 57

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Table 3-278. PERIPH_AC_LOCK Register Field Descriptions................................................................................................483

Table 3-279. MEM_CFG_REGS Registers..............................................................................................................................484
Table 3-280. MEM_CFG_REGS Access Type Codes............................................................................................................. 485
Table 3-281. DxLOCK Register Field Descriptions..................................................................................................................486
Table 3-282. DxCOMMIT Register Field Descriptions............................................................................................................. 487
Table 3-283. DxACCPROT0 Register Field Descriptions........................................................................................................ 488
Table 3-284. DxACCPROT1 Register Field Descriptions........................................................................................................ 489
Table 3-285. DxTEST Register Field Descriptions.................................................................................................................. 490
Table 3-286. DxINIT Register Field Descriptions.....................................................................................................................491
Table 3-287. DxINITDONE Register Field Descriptions.......................................................................................................... 492
Table 3-288. DxRAMTEST_LOCK Register Field Descriptions...............................................................................................493
Table 3-289. LSxLOCK Register Field Descriptions................................................................................................................ 494
Table 3-290. LSxCOMMIT Register Field Descriptions........................................................................................................... 496
Table 3-291. LSxMSEL Register Field Descriptions................................................................................................................ 498
Table 3-292. LSxCLAPGM Register Field Descriptions...........................................................................................................500
Table 3-293. LSxACCPROT0 Register Field Descriptions...................................................................................................... 502
Table 3-294. LSxACCPROT1 Register Field Descriptions...................................................................................................... 504
Table 3-295. LSxACCPROT2_y Register Field Descriptions.................................................................................................. 506
Table 3-296. LSxTEST Register Field Descriptions.................................................................................................................507
Table 3-297. LSxINIT Register Field Descriptions................................................................................................................... 510
Table 3-298. LSxINITDONE Register Field Descriptions.........................................................................................................512
Table 3-299. LSxRAMTEST_LOCK Register Field Descriptions.............................................................................................513
Table 3-300. GSxLOCK Register Field Descriptions............................................................................................................... 514
Table 3-301. GSxCOMMIT Register Field Descriptions.......................................................................................................... 516
Table 3-302. GSxACCPROT0 Register Field Descriptions..................................................................................................... 518
Table 3-303. GSxTEST Register Field Descriptions................................................................................................................520
Table 3-304. GSxINIT Register Field Descriptions.................................................................................................................. 522
Table 3-305. GSxINITDONE Register Field Descriptions........................................................................................................524
Table 3-306. GSxRAMTEST_LOCK Register Field Descriptions............................................................................................ 526
Table 3-307. MSGxLOCK Register Field Descriptions............................................................................................................ 527
Table 3-308. MSGxCOMMIT Register Field Descriptions....................................................................................................... 529
Table 3-309. MSGxTEST Register Field Descriptions.............................................................................................................531
Table 3-310. MSGxINIT Register Field Descriptions............................................................................................................... 533
Table 3-311. MSGxINITDONE Register Field Descriptions..................................................................................................... 534
Table 3-312. MSGxRAMTEST_LOCK Register Field Descriptions......................................................................................... 535
Table 3-313. ROM_LOCK Register Field Descriptions............................................................................................................536
Table 3-314. ROM_TEST Register Field Descriptions............................................................................................................ 537
Table 3-315. ROM_FORCE_ERROR Register Field Descriptions.......................................................................................... 538
Table 3-316. ACCESS_PROTECTION_REGS Registers....................................................................................................... 539
Table 3-317. ACCESS_PROTECTION_REGS Access Type Codes.......................................................................................539
Table 3-318. NMAVFLG Register Field Descriptions............................................................................................................... 541
Table 3-319. NMAVSET Register Field Descriptions............................................................................................................... 543
Table 3-320. NMAVCLR Register Field Descriptions...............................................................................................................545
Table 3-321. NMAVINTEN Register Field Descriptions........................................................................................................... 547
Table 3-322. NMCPURDAVADDR Register Field Descriptions............................................................................................... 549
Table 3-323. NMCPUWRAVADDR Register Field Descriptions.............................................................................................. 550
Table 3-324. NMCPUFAVADDR Register Field Descriptions.................................................................................................. 551
Table 3-325. NMDMAWRAVADDR Register Field Descriptions.............................................................................................. 552
Table 3-326. NMCLA1RDAVADDR Register Field Descriptions..............................................................................................553
Table 3-327. NMCLA1WRAVADDR Register Field Descriptions............................................................................................. 554
Table 3-328. NMCLA1FAVADDR Register Field Descriptions................................................................................................. 555
Table 3-329. NMDMARDAVADDR Register Field Descriptions...............................................................................................556
Table 3-330. MAVFLG Register Field Descriptions..................................................................................................................557
Table 3-331. MAVSET Register Field Descriptions..................................................................................................................558
Table 3-332. MAVCLR Register Field Descriptions................................................................................................................. 559
Table 3-333. MAVINTEN Register Field Descriptions..............................................................................................................560
Table 3-334. MCPUFAVADDR Register Field Descriptions..................................................................................................... 561
Table 3-335. MCPUWRAVADDR Register Field Descriptions................................................................................................. 562
Table 3-336. MDMAWRAVADDR Register Field Descriptions.................................................................................................563
Table 3-337. NMNPURDAVADDR Register Field Descriptions............................................................................................... 564
Table 3-338. NMNPUWRAVADDR Register Field Descriptions.............................................................................................. 565

58 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 3-339. MEMORY_ERROR_REGS Registers.................................................................................................................566

Table 3-340. MEMORY_ERROR_REGS Access Type Codes................................................................................................ 566
Table 3-341. UCERRFLG Register Field Descriptions............................................................................................................ 568
Table 3-342. UCERRSET Register Field Descriptions............................................................................................................ 569
Table 3-343. UCERRCLR Register Field Descriptions............................................................................................................ 570
Table 3-344. UCCPUREADDR Register Field Descriptions.................................................................................................... 571
Table 3-345. UCDMAREADDR Register Field Descriptions....................................................................................................572
Table 3-346. UCCLA1READDR Register Field Descriptions...................................................................................................573
Table 3-347. UCNPUREADDR Register Field Descriptions.................................................................................................... 574
Table 3-348. FLUCERRSTATUS Register Field Descriptions................................................................................................. 575
Table 3-349. FLCERRSTATUS Register Field Descriptions.................................................................................................... 576
Table 3-350. CERRFLG Register Field Descriptions...............................................................................................................578
Table 3-351. CERRSET Register Field Descriptions...............................................................................................................579
Table 3-352. CERRCLR Register Field Descriptions...............................................................................................................580
Table 3-353. CCPUREADDR Register Field Descriptions.......................................................................................................581
Table 3-354. CDMAREADDR Register Field Descriptions...................................................................................................... 582
Table 3-355. CCLA1READDR Register Field Descriptions..................................................................................................... 583
Table 3-356. CERRCNT Register Field Descriptions.............................................................................................................. 584
Table 3-357. CERRTHRES Register Field Descriptions..........................................................................................................585
Table 3-358. CEINTFLG Register Field Descriptions.............................................................................................................. 586
Table 3-359. CEINTCLR Register Field Descriptions.............................................................................................................. 587
Table 3-360. CEINTSET Register Field Descriptions.............................................................................................................. 588
Table 3-361. CEINTEN Register Field Descriptions................................................................................................................ 589
Table 3-362. TEST_ERROR_REGS Registers....................................................................................................................... 590
Table 3-363. TEST_ERROR_REGS Access Type Codes.......................................................................................................590
Table 3-364. CPU_RAM_TEST_ERROR_STS Register Field Descriptions........................................................................... 591
Table 3-365. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions.................................................................. 592
Table 3-366. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions........................................................................ 593
Table 3-367. UID_REGS Registers......................................................................................................................................... 594
Table 3-368. UID_REGS Access Type Codes.........................................................................................................................594
Table 3-369. UID_PSRAND0 Register Field Descriptions.......................................................................................................595
Table 3-370. UID_PSRAND1 Register Field Descriptions.......................................................................................................596
Table 3-371. UID_PSRAND2 Register Field Descriptions.......................................................................................................597
Table 3-372. UID_PSRAND3 Register Field Descriptions.......................................................................................................598
Table 3-373. UID_PSRAND4 Register Field Descriptions.......................................................................................................599
Table 3-374. UID_UNIQUE0 Register Field Descriptions........................................................................................................600
Table 3-375. UID_UNIQUE1 Register Field Descriptions........................................................................................................601
Table 3-376. UID_CHECKSUM Register Field Descriptions................................................................................................... 602
Table 4-1. Boot System Overview............................................................................................................................................604
Table 4-2. ROM Memory..........................................................................................................................................................604
Table 4-3. Device Boot ROM Sequence.................................................................................................................................. 605
Table 4-4. Device Default Boot Modes.................................................................................................................................... 605
Table 4-5. Custom Boot Modes............................................................................................................................................... 606
Table 4-6. BOOTPIN-CONFIG Bit Fields.................................................................................................................................607
Table 4-7. Standalone Boot Mode Select Pin Decoding.......................................................................................................... 608
Table 4-8. BOOTDEF Bit Fields...............................................................................................................................................609
Table 4-9. Zero Boot Pin Boot Table Result.............................................................................................................................610
Table 4-10. One Boot Pin Boot Table Result........................................................................................................................... 610
Table 4-11. Three Boot Pins Boot Table Result........................................................................................................................611
Table 4-12. Boot ROM Reset Causes and Actions..................................................................................................................615
Table 4-13. Boot ROM Exceptions and Actions.......................................................................................................................616
Table 4-14. Boot ROM Registers............................................................................................................................................. 617
Table 4-15. DCSM Z1 GPREG2 Bit Fields.............................................................................................................................. 618
Table 4-16. DCSM Z1/Z2 DIAG Bit Fields............................................................................................................................... 619
Table 4-17. Flash Entry Point Addresses.................................................................................................................................619
Table 4-18. RAM Entry Point Address..................................................................................................................................... 619
Table 4-19. Wait Boot Options................................................................................................................................................. 620
Table 4-20. Wait Point Addresses............................................................................................................................................620
Table 4-21. Secure Flash Tag and Key Details........................................................................................................................621
Table 4-22. Secure Flash Entry Point Addresses.................................................................................................................... 622
Table 4-23. Secure Flash Authentication Failure Actions........................................................................................................ 622

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 59

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Table 4-24. Secure Flash on all CPUs Recommended Flow...................................................................................................622

Table 4-25. FWU Application Image Format............................................................................................................................623
Table 4-26. FWU Entry Point Addresses................................................................................................................................. 623
Table 4-27. Boot ROM Memory Map....................................................................................................................................... 624
Table 4-28. Secure ROM Memory Map................................................................................................................................... 624
Table 4-29. CLA Data ROM Memory Map............................................................................................................................... 624
Table 4-30. Reserved RAM Memory Map................................................................................................................................625
Table 4-31. ROM Symbol Tables............................................................................................................................................. 625
Table 4-32. Boot Mode Availability...........................................................................................................................................625
Table 4-33. Wait Boot Options................................................................................................................................................. 625
Table 4-34. SPI 8-Bit Data Stream...........................................................................................................................................628
Table 4-35. I2C 8-Bit Data Stream...........................................................................................................................................633
Table 4-36. Parallel GPIO Boot 8-Bit Data Stream.................................................................................................................. 634
Table 4-37. Bit-Rate Value for Internal Oscillators................................................................................................................... 638
Table 4-38. CAN 8-Bit Data Stream.........................................................................................................................................639
Table 4-39. CAN-FD 8-Bit Data Stream...................................................................................................................................640
Table 4-40. USB 8-Bit Data Stream......................................................................................................................................... 642
Table 4-41. SCI Boot Options.................................................................................................................................................. 643
Table 4-42. CAN Boot Options.................................................................................................................................................643
Table 4-43. CAN-FD Boot Options...........................................................................................................................................643
Table 4-44. I2C Boot Options...................................................................................................................................................643
Table 4-45. SPI Boot Options.................................................................................................................................................. 644
Table 4-46. Parallel Boot Options............................................................................................................................................ 644
Table 4-47. USB Boot Options.................................................................................................................................................644
Table 4-48. Secure Copy Code Function.................................................................................................................................645
Table 4-49. Secure CRC Calculation Function........................................................................................................................ 645
Table 4-50. Secure CRC Calculation Function........................................................................................................................ 646
Table 4-51. CPU Boot Clock Sources......................................................................................................................................646
Table 4-52. CPU Clock State After Boot.................................................................................................................................. 646
Table 4-53. Boot Status Address............................................................................................................................................. 647
Table 4-54. Boot Status Bit Fields............................................................................................................................................647
Table 4-55. Boot Mode and MPOST Status Addresses...........................................................................................................648
Table 4-56. Boot ROM Version Information............................................................................................................................. 648
Table 4-57. LSB/MSB Loading Sequence in 8-Bit Data Stream.............................................................................................. 649
Table 4-58. Boot Loader Options............................................................................................................................................. 651
Table 5-1. RAM/Flash Status................................................................................................................................................... 654
Table 5-2. Security Levels........................................................................................................................................................654
Table 5-3. Default Value of ZxOTP (Programmed by TI)......................................................................................................... 655
Table 5-4. DCSM Registers to Driverlib Functions.................................................................................................................. 667
Table 5-5. DCSM Base Address Table.................................................................................................................................... 672
Table 5-6. DCSM_Z1_REGS Registers...................................................................................................................................673
Table 5-7. DCSM_Z1_REGS Access Type Codes.................................................................................................................. 673
Table 5-8. Z1_LINKPOINTER Register Field Descriptions......................................................................................................675
Table 5-9. Z1_OTPSECLOCK Register Field Descriptions..................................................................................................... 676
Table 5-10. Z1_JLM_ENABLE Register Field Descriptions.....................................................................................................677
Table 5-11. Z1_LINKPOINTERERR Register Field Descriptions.............................................................................................678
Table 5-12. Z1_GPREG1 Register Field Descriptions.............................................................................................................679
Table 5-13. Z1_GPREG2 Register Field Descriptions.............................................................................................................680
Table 5-14. Z1_GPREG3 Register Field Descriptions.............................................................................................................681
Table 5-15. Z1_GPREG4 Register Field Descriptions.............................................................................................................682
Table 5-16. Z1_CSMKEY0 Register Field Descriptions...........................................................................................................683
Table 5-17. Z1_CSMKEY1 Register Field Descriptions...........................................................................................................684
Table 5-18. Z1_CSMKEY2 Register Field Descriptions...........................................................................................................685
Table 5-19. Z1_CSMKEY3 Register Field Descriptions...........................................................................................................686
Table 5-20. Z1_CR Register Field Descriptions.......................................................................................................................687
Table 5-21. Z1_GRABSECT1R Register Field Descriptions................................................................................................... 689
Table 5-22. Z1_GRABSECT2R Register Field Descriptions................................................................................................... 693
Table 5-23. Z1_GRABSECT3R Register Field Descriptions................................................................................................... 697
Table 5-24. Z1_GRABRAM1R Register Field Descriptions..................................................................................................... 699
Table 5-25. Z1_EXEONLYSECT1R Register Field Descriptions............................................................................................. 702
Table 5-26. Z1_EXEONLYSECT2R Register Field Descriptions............................................................................................. 708

60 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 5-27. Z1_EXEONLYRAM1R Register Field Descriptions...............................................................................................710

Table 5-28. Z1_JTAGKEY0 Register Field Descriptions..........................................................................................................712
Table 5-29. Z1_JTAGKEY1 Register Field Descriptions..........................................................................................................713
Table 5-30. Z1_JTAGKEY2 Register Field Descriptions..........................................................................................................714
Table 5-31. Z1_JTAGKEY3 Register Field Descriptions..........................................................................................................715
Table 5-32. Z1_CMACKEY0 Register Field Descriptions........................................................................................................ 716
Table 5-33. Z1_CMACKEY1 Register Field Descriptions........................................................................................................ 717
Table 5-34. Z1_CMACKEY2 Register Field Descriptions........................................................................................................ 718
Table 5-35. Z1_CMACKEY3 Register Field Descriptions........................................................................................................ 719
Table 5-36. Z1_DIAG Register Field Descriptions................................................................................................................... 720
Table 5-37. DCSM_Z2_REGS Registers.................................................................................................................................721
Table 5-38. DCSM_Z2_REGS Access Type Codes................................................................................................................ 721
Table 5-39. Z2_LINKPOINTER Register Field Descriptions....................................................................................................722
Table 5-40. Z2_OTPSECLOCK Register Field Descriptions................................................................................................... 723
Table 5-41. Z2_LINKPOINTERERR Register Field Descriptions............................................................................................ 724
Table 5-42. Z2_GPREG1 Register Field Descriptions.............................................................................................................725
Table 5-43. Z2_GPREG2 Register Field Descriptions.............................................................................................................726
Table 5-44. Z2_GPREG3 Register Field Descriptions.............................................................................................................727
Table 5-45. Z2_GPREG4 Register Field Descriptions.............................................................................................................728
Table 5-46. Z2_CSMKEY0 Register Field Descriptions...........................................................................................................729
Table 5-47. Z2_CSMKEY1 Register Field Descriptions...........................................................................................................730
Table 5-48. Z2_CSMKEY2 Register Field Descriptions...........................................................................................................731
Table 5-49. Z2_CSMKEY3 Register Field Descriptions...........................................................................................................732
Table 5-50. Z2_CR Register Field Descriptions.......................................................................................................................733
Table 5-51. Z2_GRABSECT1R Register Field Descriptions................................................................................................... 735
Table 5-52. Z2_GRABSECT2R Register Field Descriptions................................................................................................... 739
Table 5-53. Z2_GRABSECT3R Register Field Descriptions................................................................................................... 743
Table 5-54. Z2_GRABRAM1R Register Field Descriptions..................................................................................................... 745
Table 5-55. Z2_EXEONLYSECT1R Register Field Descriptions............................................................................................. 748
Table 5-56. Z2_EXEONLYSECT2R Register Field Descriptions............................................................................................. 754
Table 5-57. Z2_EXEONLYRAM1R Register Field Descriptions...............................................................................................756
Table 5-58. DCSM_COMMON_REGS Registers.................................................................................................................... 758
Table 5-59. DCSM_COMMON_REGS Access Type Codes....................................................................................................758
Table 5-60. FLSEM Register Field Descriptions...................................................................................................................... 759
Table 5-61. SECTSTAT1 Register Field Descriptions..............................................................................................................760
Table 5-62. SECTSTAT2 Register Field Descriptions..............................................................................................................763
Table 5-63. SECTSTAT3 Register Field Descriptions..............................................................................................................766
Table 5-64. RAMSTAT1 Register Field Descriptions............................................................................................................... 768
Table 5-65. SECERRSTAT Register Field Descriptions.......................................................................................................... 770
Table 5-66. SECERRCLR Register Field Descriptions............................................................................................................771
Table 5-67. SECERRFRC Register Field Descriptions............................................................................................................772
Table 5-68. DENYCODE Register Field Descriptions..............................................................................................................773
Table 5-69. UID_UNIQUE_31_0 Register Field Descriptions..................................................................................................775
Table 5-70. UID_UNIQUE_63_32 Register Field Descriptions................................................................................................776
Table 5-71. PARTIDH Register Field Descriptions...................................................................................................................777
Table 5-72. PERSEM1 Register Field Descriptions.................................................................................................................778
Table 5-73. DCSM_Z1_OTP Registers....................................................................................................................................780
Table 5-74. DCSM_Z1_OTP Access Type Codes................................................................................................................... 780
Table 5-75. Z1OTP_LINKPOINTER1 Register Field Descriptions.......................................................................................... 781
Table 5-76. Z1OTP_LINKPOINTER2 Register Field Descriptions.......................................................................................... 782
Table 5-77. Z1OTP_LINKPOINTER3 Register Field Descriptions.......................................................................................... 783
Table 5-78. Z1OTP_JLM_ENABLE Register Field Descriptions............................................................................................. 784
Table 5-79. Z1OTP_GPREG1 Register Field Descriptions..................................................................................................... 785
Table 5-80. Z1OTP_GPREG2 Register Field Descriptions..................................................................................................... 786
Table 5-81. Z1OTP_GPREG3 Register Field Descriptions..................................................................................................... 787
Table 5-82. Z1OTP_GPREG4 Register Field Descriptions..................................................................................................... 788
Table 5-83. Z1OTP_PSWDLOCK Register Field Descriptions................................................................................................789
Table 5-84. Z1OTP_CRCLOCK Register Field Descriptions...................................................................................................790
Table 5-85. Z1OTP_JTAGPSWDH0 Register Field Descriptions............................................................................................ 791
Table 5-86. Z1OTP_JTAGPSWDH1 Register Field Descriptions............................................................................................ 792
Table 5-87. Z1OTP_CMACKEY0 Register Field Descriptions.................................................................................................793

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Table 5-88. Z1OTP_CMACKEY1 Register Field Descriptions.................................................................................................794

Table 5-89. Z1OTP_CMACKEY2 Register Field Descriptions.................................................................................................795
Table 5-90. Z1OTP_CMACKEY3 Register Field Descriptions.................................................................................................796
Table 5-91. DCSM_Z2_OTP Registers....................................................................................................................................797
Table 5-92. DCSM_Z2_OTP Access Type Codes................................................................................................................... 797
Table 5-93. Z2OTP_LINKPOINTER1 Register Field Descriptions.......................................................................................... 798
Table 5-94. Z2OTP_LINKPOINTER2 Register Field Descriptions.......................................................................................... 799
Table 5-95. Z2OTP_LINKPOINTER3 Register Field Descriptions.......................................................................................... 800
Table 5-96. Z2OTP_GPREG1 Register Field Descriptions..................................................................................................... 801
Table 5-97. Z2OTP_GPREG2 Register Field Descriptions..................................................................................................... 802
Table 5-98. Z2OTP_GPREG3 Register Field Descriptions..................................................................................................... 803
Table 5-99. Z2OTP_GPREG4 Register Field Descriptions..................................................................................................... 804
Table 5-100. Z2OTP_PSWDLOCK Register Field Descriptions..............................................................................................805
Table 5-101. Z2OTP_CRCLOCK Register Field Descriptions.................................................................................................806
Table 6-1. FLASH Registers to Driverlib Functions................................................................................................................. 820
Table 6-2. FLASH Base Address Table................................................................................................................................... 821
Table 6-3. FLASH_CTRL_REGS Registers.............................................................................................................................822
Table 6-4. FLASH_CTRL_REGS Access Type Codes............................................................................................................ 822
Table 6-5. FRDCNTL Register Field Descriptions................................................................................................................... 823
Table 6-6. FLPROT Register Field Descriptions......................................................................................................................824
Table 6-7. FRD_INTF_CTRL Register Field Descriptions....................................................................................................... 825
Table 6-8. FLASH_ECC_REGS Registers.............................................................................................................................. 826
Table 6-9. FLASH_ECC_REGS Access Type Codes..............................................................................................................826
Table 6-10. ECC_ENABLE Register Field Descriptions.......................................................................................................... 827
Table 6-11. FECC_CTRL Register Field Descriptions............................................................................................................. 828
Table 7-1. Configuration Options............................................................................................................................................. 834
Table 7-2. Write Followed by Read - Read Occurs First..........................................................................................................845
Table 7-3. Write Followed by Read - Write Occurs First.......................................................................................................... 845
Table 7-4. ADC to CLA Early Interrupt Response....................................................................................................................848
Table 7-5. CLA Registers to Driverlib Functions...................................................................................................................... 850
Table 7-6. Operand Nomenclature...........................................................................................................................................857
Table 7-7. INSTRUCTION dest, source1, source2 Short Description..................................................................................... 858
Table 7-8. Addressing Modes.................................................................................................................................................. 859
Table 7-9. Shift Field Encoding................................................................................................................................................ 859
Table 7-10. Operand Encoding................................................................................................................................................ 860
Table 7-11. Condition Field Encoding...................................................................................................................................... 860
Table 7-12. Pipeline Activity for MBCNDD, Branch Not Taken................................................................................................ 878
Table 7-13. Pipeline Activity for MBCNDD, Branch Taken.......................................................................................................878
Table 7-14. Pipeline Activity for MCCNDD, Call Not Taken..................................................................................................... 883
Table 7-15. Pipeline Activity for MCCNDD, Call Taken............................................................................................................884
Table 7-16. Pipeline Activity for MMOV16 MARx, MRa , #16I................................................................................................. 924
Table 7-17. Pipeline Activity for MMOV16 MAR0/MAR1, mem16........................................................................................... 927
Table 7-18. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I............................................................................................... 945
Table 7-19. Pipeline Activity for MRCNDD, Return Not Taken.................................................................................................969
Table 7-20. Pipeline Activity for MRCNDD, Return Taken....................................................................................................... 969
Table 7-21. Pipeline Activity for MSTOP.................................................................................................................................. 972
Table 7-22. CLA Base Address Table...................................................................................................................................... 988
Table 7-23. CLA_ONLY_REGS Registers............................................................................................................................... 989
Table 7-24. CLA_ONLY_REGS Access Type Codes...............................................................................................................989
Table 7-25. _MVECTBGRNDACTIVE Register Field Descriptions......................................................................................... 990
Table 7-26. _MPSACTL Register Field Descriptions............................................................................................................... 991
Table 7-27. _MPSA1 Register Field Descriptions....................................................................................................................993
Table 7-28. _MPSA2 Register Field Descriptions....................................................................................................................994
Table 7-29. SOFTINTEN Register Field Descriptions..............................................................................................................995
Table 7-30. SOFTINTFRC Register Field Descriptions........................................................................................................... 997
Table 7-31. CLA_SOFTINT_REGS Registers......................................................................................................................... 998
Table 7-32. CLA_SOFTINT_REGS Access Type Codes.........................................................................................................998
Table 7-33. SOFTINTEN Register Field Descriptions..............................................................................................................999
Table 7-34. SOFTINTFRC Register Field Descriptions......................................................................................................... 1001
Table 7-35. CLA_REGS Registers.........................................................................................................................................1002
Table 7-36. CLA_REGS Access Type Codes........................................................................................................................ 1002

62 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 7-37. MVECT1 Register Field Descriptions................................................................................................................. 1004

Table 7-38. MVECT2 Register Field Descriptions................................................................................................................. 1005
Table 7-39. MVECT3 Register Field Descriptions................................................................................................................. 1006
Table 7-40. MVECT4 Register Field Descriptions................................................................................................................. 1007
Table 7-41. MVECT5 Register Field Descriptions................................................................................................................. 1008
Table 7-42. MVECT6 Register Field Descriptions................................................................................................................. 1009
Table 7-43. MVECT7 Register Field Descriptions................................................................................................................. 1010
Table 7-44. MVECT8 Register Field Descriptions..................................................................................................................1011
Table 7-45. MCTL Register Field Descriptions...................................................................................................................... 1012
Table 7-46. _MVECTBGRNDACTIVE Register Field Descriptions....................................................................................... 1013
Table 7-47. SOFTINTEN Register Field Descriptions............................................................................................................1014
Table 7-48. _MSTSBGRND Register Field Descriptions....................................................................................................... 1016
Table 7-49. _MCTLBGRND Register Field Descriptions....................................................................................................... 1017
Table 7-50. _MVECTBGRND Register Field Descriptions.................................................................................................... 1018
Table 7-51. MIFR Register Field Descriptions....................................................................................................................... 1019
Table 7-52. MIOVF Register Field Descriptions.....................................................................................................................1023
Table 7-53. MIFRC Register Field Descriptions.....................................................................................................................1026
Table 7-54. MICLR Register Field Descriptions.....................................................................................................................1028
Table 7-55. MICLROVF Register Field Descriptions............................................................................................................. 1030
Table 7-56. MIER Register Field Descriptions....................................................................................................................... 1032
Table 7-57. MIRUN Register Field Descriptions.................................................................................................................... 1035
Table 7-58. _MPC Register Field Descriptions...................................................................................................................... 1037
Table 7-59. _MAR0 Register Field Descriptions.................................................................................................................... 1038
Table 7-60. _MAR1 Register Field Descriptions.................................................................................................................... 1039
Table 7-61. _MSTF Register Field Descriptions.................................................................................................................... 1040
Table 7-62. _MR0 Register Field Descriptions...................................................................................................................... 1043
Table 7-63. _MR1 Register Field Descriptions...................................................................................................................... 1044
Table 7-64. _MR2 Register Field Descriptions...................................................................................................................... 1045
Table 7-65. _MR3 Register Field Descriptions...................................................................................................................... 1046
Table 7-66. _MPSACTL Register Field Descriptions............................................................................................................. 1047
Table 7-67. _MPSA1 Register Field Descriptions..................................................................................................................1049
Table 7-68. _MPSA2 Register Field Descriptions..................................................................................................................1050
Table 9-1. DCC Registers to Driverlib Functions................................................................................................................... 1062
Table 9-2. DCC Base Address Table..................................................................................................................................... 1064
Table 9-3. DCC_REGS Registers..........................................................................................................................................1065
Table 9-4. DCC_REGS Access Type Codes......................................................................................................................... 1065
Table 9-5. DCCGCTRL Register Field Descriptions.............................................................................................................. 1066
Table 9-6. DCCCNTSEED0 Register Field Descriptions....................................................................................................... 1067
Table 9-7. DCCVALIDSEED0 Register Field Descriptions.................................................................................................... 1068
Table 9-8. DCCCNTSEED1 Register Field Descriptions....................................................................................................... 1069
Table 9-9. DCCSTATUS Register Field Descriptions.............................................................................................................1070
Table 9-10. DCCCNT0 Register Field Descriptions...............................................................................................................1071
Table 9-11. DCCVALID0 Register Field Descriptions............................................................................................................ 1072
Table 9-12. DCCCNT1 Register Field Descriptions...............................................................................................................1073
Table 9-13. DCCCLKSRC1 Register Field Descriptions........................................................................................................1074
Table 9-14. DCCCLKSRC0 Register Field Descriptions........................................................................................................1075
Table 10-1. GPIO access by different controllers...................................................................................................................1078
Table 10-2. AGPIO Configuration.......................................................................................................................................... 1080
Table 10-3. The Combinations of Use Cases for a Specific Analog Input Pin....................................................................... 1081
Table 10-4. Sampling Period..................................................................................................................................................1084
Table 10-5. Sampling Frequency........................................................................................................................................... 1084
Table 10-6. Case 1: Three-Sample Sampling-Window Width................................................................................................1085
Table 10-7. Case 2: Six-Sample Sampling-Window Width.................................................................................................... 1085
Table 10-8. GPIO Muxed Pins............................................................................................................................................... 1089
Table 10-9. GPIO and Peripheral Muxing.............................................................................................................................. 1094
Table 10-10. Peripheral Muxing (Multiple Pins Assigned)..................................................................................................... 1095
Table 10-11. GPIO Registers to Driverlib Functions.............................................................................................................. 1096
Table 10-12. GPIO Base Address Table................................................................................................................................ 1102
Table 10-13. GPIO_CTRL_REGS Registers..........................................................................................................................1103
Table 10-14. GPIO_CTRL_REGS Access Type Codes......................................................................................................... 1105
Table 10-15. GPACTRL Register Field Descriptions..............................................................................................................1106

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Table 10-16. GPAQSEL1 Register Field Descriptions........................................................................................................... 1107

Table 10-17. GPAQSEL2 Register Field Descriptions............................................................................................................1110
Table 10-18. GPAMUX1 Register Field Descriptions............................................................................................................. 1113
Table 10-19. GPAMUX2 Register Field Descriptions............................................................................................................. 1115
Table 10-20. GPADIR Register Field Descriptions................................................................................................................. 1117
Table 10-21. GPAPUD Register Field Descriptions................................................................................................................1119
Table 10-22. GPAINV Register Field Descriptions................................................................................................................. 1121
Table 10-23. GPAODR Register Field Descriptions............................................................................................................... 1123
Table 10-24. GPAAMSEL Register Field Descriptions...........................................................................................................1125
Table 10-25. GPAGMUX1 Register Field Descriptions.......................................................................................................... 1127
Table 10-26. GPAGMUX2 Register Field Descriptions.......................................................................................................... 1129
Table 10-27. GPACSEL1 Register Field Descriptions............................................................................................................1131
Table 10-28. GPACSEL2 Register Field Descriptions............................................................................................................1132
Table 10-29. GPACSEL3 Register Field Descriptions............................................................................................................1133
Table 10-30. GPACSEL4 Register Field Descriptions............................................................................................................1134
Table 10-31. GPALOCK Register Field Descriptions............................................................................................................. 1135
Table 10-32. GPACR Register Field Descriptions..................................................................................................................1137
Table 10-33. GPBCTRL Register Field Descriptions............................................................................................................. 1139
Table 10-34. GPBQSEL1 Register Field Descriptions........................................................................................................... 1140
Table 10-35. GPBQSEL2 Register Field Descriptions........................................................................................................... 1142
Table 10-36. GPBMUX1 Register Field Descriptions.............................................................................................................1145
Table 10-37. GPBMUX2 Register Field Descriptions.............................................................................................................1146
Table 10-38. GPBDIR Register Field Descriptions.................................................................................................................1148
Table 10-39. GPBPUD Register Field Descriptions............................................................................................................... 1150
Table 10-40. GPBINV Register Field Descriptions.................................................................................................................1152
Table 10-41. GPBODR Register Field Descriptions...............................................................................................................1154
Table 10-42. GPBAMSEL Register Field Descriptions...........................................................................................................1156
Table 10-43. GPBGMUX1 Register Field Descriptions.......................................................................................................... 1158
Table 10-44. GPBGMUX2 Register Field Descriptions.......................................................................................................... 1159
Table 10-45. GPBCSEL1 Register Field Descriptions........................................................................................................... 1161
Table 10-46. GPBCSEL2 Register Field Descriptions........................................................................................................... 1162
Table 10-47. GPBCSEL3 Register Field Descriptions........................................................................................................... 1163
Table 10-48. GPBCSEL4 Register Field Descriptions........................................................................................................... 1164
Table 10-49. GPBLOCK Register Field Descriptions............................................................................................................. 1165
Table 10-50. GPBCR Register Field Descriptions..................................................................................................................1167
Table 10-51. GPCCTRL Register Field Descriptions............................................................................................................. 1169
Table 10-52. GPCQSEL1 Register Field Descriptions........................................................................................................... 1170
Table 10-53. GPCQSEL2 Register Field Descriptions........................................................................................................... 1173
Table 10-54. GPCMUX1 Register Field Descriptions.............................................................................................................1174
Table 10-55. GPCMUX2 Register Field Descriptions.............................................................................................................1176
Table 10-56. GPCDIR Register Field Descriptions................................................................................................................ 1177
Table 10-57. GPCPUD Register Field Descriptions............................................................................................................... 1179
Table 10-58. GPCINV Register Field Descriptions.................................................................................................................1181
Table 10-59. GPCODR Register Field Descriptions...............................................................................................................1183
Table 10-60. GPCAMSEL Register Field Descriptions.......................................................................................................... 1185
Table 10-61. GPCGMUX1 Register Field Descriptions..........................................................................................................1187
Table 10-62. GPCGMUX2 Register Field Descriptions..........................................................................................................1189
Table 10-63. GPCCSEL1 Register Field Descriptions........................................................................................................... 1190
Table 10-64. GPCCSEL2 Register Field Descriptions........................................................................................................... 1191
Table 10-65. GPCCSEL3 Register Field Descriptions........................................................................................................... 1192
Table 10-66. GPCLOCK Register Field Descriptions.............................................................................................................1193
Table 10-67. GPCCR Register Field Descriptions................................................................................................................. 1195
Table 10-68. GPGCTRL Register Field Descriptions............................................................................................................. 1197
Table 10-69. GPGQSEL2 Register Field Descriptions...........................................................................................................1198
Table 10-70. GPGMUX2 Register Field Descriptions............................................................................................................ 1200
Table 10-71. GPGDIR Register Field Descriptions................................................................................................................1202
Table 10-72. GPGPUD Register Field Descriptions.............................................................................................................. 1204
Table 10-73. GPGINV Register Field Descriptions................................................................................................................ 1206
Table 10-74. GPGODR Register Field Descriptions.............................................................................................................. 1208
Table 10-75. GPGAMSEL Register Field Descriptions..........................................................................................................1210
Table 10-76. GPGGMUX2 Register Field Descriptions......................................................................................................... 1213

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Table 10-77. GPGCSEL3 Register Field Descriptions...........................................................................................................1215

Table 10-78. GPGLOCK Register Field Descriptions............................................................................................................ 1216
Table 10-79. GPGCR Register Field Descriptions.................................................................................................................1218
Table 10-80. GPHCTRL Register Field Descriptions.............................................................................................................1220
Table 10-81. GPHQSEL1 Register Field Descriptions...........................................................................................................1221
Table 10-82. GPHQSEL2 Register Field Descriptions...........................................................................................................1223
Table 10-83. GPHMUX1 Register Field Descriptions............................................................................................................ 1225
Table 10-84. GPHMUX2 Register Field Descriptions............................................................................................................ 1227
Table 10-85. GPHDIR Register Field Descriptions................................................................................................................ 1229
Table 10-86. GPHPUD Register Field Descriptions...............................................................................................................1231
Table 10-87. GPHINV Register Field Descriptions................................................................................................................ 1237
Table 10-88. GPHODR Register Field Descriptions.............................................................................................................. 1241
Table 10-89. GPHAMSEL Register Field Descriptions.......................................................................................................... 1243
Table 10-90. GPHGMUX1 Register Field Descriptions......................................................................................................... 1249
Table 10-91. GPHGMUX2 Register Field Descriptions......................................................................................................... 1251
Table 10-92. GPHCSEL1 Register Field Descriptions...........................................................................................................1253
Table 10-93. GPHCSEL2 Register Field Descriptions...........................................................................................................1254
Table 10-94. GPHCSEL3 Register Field Descriptions...........................................................................................................1255
Table 10-95. GPHCSEL4 Register Field Descriptions...........................................................................................................1256
Table 10-96. GPHLOCK Register Field Descriptions............................................................................................................ 1257
Table 10-97. GPHCR Register Field Descriptions................................................................................................................. 1261
Table 10-98. GPIO_DATA_REGS Registers..........................................................................................................................1264
Table 10-99. GPIO_DATA_REGS Access Type Codes......................................................................................................... 1264
Table 10-100. GPADAT Register Field Descriptions..............................................................................................................1266
Table 10-101. GPASET Register Field Descriptions..............................................................................................................1268
Table 10-102. GPACLEAR Register Field Descriptions.........................................................................................................1270
Table 10-103. GPATOGGLE Register Field Descriptions...................................................................................................... 1272
Table 10-104. GPBDAT Register Field Descriptions..............................................................................................................1274
Table 10-105. GPBSET Register Field Descriptions............................................................................................................. 1276
Table 10-106. GPBCLEAR Register Field Descriptions........................................................................................................ 1278
Table 10-107. GPBTOGGLE Register Field Descriptions......................................................................................................1280
Table 10-108. GPCDAT Register Field Descriptions............................................................................................................. 1282
Table 10-109. GPCSET Register Field Descriptions............................................................................................................. 1284
Table 10-110. GPCCLEAR Register Field Descriptions.........................................................................................................1286
Table 10-111. GPCTOGGLE Register Field Descriptions......................................................................................................1288
Table 10-112. GPGDAT Register Field Descriptions............................................................................................................. 1290
Table 10-113. GPGSET Register Field Descriptions............................................................................................................. 1292
Table 10-114. GPGCLEAR Register Field Descriptions........................................................................................................ 1294
Table 10-115. GPGTOGGLE Register Field Descriptions..................................................................................................... 1296
Table 10-116. GPHDAT Register Field Descriptions..............................................................................................................1298
Table 10-117. GPHSET Register Field Descriptions..............................................................................................................1305
Table 10-118. GPHCLEAR Register Field Descriptions.........................................................................................................1307
Table 10-119. GPHTOGGLE Register Field Descriptions......................................................................................................1309
Table 10-120. GPIO_DATA_READ_REGS Registers............................................................................................................1311
Table 10-121. GPIO_DATA_READ_REGS Access Type Codes........................................................................................... 1311
Table 10-122. GPADAT_R Register Field Descriptions......................................................................................................... 1312
Table 10-123. GPBDAT_R Register Field Descriptions......................................................................................................... 1313
Table 10-124. GPCDAT_R Register Field Descriptions.........................................................................................................1314
Table 10-125. GPGDAT_R Register Field Descriptions.........................................................................................................1315
Table 10-126. GPHDAT_R Register Field Descriptions.........................................................................................................1316
Table 11-1. Input X-BAR Destinations....................................................................................................................................1320
Table 11-2. CLB Input X-BAR Destinations............................................................................................................................1321
Table 11-3. EPWM X-BAR Mux Configuration Table............................................................................................................. 1323
Table 11-4. CLB X-BAR Mux Configuration Table..................................................................................................................1326
Table 11-5. Output X-BAR Mux Configuration Table..............................................................................................................1328
Table 11-6. INPUTXBAR Registers to Driverlib Functions.....................................................................................................1331
Table 11-7. EPWMXBAR Registers to Driverlib Functions.................................................................................................... 1331
Table 11-8. CLBXBAR Registers to Driverlib Functions.........................................................................................................1333
Table 11-9. OUTPUTXBAR Registers to Driverlib Functions.................................................................................................1334
Table 11-10. XBAR Registers to Driverlib Functions..............................................................................................................1335
Table 11-11. XBAR Base Address Table................................................................................................................................1336

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Table 11-12. INPUT_XBAR_REGS Registers....................................................................................................................... 1337

Table 11-13. INPUT_XBAR_REGS Access Type Codes.......................................................................................................1337
Table 11-14. INPUT1SELECT Register Field Descriptions....................................................................................................1338
Table 11-15. INPUT2SELECT Register Field Descriptions....................................................................................................1339
Table 11-16. INPUT3SELECT Register Field Descriptions....................................................................................................1340
Table 11-17. INPUT4SELECT Register Field Descriptions....................................................................................................1341
Table 11-18. INPUT5SELECT Register Field Descriptions....................................................................................................1342
Table 11-19. INPUT6SELECT Register Field Descriptions....................................................................................................1343
Table 11-20. INPUT7SELECT Register Field Descriptions....................................................................................................1344
Table 11-21. INPUT8SELECT Register Field Descriptions....................................................................................................1345
Table 11-22. INPUT9SELECT Register Field Descriptions....................................................................................................1346
Table 11-23. INPUT10SELECT Register Field Descriptions..................................................................................................1347
Table 11-24. INPUT11SELECT Register Field Descriptions..................................................................................................1348
Table 11-25. INPUT12SELECT Register Field Descriptions..................................................................................................1349
Table 11-26. INPUT13SELECT Register Field Descriptions..................................................................................................1350
Table 11-27. INPUT14SELECT Register Field Descriptions..................................................................................................1351
Table 11-28. INPUT15SELECT Register Field Descriptions..................................................................................................1352
Table 11-29. INPUT16SELECT Register Field Descriptions..................................................................................................1353
Table 11-30. INPUTSELECTLOCK Register Field Descriptions............................................................................................1354
Table 11-31. XBAR_REGS Registers.................................................................................................................................... 1356
Table 11-32. XBAR_REGS Access Type Codes....................................................................................................................1356
Table 11-33. XBARFLG1 Register Field Descriptions............................................................................................................1357
Table 11-34. XBARFLG2 Register Field Descriptions............................................................................................................1360
Table 11-35. XBARFLG3 Register Field Descriptions............................................................................................................1365
Table 11-36. XBARFLG4 Register Field Descriptions............................................................................................................1368
Table 11-37. XBARCLR1 Register Field Descriptions........................................................................................................... 1371
Table 11-38. XBARCLR2 Register Field Descriptions........................................................................................................... 1373
Table 11-39. XBARCLR3 Register Field Descriptions........................................................................................................... 1376
Table 11-40. XBARCLR4 Register Field Descriptions........................................................................................................... 1378
Table 11-41. EPWM_XBAR_REGS Registers....................................................................................................................... 1380
Table 11-42. EPWM_XBAR_REGS Access Type Codes...................................................................................................... 1380
Table 11-43. TRIP4MUX0TO15CFG Register Field Descriptions..........................................................................................1382
Table 11-44. TRIP4MUX16TO31CFG Register Field Descriptions........................................................................................1385
Table 11-45. TRIP5MUX0TO15CFG Register Field Descriptions..........................................................................................1388
Table 11-46. TRIP5MUX16TO31CFG Register Field Descriptions........................................................................................1391
Table 11-47. TRIP7MUX0TO15CFG Register Field Descriptions..........................................................................................1394
Table 11-48. TRIP7MUX16TO31CFG Register Field Descriptions........................................................................................1397
Table 11-49. TRIP8MUX0TO15CFG Register Field Descriptions..........................................................................................1400
Table 11-50. TRIP8MUX16TO31CFG Register Field Descriptions........................................................................................1403
Table 11-51. TRIP9MUX0TO15CFG Register Field Descriptions..........................................................................................1406
Table 11-52. TRIP9MUX16TO31CFG Register Field Descriptions........................................................................................1409
Table 11-53. TRIP10MUX0TO15CFG Register Field Descriptions........................................................................................1412
Table 11-54. TRIP10MUX16TO31CFG Register Field Descriptions......................................................................................1415
Table 11-55. TRIP11MUX0TO15CFG Register Field Descriptions........................................................................................1418
Table 11-56. TRIP11MUX16TO31CFG Register Field Descriptions......................................................................................1421
Table 11-57. TRIP12MUX0TO15CFG Register Field Descriptions........................................................................................1424
Table 11-58. TRIP12MUX16TO31CFG Register Field Descriptions......................................................................................1427
Table 11-59. TRIP4MUXENABLE Register Field Descriptions.............................................................................................. 1430
Table 11-60. TRIP5MUXENABLE Register Field Descriptions.............................................................................................. 1435
Table 11-61. TRIP7MUXENABLE Register Field Descriptions.............................................................................................. 1440
Table 11-62. TRIP8MUXENABLE Register Field Descriptions.............................................................................................. 1445
Table 11-63. TRIP9MUXENABLE Register Field Descriptions.............................................................................................. 1450
Table 11-64. TRIP10MUXENABLE Register Field Descriptions............................................................................................ 1455
Table 11-65. TRIP11MUXENABLE Register Field Descriptions............................................................................................ 1460
Table 11-66. TRIP12MUXENABLE Register Field Descriptions............................................................................................ 1465
Table 11-67. TRIPOUTINV Register Field Descriptions.........................................................................................................1470
Table 11-68. TRIPLOCK Register Field Descriptions............................................................................................................ 1472
Table 11-69. CLB_XBAR_REGS Registers........................................................................................................................... 1473
Table 11-70. CLB_XBAR_REGS Access Type Codes...........................................................................................................1473
Table 11-71. AUXSIG0MUX0TO15CFG Register Field Descriptions.................................................................................... 1475
Table 11-72. AUXSIG0MUX16TO31CFG Register Field Descriptions.................................................................................. 1478

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Table 11-73. AUXSIG1MUX0TO15CFG Register Field Descriptions.................................................................................... 1481

Table 11-74. AUXSIG1MUX16TO31CFG Register Field Descriptions.................................................................................. 1484
Table 11-75. AUXSIG2MUX0TO15CFG Register Field Descriptions.................................................................................... 1487
Table 11-76. AUXSIG2MUX16TO31CFG Register Field Descriptions.................................................................................. 1490
Table 11-77. AUXSIG3MUX0TO15CFG Register Field Descriptions.................................................................................... 1493
Table 11-78. AUXSIG3MUX16TO31CFG Register Field Descriptions.................................................................................. 1496
Table 11-79. AUXSIG4MUX0TO15CFG Register Field Descriptions.................................................................................... 1499
Table 11-80. AUXSIG4MUX16TO31CFG Register Field Descriptions.................................................................................. 1502
Table 11-81. AUXSIG5MUX0TO15CFG Register Field Descriptions.................................................................................... 1505
Table 11-82. AUXSIG5MUX16TO31CFG Register Field Descriptions.................................................................................. 1508
Table 11-83. AUXSIG6MUX0TO15CFG Register Field Descriptions.................................................................................... 1511
Table 11-84. AUXSIG6MUX16TO31CFG Register Field Descriptions.................................................................................. 1514
Table 11-85. AUXSIG7MUX0TO15CFG Register Field Descriptions.................................................................................... 1517
Table 11-86. AUXSIG7MUX16TO31CFG Register Field Descriptions.................................................................................. 1520
Table 11-87. AUXSIG0MUXENABLE Register Field Descriptions.........................................................................................1523
Table 11-88. AUXSIG1MUXENABLE Register Field Descriptions.........................................................................................1528
Table 11-89. AUXSIG2MUXENABLE Register Field Descriptions.........................................................................................1533
Table 11-90. AUXSIG3MUXENABLE Register Field Descriptions.........................................................................................1538
Table 11-91. AUXSIG4MUXENABLE Register Field Descriptions.........................................................................................1543
Table 11-92. AUXSIG5MUXENABLE Register Field Descriptions.........................................................................................1548
Table 11-93. AUXSIG6MUXENABLE Register Field Descriptions.........................................................................................1553
Table 11-94. AUXSIG7MUXENABLE Register Field Descriptions.........................................................................................1558
Table 11-95. AUXSIGOUTINV Register Field Descriptions................................................................................................... 1563
Table 11-96. AUXSIGLOCK Register Field Descriptions....................................................................................................... 1565
Table 11-97. OUTPUT_XBAR_REGS Registers................................................................................................................... 1566
Table 11-98. OUTPUT_XBAR_REGS Access Type Codes...................................................................................................1566
Table 11-99. OUTPUT1MUX0TO15CFG Register Field Descriptions................................................................................... 1568
Table 11-100. OUTPUT1MUX16TO31CFG Register Field Descriptions............................................................................... 1571
Table 11-101. OUTPUT2MUX0TO15CFG Register Field Descriptions................................................................................. 1574
Table 11-102. OUTPUT2MUX16TO31CFG Register Field Descriptions............................................................................... 1577
Table 11-103. OUTPUT3MUX0TO15CFG Register Field Descriptions................................................................................. 1580
Table 11-104. OUTPUT3MUX16TO31CFG Register Field Descriptions............................................................................... 1583
Table 11-105. OUTPUT4MUX0TO15CFG Register Field Descriptions................................................................................. 1586
Table 11-106. OUTPUT4MUX16TO31CFG Register Field Descriptions............................................................................... 1589
Table 11-107. OUTPUT5MUX0TO15CFG Register Field Descriptions................................................................................. 1592
Table 11-108. OUTPUT5MUX16TO31CFG Register Field Descriptions............................................................................... 1595
Table 11-109. OUTPUT6MUX0TO15CFG Register Field Descriptions................................................................................. 1598
Table 11-110. OUTPUT6MUX16TO31CFG Register Field Descriptions............................................................................... 1601
Table 11-111. OUTPUT7MUX0TO15CFG Register Field Descriptions..................................................................................1604
Table 11-112. OUTPUT7MUX16TO31CFG Register Field Descriptions............................................................................... 1607
Table 11-113. OUTPUT8MUX0TO15CFG Register Field Descriptions................................................................................. 1610
Table 11-114. OUTPUT8MUX16TO31CFG Register Field Descriptions............................................................................... 1613
Table 11-115. OUTPUT1MUXENABLE Register Field Descriptions......................................................................................1616
Table 11-116. OUTPUT2MUXENABLE Register Field Descriptions......................................................................................1621
Table 11-117. OUTPUT3MUXENABLE Register Field Descriptions......................................................................................1626
Table 11-118. OUTPUT4MUXENABLE Register Field Descriptions......................................................................................1631
Table 11-119. OUTPUT5MUXENABLE Register Field Descriptions......................................................................................1636
Table 11-120. OUTPUT6MUXENABLE Register Field Descriptions..................................................................................... 1641
Table 11-121. OUTPUT7MUXENABLE Register Field Descriptions..................................................................................... 1646
Table 11-122. OUTPUT8MUXENABLE Register Field Descriptions..................................................................................... 1651
Table 11-123. OUTPUTLATCH Register Field Descriptions.................................................................................................. 1656
Table 11-124. OUTPUTLATCHCLR Register Field Descriptions...........................................................................................1658
Table 11-125. OUTPUTLATCHFRC Register Field Descriptions...........................................................................................1660
Table 11-126. OUTPUTLATCHENABLE Register Field Descriptions....................................................................................1662
Table 11-127. OUTPUTINV Register Field Descriptions........................................................................................................1664
Table 11-128. OUTPUTLOCK Register Field Descriptions....................................................................................................1666
Table 11-129. OUTPUT_XBAR_REGS Registers................................................................................................................. 1667
Table 11-130. OUTPUT_XBAR_REGS Access Type Codes.................................................................................................1667
Table 11-131. OUTPUT1MUX0TO15CFG Register Field Descriptions................................................................................. 1669
Table 11-132. OUTPUT1MUX16TO31CFG Register Field Descriptions............................................................................... 1672
Table 11-133. OUTPUT2MUX0TO15CFG Register Field Descriptions................................................................................. 1675

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Table 11-134. OUTPUT2MUX16TO31CFG Register Field Descriptions............................................................................... 1678

Table 11-135. OUTPUT3MUX0TO15CFG Register Field Descriptions................................................................................. 1681
Table 11-136. OUTPUT3MUX16TO31CFG Register Field Descriptions............................................................................... 1684
Table 11-137. OUTPUT4MUX0TO15CFG Register Field Descriptions................................................................................. 1687
Table 11-138. OUTPUT4MUX16TO31CFG Register Field Descriptions............................................................................... 1690
Table 11-139. OUTPUT5MUX0TO15CFG Register Field Descriptions................................................................................. 1693
Table 11-140. OUTPUT5MUX16TO31CFG Register Field Descriptions............................................................................... 1696
Table 11-141. OUTPUT6MUX0TO15CFG Register Field Descriptions................................................................................. 1699
Table 11-142. OUTPUT6MUX16TO31CFG Register Field Descriptions............................................................................... 1702
Table 11-143. OUTPUT7MUX0TO15CFG Register Field Descriptions................................................................................. 1705
Table 11-144. OUTPUT7MUX16TO31CFG Register Field Descriptions............................................................................... 1708
Table 11-145. OUTPUT8MUX0TO15CFG Register Field Descriptions................................................................................. 1711
Table 11-146. OUTPUT8MUX16TO31CFG Register Field Descriptions............................................................................... 1714
Table 11-147. OUTPUT1MUXENABLE Register Field Descriptions..................................................................................... 1717
Table 11-148. OUTPUT2MUXENABLE Register Field Descriptions..................................................................................... 1722
Table 11-149. OUTPUT3MUXENABLE Register Field Descriptions..................................................................................... 1727
Table 11-150. OUTPUT4MUXENABLE Register Field Descriptions..................................................................................... 1732
Table 11-151. OUTPUT5MUXENABLE Register Field Descriptions..................................................................................... 1737
Table 11-152. OUTPUT6MUXENABLE Register Field Descriptions..................................................................................... 1742
Table 11-153. OUTPUT7MUXENABLE Register Field Descriptions..................................................................................... 1747
Table 11-154. OUTPUT8MUXENABLE Register Field Descriptions..................................................................................... 1752
Table 11-155. OUTPUTLATCH Register Field Descriptions.................................................................................................. 1757
Table 11-156. OUTPUTLATCHCLR Register Field Descriptions...........................................................................................1759
Table 11-157. OUTPUTLATCHFRC Register Field Descriptions...........................................................................................1761
Table 11-158. OUTPUTLATCHENABLE Register Field Descriptions....................................................................................1763
Table 11-159. OUTPUTINV Register Field Descriptions........................................................................................................1765
Table 11-160. OUTPUTLOCK Register Field Descriptions....................................................................................................1767
Table 12-1. DMA Trigger Source Options.............................................................................................................................. 1773
Table 12-2. BURSTSIZE versus DATASIZE Behavior........................................................................................................... 1778
Table 12-3. DMA Registers to Driverlib Functions................................................................................................................. 1786
Table 12-4. DMA Base Address Table................................................................................................................................... 1788
Table 12-5. DMA_REGS Registers........................................................................................................................................1789
Table 12-6. DMA_REGS Access Type Codes....................................................................................................................... 1789
Table 12-7. DMACTRL Register Field Descriptions...............................................................................................................1790
Table 12-8. DEBUGCTRL Register Field Descriptions..........................................................................................................1791
Table 12-9. PRIORITYCTRL1 Register Field Descriptions....................................................................................................1792
Table 12-10. PRIORITYSTAT Register Field Descriptions.................................................................................................... 1793
Table 12-11. DMA_CH_REGS Registers...............................................................................................................................1794
Table 12-12. DMA_CH_REGS Access Type Codes..............................................................................................................1794
Table 12-13. MODE Register Field Descriptions................................................................................................................... 1795
Table 12-14. CONTROL Register Field Descriptions............................................................................................................ 1797
Table 12-15. BURST_SIZE Register Field Descriptions........................................................................................................1799
Table 12-16. BURST_COUNT Register Field Descriptions................................................................................................... 1800
Table 12-17. SRC_BURST_STEP Register Field Descriptions.............................................................................................1801
Table 12-18. DST_BURST_STEP Register Field Descriptions............................................................................................. 1802
Table 12-19. TRANSFER_SIZE Register Field Descriptions.................................................................................................1803
Table 12-20. TRANSFER_COUNT Register Field Descriptions............................................................................................1804
Table 12-21. SRC_TRANSFER_STEP Register Field Descriptions......................................................................................1805
Table 12-22. DST_TRANSFER_STEP Register Field Descriptions...................................................................................... 1806
Table 12-23. SRC_WRAP_SIZE Register Field Descriptions................................................................................................1807
Table 12-24. SRC_WRAP_COUNT Register Field Descriptions...........................................................................................1808
Table 12-25. SRC_WRAP_STEP Register Field Descriptions.............................................................................................. 1809
Table 12-26. DST_WRAP_SIZE Register Field Descriptions................................................................................................ 1810
Table 12-27. DST_WRAP_COUNT Register Field Descriptions............................................................................................1811
Table 12-28. DST_WRAP_STEP Register Field Descriptions...............................................................................................1812
Table 12-29. SRC_BEG_ADDR_SHADOW Register Field Descriptions.............................................................................. 1813
Table 12-30. SRC_ADDR_SHADOW Register Field Descriptions........................................................................................ 1814
Table 12-31. SRC_BEG_ADDR_ACTIVE Register Field Descriptions..................................................................................1815
Table 12-32. SRC_ADDR_ACTIVE Register Field Descriptions........................................................................................... 1816
Table 12-33. DST_BEG_ADDR_SHADOW Register Field Descriptions...............................................................................1817
Table 12-34. DST_ADDR_SHADOW Register Field Descriptions........................................................................................ 1818

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Table 12-35. DST_BEG_ADDR_ACTIVE Register Field Descriptions.................................................................................. 1819

Table 12-36. DST_ADDR_ACTIVE Register Field Descriptions............................................................................................1820
Table 13-1. Event Selector Mux Signals................................................................................................................................ 1827
Table 13-2. CPU Interfaces Monitored by CRC Units............................................................................................................1834
Table 13-3. Event Selector Mux Signals................................................................................................................................ 1838
Table 13-4. Trace Memory Entry Bit Fields............................................................................................................................1842
Table 13-5. ERAD Registers to Driverlib Functions............................................................................................................... 1845
Table 13-6. ERAD Base Address Table................................................................................................................................. 1855
Table 13-7. ERAD_GLOBAL_REGS Registers..................................................................................................................... 1856
Table 13-8. ERAD_GLOBAL_REGS Access Type Codes.....................................................................................................1856
Table 13-9. GLBL_EVENT_STAT Register Field Descriptions.............................................................................................. 1857
Table 13-10. GLBL_HALT_STAT Register Field Descriptions............................................................................................... 1859
Table 13-11. GLBL_ENABLE Register Field Descriptions..................................................................................................... 1861
Table 13-12. GLBL_CTM_RESET Register Field Descriptions............................................................................................. 1863
Table 13-13. GLBL_NMI_CTL Register Field Descriptions................................................................................................... 1864
Table 13-14. GLBL_OWNER Register Field Descriptions..................................................................................................... 1866
Table 13-15. GLBL_EVENT_AND_MASK Register Field Descriptions................................................................................. 1867
Table 13-16. GLBL_EVENT_OR_MASK Register Field Descriptions................................................................................... 1872
Table 13-17. GLBL_AND_EVENT_INT_MASK Register Field Descriptions......................................................................... 1877
Table 13-18. GLBL_OR_EVENT_INT_MASK Register Field Descriptions........................................................................... 1878
Table 13-19. ERAD_HWBP_REGS Registers.......................................................................................................................1879
Table 13-20. ERAD_HWBP_REGS Access Type Codes...................................................................................................... 1879
Table 13-21. HWBP_MASK Register Field Descriptions....................................................................................................... 1880
Table 13-22. HWBP_REF Register Field Descriptions.......................................................................................................... 1881
Table 13-23. HWBP_CLEAR Register Field Descriptions..................................................................................................... 1882
Table 13-24. HWBP_CNTL Register Field Descriptions........................................................................................................1883
Table 13-25. HWBP_STATUS Register Field Descriptions....................................................................................................1885
Table 13-26. ERAD_COUNTER_REGS Registers................................................................................................................1886
Table 13-27. ERAD_COUNTER_REGS Access Type Codes............................................................................................... 1886
Table 13-28. CTM_CNTL Register Field Descriptions...........................................................................................................1887
Table 13-29. CTM_STATUS Register Field Descriptions.......................................................................................................1889
Table 13-30. CTM_REF Register Field Descriptions............................................................................................................. 1890
Table 13-31. CTM_COUNT Register Field Descriptions....................................................................................................... 1891
Table 13-32. CTM_MAX_COUNT Register Field Descriptions..............................................................................................1892
Table 13-33. CTM_INPUT_SEL Register Field Descriptions.................................................................................................1893
Table 13-34. CTM_CLEAR Register Field Descriptions........................................................................................................ 1894
Table 13-35. CTM_INPUT_SEL_2 Register Field Descriptions.............................................................................................1895
Table 13-36. CTM_INPUT_COND Register Field Descriptions.............................................................................................1896
Table 13-37. ERAD_CRC_GLOBAL_REGS Registers......................................................................................................... 1897
Table 13-38. ERAD_CRC_GLOBAL_REGS Access Type Codes.........................................................................................1897
Table 13-39. CRC_GLOBAL_CTRL Register Field Descriptions.......................................................................................... 1898
Table 13-40. ERAD_CRC_REGS Registers..........................................................................................................................1900
Table 13-41. ERAD_CRC_REGS Access Type Codes......................................................................................................... 1900
Table 13-42. CRC_CURRENT Register Field Descriptions...................................................................................................1901
Table 13-43. CRC_SEED Register Field Descriptions.......................................................................................................... 1902
Table 13-44. CRC_QUALIFIER Register Field Descriptions................................................................................................. 1903
Table 13-45. PCTRACE_REGS Registers............................................................................................................................ 1904
Table 13-46. PCTRACE_REGS Access Type Codes............................................................................................................1904
Table 13-47. PCTRACE_GLOBAL Register Field Descriptions............................................................................................ 1905
Table 13-48. PCTRACE_BUFFER Register Field Descriptions............................................................................................ 1906
Table 13-49. PCTRACE_QUAL1 Register Field Descriptions............................................................................................... 1907
Table 13-50. PCTRACE_QUAL2 Register Field Descriptions............................................................................................... 1908
Table 13-51. PCTRACE_LOGPC_SOFTENABLE Register Field Descriptions.................................................................... 1909
Table 13-52. PCTRACE_LOGPC_SOFTDISABLE Register Field Descriptions................................................................... 1910
Table 13-53. PCTRACE_BUFFER_REGS Registers............................................................................................................ 1911
Table 13-54. PCTRACE_BUFFER_REGS Access Type Codes............................................................................................1911
Table 13-55. PCTRACE_BUFFER_BASE_y Register Field Descriptions............................................................................. 1912
Table 14-1. CMPSS Input Mux Options................................................................................................................................. 1918
Table 14-2. AGPIO Configuration.......................................................................................................................................... 1919
Table 14-3. The Combinations of Use Cases for a Specific Analog Input Pin....................................................................... 1921
Table 14-4. Analog Pins and Internal Connections................................................................................................................1922

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Table 14-5. Analog Signal Descriptions................................................................................................................................. 1924

Table 14-6. Reference Summary........................................................................................................................................... 1925
Table 14-7. ASYSCTL Registers to Driverlib Functions.........................................................................................................1926
Table 14-8. ASBSYS Base Address Table.............................................................................................................................1928
Table 14-9. ANALOG_SUBSYS_REGS Registers................................................................................................................ 1929
Table 14-10. ANALOG_SUBSYS_REGS Access Type Codes............................................................................................. 1929
Table 14-11. ADCOSDETECT Register Field Descriptions................................................................................................... 1931
Table 14-12. REFCONFIGB Register Field Descriptions...................................................................................................... 1932
Table 14-13. INTERNALTESTCTL Register Field Descriptions.............................................................................................1934
Table 14-14. CONFIGLOCK Register Field Descriptions...................................................................................................... 1936
Table 14-15. TSNSCTL Register Field Descriptions..............................................................................................................1937
Table 14-16. ANAREFPCTL Register Field Descriptions...................................................................................................... 1938
Table 14-17. ANAREFNCTL Register Field Descriptions...................................................................................................... 1940
Table 14-18. VMONCTL Register Field Descriptions............................................................................................................ 1941
Table 14-19. CMPHPMXSEL Register Field Descriptions.....................................................................................................1942
Table 14-20. CMPLPMXSEL Register Field Descriptions..................................................................................................... 1943
Table 14-21. CMPHNMXSEL Register Field Descriptions.....................................................................................................1944
Table 14-22. CMPLNMXSEL Register Field Descriptions..................................................................................................... 1945
Table 14-23. ADCDACLOOPBACK Register Field Descriptions........................................................................................... 1946
Table 14-24. CMPSSCTL Register Field Descriptions.......................................................................................................... 1948
Table 14-25. CMPSSDACBUFCONFIG Register Field Descriptions.................................................................................... 1949
Table 14-26. LOCK Register Field Descriptions.................................................................................................................... 1950
Table 14-27. AGPIOCTRLA Register Field Descriptions.......................................................................................................1952
Table 14-28. AGPIOCTRLB Register Field Descriptions.......................................................................................................1954
Table 14-29. AGPIOCTRLG Register Field Descriptions...................................................................................................... 1956
Table 14-30. AGPIOCTRLH Register Field Descriptions.......................................................................................................1958
Table 14-31. GPIOINENACTRL Register Field Descriptions.................................................................................................1960
Table 14-32. IO_DRVSEL Register Field Descriptions.......................................................................................................... 1961
Table 14-33. IO_MODESEL Register Field Descriptions.......................................................................................................1962
Table 14-34. ADCSOCFRCGB Register Field Descriptions.................................................................................................. 1963
Table 14-35. ADCSOCFRCGBSEL Register Field Descriptions........................................................................................... 1965
Table 15-1. ADC Options and Configuration Levels.............................................................................................................. 1970
Table 15-2. Analog to 12-bit Digital Formulas........................................................................................................................1972
Table 15-3. 12-Bit Digital-to-Analog Formulas....................................................................................................................... 1972
Table 15-4. Channel Selection of Input Pins..........................................................................................................................1984
Table 15-5. Example Requirements for Multiple Signal Sampling......................................................................................... 1992
Table 15-6. Example Connections for Multiple Signal Sampling........................................................................................... 1992
Table 15-7. DETECTCFG Settings........................................................................................................................................ 2008
Table 15-8. ADC Timing Parameter Descriptions.................................................................................................................. 2011
Table 15-9. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 0............................................................................ 2014
Table 15-10. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 1.......................................................................... 2014
Table 15-11. PPB Result Timings (One PPB per SOC)......................................................................................................... 2016
Table 15-12. PPB Result Timings (Multiple PPBs Configured to Same SOC).......................................................................2016
Table 15-13. ADC Registers to Driverlib Functions............................................................................................................... 2026
Table 15-14. ADC Base Address Table................................................................................................................................. 2039
Table 15-15. ADC_RESULT_REGS Registers...................................................................................................................... 2040
Table 15-16. ADC_RESULT_REGS Access Type Codes......................................................................................................2041
Table 15-17. ADCRESULT0 Register Field Descriptions.......................................................................................................2042
Table 15-18. ADCRESULT1 Register Field Descriptions.......................................................................................................2043
Table 15-19. ADCRESULT2 Register Field Descriptions.......................................................................................................2044
Table 15-20. ADCRESULT3 Register Field Descriptions.......................................................................................................2045
Table 15-21. ADCRESULT4 Register Field Descriptions.......................................................................................................2046
Table 15-22. ADCRESULT5 Register Field Descriptions.......................................................................................................2047
Table 15-23. ADCRESULT6 Register Field Descriptions.......................................................................................................2048
Table 15-24. ADCRESULT7 Register Field Descriptions.......................................................................................................2049
Table 15-25. ADCRESULT8 Register Field Descriptions.......................................................................................................2050
Table 15-26. ADCRESULT9 Register Field Descriptions.......................................................................................................2051
Table 15-27. ADCRESULT10 Register Field Descriptions.....................................................................................................2052
Table 15-28. ADCRESULT11 Register Field Descriptions.....................................................................................................2053
Table 15-29. ADCRESULT12 Register Field Descriptions.....................................................................................................2054
Table 15-30. ADCRESULT13 Register Field Descriptions.....................................................................................................2055

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Table 15-31. ADCRESULT14 Register Field Descriptions.....................................................................................................2056

Table 15-32. ADCRESULT15 Register Field Descriptions.....................................................................................................2057
Table 15-33. ADCPPB1RESULT Register Field Descriptions............................................................................................... 2058
Table 15-34. ADCPPB2RESULT Register Field Descriptions............................................................................................... 2059
Table 15-35. ADCPPB3RESULT Register Field Descriptions............................................................................................... 2060
Table 15-36. ADCPPB4RESULT Register Field Descriptions............................................................................................... 2061
Table 15-37. ADCPPB1SUM Register Field Descriptions..................................................................................................... 2062
Table 15-38. ADCPPB1COUNT Register Field Descriptions................................................................................................ 2063
Table 15-39. ADCPPB2SUM Register Field Descriptions..................................................................................................... 2064
Table 15-40. ADCPPB2COUNT Register Field Descriptions................................................................................................ 2065
Table 15-41. ADCPPB3SUM Register Field Descriptions..................................................................................................... 2066
Table 15-42. ADCPPB3COUNT Register Field Descriptions................................................................................................ 2067
Table 15-43. ADCPPB4SUM Register Field Descriptions..................................................................................................... 2068
Table 15-44. ADCPPB4COUNT Register Field Descriptions................................................................................................ 2069
Table 15-45. ADCPPB1MAX Register Field Descriptions..................................................................................................... 2070
Table 15-46. ADCPPB1MAXI Register Field Descriptions.................................................................................................... 2071
Table 15-47. ADCPPB1MIN Register Field Descriptions.......................................................................................................2072
Table 15-48. ADCPPB1MINI Register Field Descriptions......................................................................................................2073
Table 15-49. ADCPPB2MAX Register Field Descriptions..................................................................................................... 2074
Table 15-50. ADCPPB2MAXI Register Field Descriptions.................................................................................................... 2075
Table 15-51. ADCPPB2MIN Register Field Descriptions.......................................................................................................2076
Table 15-52. ADCPPB2MINI Register Field Descriptions......................................................................................................2077
Table 15-53. ADCPPB3MAX Register Field Descriptions..................................................................................................... 2078
Table 15-54. ADCPPB3MAXI Register Field Descriptions.................................................................................................... 2079
Table 15-55. ADCPPB3MIN Register Field Descriptions.......................................................................................................2080
Table 15-56. ADCPPB3MINI Register Field Descriptions......................................................................................................2081
Table 15-57. ADCPPB4MAX Register Field Descriptions..................................................................................................... 2082
Table 15-58. ADCPPB4MAXI Register Field Descriptions.................................................................................................... 2083
Table 15-59. ADCPPB4MIN Register Field Descriptions.......................................................................................................2084
Table 15-60. ADCPPB4MINI Register Field Descriptions......................................................................................................2085
Table 15-61. ADC_REGS Registers...................................................................................................................................... 2086
Table 15-62. ADC_REGS Access Type Codes..................................................................................................................... 2089
Table 15-63. ADCCTL1 Register Field Descriptions..............................................................................................................2090
Table 15-64. ADCCTL2 Register Field Descriptions..............................................................................................................2092
Table 15-65. ADCBURSTCTL Register Field Descriptions................................................................................................... 2093
Table 15-66. ADCINTFLG Register Field Descriptions..........................................................................................................2095
Table 15-67. ADCINTFLGCLR Register Field Descriptions.................................................................................................. 2098
Table 15-68. ADCINTOVF Register Field Descriptions......................................................................................................... 2099
Table 15-69. ADCINTOVFCLR Register Field Descriptions.................................................................................................. 2100
Table 15-70. ADCINTSEL1N2 Register Field Descriptions................................................................................................... 2101
Table 15-71. ADCINTSEL3N4 Register Field Descriptions................................................................................................... 2103
Table 15-72. ADCSOCPRICTL Register Field Descriptions..................................................................................................2105
Table 15-73. ADCINTSOCSEL1 Register Field Descriptions................................................................................................ 2107
Table 15-74. ADCSOCFLG1 Register Field Descriptions...................................................................................................... 2110
Table 15-75. ADCSOCFRC1 Register Field Descriptions......................................................................................................2114
Table 15-76. ADCSOCOVF1 Register Field Descriptions......................................................................................................2119
Table 15-77. ADCSOCOVFCLR1 Register Field Descriptions.............................................................................................. 2122
Table 15-78. ADCSOC0CTL Register Field Descriptions......................................................................................................2125
Table 15-79. ADCSOC1CTL Register Field Descriptions......................................................................................................2128
Table 15-80. ADCSOC2CTL Register Field Descriptions......................................................................................................2131
Table 15-81. ADCSOC3CTL Register Field Descriptions......................................................................................................2134
Table 15-82. ADCSOC4CTL Register Field Descriptions......................................................................................................2137
Table 15-83. ADCSOC5CTL Register Field Descriptions......................................................................................................2140
Table 15-84. ADCSOC6CTL Register Field Descriptions......................................................................................................2143
Table 15-85. ADCSOC7CTL Register Field Descriptions......................................................................................................2146
Table 15-86. ADCSOC8CTL Register Field Descriptions......................................................................................................2149
Table 15-87. ADCSOC9CTL Register Field Descriptions......................................................................................................2152
Table 15-88. ADCSOC10CTL Register Field Descriptions....................................................................................................2155
Table 15-89. ADCSOC11CTL Register Field Descriptions.................................................................................................... 2158
Table 15-90. ADCSOC12CTL Register Field Descriptions....................................................................................................2161
Table 15-91. ADCSOC13CTL Register Field Descriptions....................................................................................................2164

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Table 15-92. ADCSOC14CTL Register Field Descriptions....................................................................................................2167

Table 15-93. ADCSOC15CTL Register Field Descriptions....................................................................................................2170
Table 15-94. ADCEVTSTAT Register Field Descriptions.......................................................................................................2173
Table 15-95. ADCEVTCLR Register Field Descriptions........................................................................................................ 2176
Table 15-96. ADCEVTSEL Register Field Descriptions.........................................................................................................2178
Table 15-97. ADCEVTINTSEL Register Field Descriptions...................................................................................................2180
Table 15-98. ADCCOUNTER Register Field Descriptions.....................................................................................................2182
Table 15-99. ADCREV Register Field Descriptions............................................................................................................... 2183
Table 15-100. ADCOFFTRIM Register Field Descriptions.................................................................................................... 2184
Table 15-101. ADCCONFIG2 Register Field Descriptions.................................................................................................... 2185
Table 15-102. ADCPPB1CONFIG Register Field Descriptions............................................................................................. 2186
Table 15-103. ADCPPB1STAMP Register Field Descriptions............................................................................................... 2188
Table 15-104. ADCPPB1OFFCAL Register Field Descriptions............................................................................................. 2189
Table 15-105. ADCPPB1OFFREF Register Field Descriptions.............................................................................................2190
Table 15-106. ADCPPB1TRIPHI Register Field Descriptions............................................................................................... 2191
Table 15-107. ADCPPB1TRIPLO Register Field Descriptions.............................................................................................. 2192
Table 15-108. ADCPPBTRIP1FILCTL Register Field Descriptions....................................................................................... 2193
Table 15-109. ADCPPBTRIP1FILCLKCTL Register Field Descriptions................................................................................ 2194
Table 15-110. ADCPPB2CONFIG Register Field Descriptions..............................................................................................2195
Table 15-111. ADCPPB2STAMP Register Field Descriptions................................................................................................2197
Table 15-112. ADCPPB2OFFCAL Register Field Descriptions............................................................................................. 2198
Table 15-113. ADCPPB2OFFREF Register Field Descriptions............................................................................................. 2199
Table 15-114. ADCPPB2TRIPHI Register Field Descriptions................................................................................................2200
Table 15-115. ADCPPB2TRIPLO Register Field Descriptions...............................................................................................2201
Table 15-116. ADCPPBTRIP2FILCTL Register Field Descriptions....................................................................................... 2202
Table 15-117. ADCPPBTRIP2FILCLKCTL Register Field Descriptions................................................................................ 2203
Table 15-118. ADCPPB3CONFIG Register Field Descriptions..............................................................................................2204
Table 15-119. ADCPPB3STAMP Register Field Descriptions............................................................................................... 2206
Table 15-120. ADCPPB3OFFCAL Register Field Descriptions............................................................................................. 2207
Table 15-121. ADCPPB3OFFREF Register Field Descriptions.............................................................................................2208
Table 15-122. ADCPPB3TRIPHI Register Field Descriptions............................................................................................... 2209
Table 15-123. ADCPPB3TRIPLO Register Field Descriptions.............................................................................................. 2210
Table 15-124. ADCPPBTRIP3FILCTL Register Field Descriptions....................................................................................... 2211
Table 15-125. ADCPPBTRIP3FILCLKCTL Register Field Descriptions................................................................................ 2212
Table 15-126. ADCPPB4CONFIG Register Field Descriptions............................................................................................. 2213
Table 15-127. ADCPPB4STAMP Register Field Descriptions............................................................................................... 2215
Table 15-128. ADCPPB4OFFCAL Register Field Descriptions............................................................................................. 2216
Table 15-129. ADCPPB4OFFREF Register Field Descriptions.............................................................................................2217
Table 15-130. ADCPPB4TRIPHI Register Field Descriptions............................................................................................... 2218
Table 15-131. ADCPPB4TRIPLO Register Field Descriptions.............................................................................................. 2219
Table 15-132. ADCPPBTRIP4FILCTL Register Field Descriptions....................................................................................... 2220
Table 15-133. ADCPPBTRIP4FILCLKCTL Register Field Descriptions................................................................................ 2221
Table 15-134. ADCINTCYCLE Register Field Descriptions...................................................................................................2222
Table 15-135. ADCINLTRIM1 Register Field Descriptions.................................................................................................... 2223
Table 15-136. ADCINLTRIM2 Register Field Descriptions.................................................................................................... 2224
Table 15-137. ADCINLTRIM3 Register Field Descriptions.................................................................................................... 2225
Table 15-138. ADCINLTRIM4 Register Field Descriptions.................................................................................................... 2226
Table 15-139. ADCINLTRIM5 Register Field Descriptions.................................................................................................... 2227
Table 15-140. ADCINLTRIM6 Register Field Descriptions.................................................................................................... 2228
Table 15-141. ADCREV2 Register Field Descriptions........................................................................................................... 2229
Table 15-142. REP1CTL Register Field Descriptions............................................................................................................2230
Table 15-143. REP1N Register Field Descriptions................................................................................................................ 2233
Table 15-144. REP1PHASE Register Field Descriptions...................................................................................................... 2234
Table 15-145. REP1SPREAD Register Field Descriptions....................................................................................................2235
Table 15-146. REP1FRC Register Field Descriptions........................................................................................................... 2236
Table 15-147. REP2CTL Register Field Descriptions............................................................................................................2237
Table 15-148. REP2N Register Field Descriptions................................................................................................................ 2240
Table 15-149. REP2PHASE Register Field Descriptions...................................................................................................... 2241
Table 15-150. REP2SPREAD Register Field Descriptions....................................................................................................2242
Table 15-151. REP2FRC Register Field Descriptions........................................................................................................... 2243
Table 15-152. ADCPPB1LIMIT Register Field Descriptions.................................................................................................. 2244

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Table 15-153. ADCPPBP1PCOUNT Register Field Descriptions..........................................................................................2245

Table 15-154. ADCPPB1CONFIG2 Register Field Descriptions........................................................................................... 2246
Table 15-155. ADCPPB1PSUM Register Field Descriptions.................................................................................................2248
Table 15-156. ADCPPB1PMAX Register Field Descriptions................................................................................................. 2249
Table 15-157. ADCPPB1PMAXI Register Field Descriptions................................................................................................ 2250
Table 15-158. ADCPPB1PMIN Register Field Descriptions.................................................................................................. 2251
Table 15-159. ADCPPB1PMINI Register Field Descriptions................................................................................................. 2252
Table 15-160. ADCPPB1TRIPLO2 Register Field Descriptions............................................................................................ 2253
Table 15-161. ADCPPB2LIMIT Register Field Descriptions.................................................................................................. 2254
Table 15-162. ADCPPBP2PCOUNT Register Field Descriptions..........................................................................................2255
Table 15-163. ADCPPB2CONFIG2 Register Field Descriptions........................................................................................... 2256
Table 15-164. ADCPPB2PSUM Register Field Descriptions.................................................................................................2258
Table 15-165. ADCPPB2PMAX Register Field Descriptions................................................................................................. 2259
Table 15-166. ADCPPB2PMAXI Register Field Descriptions................................................................................................ 2260
Table 15-167. ADCPPB2PMIN Register Field Descriptions.................................................................................................. 2261
Table 15-168. ADCPPB2PMINI Register Field Descriptions................................................................................................. 2262
Table 15-169. ADCPPB2TRIPLO2 Register Field Descriptions............................................................................................ 2263
Table 15-170. ADCPPB3LIMIT Register Field Descriptions.................................................................................................. 2264
Table 15-171. ADCPPBP3PCOUNT Register Field Descriptions..........................................................................................2265
Table 15-172. ADCPPB3CONFIG2 Register Field Descriptions........................................................................................... 2266
Table 15-173. ADCPPB3PSUM Register Field Descriptions.................................................................................................2268
Table 15-174. ADCPPB3PMAX Register Field Descriptions................................................................................................. 2269
Table 15-175. ADCPPB3PMAXI Register Field Descriptions................................................................................................ 2270
Table 15-176. ADCPPB3PMIN Register Field Descriptions.................................................................................................. 2271
Table 15-177. ADCPPB3PMINI Register Field Descriptions................................................................................................. 2272
Table 15-178. ADCPPB3TRIPLO2 Register Field Descriptions............................................................................................ 2273
Table 15-179. ADCPPB4LIMIT Register Field Descriptions.................................................................................................. 2274
Table 15-180. ADCPPBP4PCOUNT Register Field Descriptions..........................................................................................2275
Table 15-181. ADCPPB4CONFIG2 Register Field Descriptions........................................................................................... 2276
Table 15-182. ADCPPB4PSUM Register Field Descriptions.................................................................................................2278
Table 15-183. ADCPPB4PMAX Register Field Descriptions................................................................................................. 2279
Table 15-184. ADCPPB4PMAXI Register Field Descriptions................................................................................................ 2280
Table 15-185. ADCPPB4PMIN Register Field Descriptions.................................................................................................. 2281
Table 15-186. ADCPPB4PMINI Register Field Descriptions................................................................................................. 2282
Table 15-187. ADCPPB4TRIPLO2 Register Field Descriptions............................................................................................ 2283
Table 16-1. DAC Supported Gain Mode Combinations......................................................................................................... 2286
Table 16-2. DAC Registers to Driverlib Functions................................................................................................................. 2288
Table 16-3. DAC Base Address Table................................................................................................................................... 2289
Table 16-4. DAC_REGS Registers........................................................................................................................................ 2290
Table 16-5. DAC_REGS Access Type Codes....................................................................................................................... 2290
Table 16-6. DACREV Register Field Descriptions................................................................................................................. 2291
Table 16-7. DACCTL Register Field Descriptions..................................................................................................................2292
Table 16-8. DACVALA Register Field Descriptions................................................................................................................2293
Table 16-9. DACVALS Register Field Descriptions................................................................................................................2294
Table 16-10. DACOUTEN Register Field Descriptions..........................................................................................................2295
Table 16-11. DACLOCK Register Field Descriptions............................................................................................................. 2296
Table 16-12. DACTRIM Register Field Descriptions..............................................................................................................2297
Table 17-1. CMPSS Registers to Driverlib Functions............................................................................................................ 2309
Table 17-2. CMPSS Base Address Table.............................................................................................................................. 2313
Table 17-3. CMPSS_REGS Registers...................................................................................................................................2314
Table 17-4. CMPSS_REGS Access Type Codes.................................................................................................................. 2315
Table 17-5. COMPCTL Register Field Descriptions.............................................................................................................. 2316
Table 17-6. COMPHYSCTL Register Field Descriptions....................................................................................................... 2318
Table 17-7. COMPSTS Register Field Descriptions.............................................................................................................. 2319
Table 17-8. COMPSTSCLR Register Field Descriptions....................................................................................................... 2320
Table 17-9. COMPDACHCTL Register Field Descriptions.................................................................................................... 2321
Table 17-10. COMPDACHCTL2 Register Field Descriptions................................................................................................ 2323
Table 17-11. DACHVALS Register Field Descriptions........................................................................................................... 2324
Table 17-12. DACHVALA Register Field Descriptions........................................................................................................... 2325
Table 17-13. RAMPHREFA Register Field Descriptions........................................................................................................2326
Table 17-14. RAMPHREFS Register Field Descriptions....................................................................................................... 2327

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Table 17-15. RAMPHSTEPVALA Register Field Descriptions...............................................................................................2328

Table 17-16. RAMPHCTLA Register Field Descriptions........................................................................................................2329
Table 17-17. RAMPHSTEPVALS Register Field Descriptions...............................................................................................2330
Table 17-18. RAMPHCTLS Register Field Descriptions........................................................................................................2331
Table 17-19. RAMPHSTS Register Field Descriptions.......................................................................................................... 2332
Table 17-20. DACLVALS Register Field Descriptions............................................................................................................2333
Table 17-21. DACLVALA Register Field Descriptions............................................................................................................2334
Table 17-22. RAMPHDLYA Register Field Descriptions........................................................................................................ 2335
Table 17-23. RAMPHDLYS Register Field Descriptions........................................................................................................ 2336
Table 17-24. CTRIPLFILCTL Register Field Descriptions..................................................................................................... 2337
Table 17-25. CTRIPLFILCLKCTL Register Field Descriptions.............................................................................................. 2338
Table 17-26. CTRIPHFILCTL Register Field Descriptions.....................................................................................................2339
Table 17-27. CTRIPHFILCLKCTL Register Field Descriptions..............................................................................................2340
Table 17-28. COMPLOCK Register Field Descriptions......................................................................................................... 2341
Table 17-29. COMPDACLCTL Register Field Descriptions...................................................................................................2342
Table 17-30. COMPDACLCTL2 Register Field Descriptions.................................................................................................2344
Table 17-31. RAMPLREFA Register Field Descriptions........................................................................................................ 2345
Table 17-32. RAMPLREFS Register Field Descriptions........................................................................................................ 2346
Table 17-33. RAMPLSTEPVALA Register Field Descriptions............................................................................................... 2347
Table 17-34. RAMPLCTLA Register Field Descriptions........................................................................................................ 2348
Table 17-35. RAMPLSTEPVALS Register Field Descriptions............................................................................................... 2349
Table 17-36. RAMPLCTLS Register Field Descriptions........................................................................................................ 2350
Table 17-37. RAMPLSTS Register Field Descriptions...........................................................................................................2351
Table 17-38. RAMPLDLYA Register Field Descriptions.........................................................................................................2352
Table 17-39. RAMPLDLYS Register Field Descriptions.........................................................................................................2353
Table 17-40. CTRIPLFILCLKCTL2 Register Field Descriptions............................................................................................ 2354
Table 17-41. CTRIPHFILCLKCTL2 Register Field Descriptions............................................................................................2355
Table 18-1. Different Gain Values and Corresponding Resistor Values.................................................................................2358
Table 18-2. Modes of Operation............................................................................................................................................ 2359
Table 18-3. Minimum Filter Resistance..................................................................................................................................2363
Table 18-4. PGA and ADC Connection..................................................................................................................................2367
Table 18-5. PGA Registers to Driverlib Functions................................................................................................................. 2375
Table 18-6. PGA Base Address Table................................................................................................................................... 2376
Table 18-7. PGA_REGS Registers........................................................................................................................................ 2377
Table 18-8. PGA_REGS Access Type Codes....................................................................................................................... 2377
Table 18-9. PGACTL Register Field Descriptions..................................................................................................................2378
Table 18-10. MUXSEL Register Field Descriptions............................................................................................................... 2379
Table 18-11. OFFSETTRIM Register Field Descriptions....................................................................................................... 2380
Table 18-12. PGATYPE Register Field Descriptions............................................................................................................. 2381
Table 18-13. PGALOCK Register Field Descriptions.............................................................................................................2382
Table 19-1. Submodule Configuration Parameters................................................................................................................2391
Table 19-2. Key Time-Base Signals.......................................................................................................................................2395
Table 19-3. ePWM SYNC Selection...................................................................................................................................... 2400
Table 19-4. Action-Qualifier Submodule Possible Input Events.............................................................................................2415
Table 19-5. Action-Qualifier Event Priority for Up-Down-Count Mode................................................................................... 2417
Table 19-6. Action-Qualifier Event Priority for Up-Count Mode............................................................................................. 2417
Table 19-7. Action-Qualifier Event Priority for Down-Count Mode.........................................................................................2417
Table 19-8. Behavior if CMPA/CMPB is Greater than the Period.......................................................................................... 2418
Table 19-9. Classical Dead-Band Operating Modes..............................................................................................................2431
Table 19-10. Additional Dead-Band Operating Modes.......................................................................................................... 2431
Table 19-11. Dead-Band Delay Values in μs as a Function of DBFED and DBRED............................................................. 2433
Table 19-12. Possible Pulse Width Values for EPWMCLK = 80MHz.....................................................................................2436
Table 19-13. Possible Actions On a Trip Event......................................................................................................................2440
Table 19-14. Lock Bits and Corresponding Registers............................................................................................................2478
Table 19-15. Resolution for PWM and HRPWM.................................................................................................................... 2480
Table 19-16. Relationship Between MEP Steps, PWM Frequency, and Resolution..............................................................2486
Table 19-17. CMPA versus Duty (left), and [CMPA:CMPAHR] versus Duty (right)................................................................2487
Table 19-18. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles................................................................. 2490
Table 19-19. SFO Library Features....................................................................................................................................... 2502
Table 19-20. Factor Values.................................................................................................................................................... 2503
Table 19-21. EPWM Registers to Driverlib Functions............................................................................................................2505

74 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 19-22. HRPWM Registers to Driverlib Functions......................................................................................................... 2512

Table 19-23. EPWM Base Address Table..............................................................................................................................2524
Table 19-24. EPWM_REGS Registers.................................................................................................................................. 2525
Table 19-25. EPWM_REGS Access Type Codes..................................................................................................................2527
Table 19-26. TBCTL Register Field Descriptions...................................................................................................................2528
Table 19-27. TBCTL2 Register Field Descriptions.................................................................................................................2530
Table 19-28. EPWMSYNCINSEL Register Field Descriptions.............................................................................................. 2531
Table 19-29. TBCTR Register Field Descriptions.................................................................................................................. 2532
Table 19-30. TBSTS Register Field Descriptions.................................................................................................................. 2533
Table 19-31. EPWMSYNCOUTEN Register Field Descriptions............................................................................................ 2534
Table 19-32. TBCTL3 Register Field Descriptions.................................................................................................................2536
Table 19-33. CMPCTL Register Field Descriptions............................................................................................................... 2537
Table 19-34. CMPCTL2 Register Field Descriptions............................................................................................................. 2539
Table 19-35. DBCTL Register Field Descriptions.................................................................................................................. 2541
Table 19-36. DBCTL2 Register Field Descriptions................................................................................................................ 2544
Table 19-37. AQCTL Register Field Descriptions.................................................................................................................. 2545
Table 19-38. AQTSRCSEL Register Field Descriptions........................................................................................................ 2547
Table 19-39. PCCTL Register Field Descriptions.................................................................................................................. 2548
Table 19-40. VCAPCTL Register Field Descriptions............................................................................................................. 2550
Table 19-41. VCNTCFG Register Field Descriptions.............................................................................................................2552
Table 19-42. HRCNFG Register Field Descriptions...............................................................................................................2554
Table 19-43. HRPWR Register Field Descriptions................................................................................................................ 2556
Table 19-44. HRMSTEP Register Field Descriptions............................................................................................................ 2557
Table 19-45. HRCNFG2 Register Field Descriptions.............................................................................................................2558
Table 19-46. HRPCTL Register Field Descriptions................................................................................................................2559
Table 19-47. TRREM Register Field Descriptions................................................................................................................. 2561
Table 19-48. GLDCTL Register Field Descriptions................................................................................................................2562
Table 19-49. GLDCFG Register Field Descriptions............................................................................................................... 2564
Table 19-50. EPWMXLINK Register Field Descriptions........................................................................................................ 2566
Table 19-51. AQCTLA Register Field Descriptions................................................................................................................2568
Table 19-52. AQCTLA2 Register Field Descriptions..............................................................................................................2570
Table 19-53. AQCTLB Register Field Descriptions................................................................................................................2571
Table 19-54. AQCTLB2 Register Field Descriptions..............................................................................................................2573
Table 19-55. AQSFRC Register Field Descriptions............................................................................................................... 2574
Table 19-56. AQCSFRC Register Field Descriptions............................................................................................................ 2575
Table 19-57. DBREDHR Register Field Descriptions............................................................................................................ 2576
Table 19-58. DBRED Register Field Descriptions................................................................................................................. 2577
Table 19-59. DBFEDHR Register Field Descriptions.............................................................................................................2578
Table 19-60. DBFED Register Field Descriptions..................................................................................................................2579
Table 19-61. TBPHS Register Field Descriptions.................................................................................................................. 2580
Table 19-62. TBPRDHR Register Field Descriptions.............................................................................................................2581
Table 19-63. TBPRD Register Field Descriptions..................................................................................................................2582
Table 19-64. CMPA Register Field Descriptions.................................................................................................................... 2583
Table 19-65. CMPB Register Field Descriptions....................................................................................................................2584
Table 19-66. CMPC Register Field Descriptions................................................................................................................... 2585
Table 19-67. CMPD Register Field Descriptions................................................................................................................... 2586
Table 19-68. GLDCTL2 Register Field Descriptions..............................................................................................................2587
Table 19-69. SWVDELVAL Register Field Descriptions.........................................................................................................2588
Table 19-70. TZSEL Register Field Descriptions...................................................................................................................2589
Table 19-71. TZDCSEL Register Field Descriptions..............................................................................................................2591
Table 19-72. TZCTL Register Field Descriptions...................................................................................................................2592
Table 19-73. TZCTL2 Register Field Descriptions.................................................................................................................2594
Table 19-74. TZCTLDCA Register Field Descriptions........................................................................................................... 2596
Table 19-75. TZCTLDCB Register Field Descriptions........................................................................................................... 2598
Table 19-76. TZEINT Register Field Descriptions................................................................................................................. 2600
Table 19-77. TZFLG Register Field Descriptions...................................................................................................................2601
Table 19-78. TZCBCFLG Register Field Descriptions........................................................................................................... 2603
Table 19-79. TZOSTFLG Register Field Descriptions........................................................................................................... 2605
Table 19-80. TZCLR Register Field Descriptions.................................................................................................................. 2607
Table 19-81. TZCBCCLR Register Field Descriptions...........................................................................................................2609
Table 19-82. TZOSTCLR Register Field Descriptions........................................................................................................... 2610

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Table 19-83. TZFRC Register Field Descriptions...................................................................................................................2611

Table 19-84. ETSEL Register Field Descriptions...................................................................................................................2612
Table 19-85. ETPS Register Field Descriptions.....................................................................................................................2615
Table 19-86. ETFLG Register Field Descriptions.................................................................................................................. 2618
Table 19-87. ETCLR Register Field Descriptions.................................................................................................................. 2619
Table 19-88. ETFRC Register Field Descriptions.................................................................................................................. 2620
Table 19-89. ETINTPS Register Field Descriptions...............................................................................................................2621
Table 19-90. ETSOCPS Register Field Descriptions.............................................................................................................2622
Table 19-91. ETCNTINITCTL Register Field Descriptions.................................................................................................... 2624
Table 19-92. ETCNTINIT Register Field Descriptions........................................................................................................... 2625
Table 19-93. DCTRIPSEL Register Field Descriptions..........................................................................................................2626
Table 19-94. DCACTL Register Field Descriptions................................................................................................................2628
Table 19-95. DCBCTL Register Field Descriptions................................................................................................................2630
Table 19-96. DCFCTL Register Field Descriptions................................................................................................................2632
Table 19-97. DCCAPCTL Register Field Descriptions...........................................................................................................2634
Table 19-98. DCFOFFSET Register Field Descriptions........................................................................................................ 2636
Table 19-99. DCFOFFSETCNT Register Field Descriptions................................................................................................. 2637
Table 19-100. DCFWINDOW Register Field Descriptions.....................................................................................................2638
Table 19-101. DCFWINDOWCNT Register Field Descriptions............................................................................................. 2639
Table 19-102. BLANKPULSEMIXSEL Register Field Descriptions....................................................................................... 2640
Table 19-103. DCCAP Register Field Descriptions............................................................................................................... 2642
Table 19-104. DCAHTRIPSEL Register Field Descriptions...................................................................................................2643
Table 19-105. DCALTRIPSEL Register Field Descriptions....................................................................................................2645
Table 19-106. DCBHTRIPSEL Register Field Descriptions...................................................................................................2647
Table 19-107. DCBLTRIPSEL Register Field Descriptions....................................................................................................2649
Table 19-108. EPWMLOCK Register Field Descriptions....................................................................................................... 2651
Table 19-109. HWVDELVAL Register Field Descriptions...................................................................................................... 2653
Table 19-110. VCNTVAL Register Field Descriptions............................................................................................................ 2654
Table 20-1. eCAP Input Selection..........................................................................................................................................2658
Table 20-2. ECAP Registers to Driverlib Functions............................................................................................................... 2676
Table 20-3. ECAP Base Address Table................................................................................................................................. 2678
Table 20-4. ECAP_REGS Registers......................................................................................................................................2679
Table 20-5. ECAP_REGS Access Type Codes..................................................................................................................... 2679
Table 20-6. TSCTR Register Field Descriptions.................................................................................................................... 2680
Table 20-7. CTRPHS Register Field Descriptions................................................................................................................. 2681
Table 20-8. CAP1 Register Field Descriptions.......................................................................................................................2682
Table 20-9. CAP2 Register Field Descriptions.......................................................................................................................2683
Table 20-10. CAP3 Register Field Descriptions.....................................................................................................................2684
Table 20-11. CAP4 Register Field Descriptions..................................................................................................................... 2685
Table 20-12. ECCTL0 Register Field Descriptions................................................................................................................ 2686
Table 20-13. ECCTL1 Register Field Descriptions................................................................................................................ 2687
Table 20-14. ECCTL2 Register Field Descriptions................................................................................................................ 2689
Table 20-15. ECEINT Register Field Descriptions.................................................................................................................2691
Table 20-16. ECFLG Register Field Descriptions.................................................................................................................. 2693
Table 20-17. ECCLR Register Field Descriptions..................................................................................................................2695
Table 20-18. ECFRC Register Field Descriptions..................................................................................................................2696
Table 20-19. ECAPSYNCINSEL Register Field Descriptions................................................................................................2697
Table 21-1. eQEP Input Source Select Table........................................................................................................................ 2704
Table 21-2. EQEP Memory Map............................................................................................................................................ 2706
Table 21-3. Quadrature Decoder Truth Table........................................................................................................................ 2708
Table 21-4. EQEP Registers to Driverlib Functions............................................................................................................... 2727
Table 21-5. EQEP Base Address Table................................................................................................................................. 2731
Table 21-6. EQEP_REGS Registers......................................................................................................................................2732
Table 21-7. EQEP_REGS Access Type Codes..................................................................................................................... 2732
Table 21-8. QPOSCNT Register Field Descriptions.............................................................................................................. 2734
Table 21-9. QPOSINIT Register Field Descriptions...............................................................................................................2735
Table 21-10. QPOSMAX Register Field Descriptions............................................................................................................2736
Table 21-11. QPOSCMP Register Field Descriptions............................................................................................................ 2737
Table 21-12. QPOSILAT Register Field Descriptions............................................................................................................ 2738
Table 21-13. QPOSSLAT Register Field Descriptions........................................................................................................... 2739
Table 21-14. QPOSLAT Register Field Descriptions............................................................................................................. 2740

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Table 21-15. QUTMR Register Field Descriptions.................................................................................................................2741

Table 21-16. QUPRD Register Field Descriptions................................................................................................................. 2742
Table 21-17. QWDTMR Register Field Descriptions............................................................................................................. 2743
Table 21-18. QWDPRD Register Field Descriptions..............................................................................................................2744
Table 21-19. QDECCTL Register Field Descriptions.............................................................................................................2745
Table 21-20. QEPCTL Register Field Descriptions................................................................................................................2747
Table 21-21. QCAPCTL Register Field Descriptions............................................................................................................. 2749
Table 21-22. QPOSCTL Register Field Descriptions.............................................................................................................2750
Table 21-23. QEINT Register Field Descriptions................................................................................................................... 2751
Table 21-24. QFLG Register Field Descriptions.................................................................................................................... 2753
Table 21-25. QCLR Register Field Descriptions.................................................................................................................... 2755
Table 21-26. QFRC Register Field Descriptions....................................................................................................................2757
Table 21-27. QEPSTS Register Field Descriptions............................................................................................................... 2759
Table 21-28. QCTMR Register Field Descriptions.................................................................................................................2761
Table 21-29. QCPRD Register Field Descriptions................................................................................................................. 2762
Table 21-30. QCTMRLAT Register Field Descriptions...........................................................................................................2763
Table 21-31. QCPRDLAT Register Field Descriptions...........................................................................................................2764
Table 21-32. REV Register Field Descriptions.......................................................................................................................2765
Table 21-33. QEPSTROBESEL Register Field Descriptions.................................................................................................2766
Table 21-34. QMACTRL Register Field Descriptions............................................................................................................ 2767
Table 21-35. QEPSRCSEL Register Field Descriptions........................................................................................................ 2768
Table 22-1. SPI Module Signal Summary.............................................................................................................................. 2773
Table 22-2. SPI Interrupt Flag Modes.................................................................................................................................... 2775
Table 22-3. SPI Clocking Scheme Selection Guide...............................................................................................................2783
Table 22-4. 4-wire versus 3-wire SPI Pin Functions.............................................................................................................. 2786
Table 22-5. 3-Wire SPI Pin Configuration.............................................................................................................................. 2787
Table 22-6. SPI Registers to Driverlib Functions................................................................................................................... 2794
Table 22-7. SPI Base Address Table..................................................................................................................................... 2798
Table 22-8. SPI_REGS Registers..........................................................................................................................................2799
Table 22-9. SPI_REGS Access Type Codes......................................................................................................................... 2799
Table 22-10. SPICCR Register Field Descriptions................................................................................................................ 2800
Table 22-11. SPICTL Register Field Descriptions..................................................................................................................2802
Table 22-12. SPISTS Register Field Descriptions................................................................................................................. 2804
Table 22-13. SPIBRR Register Field Descriptions.................................................................................................................2806
Table 22-14. SPIRXEMU Register Field Descriptions........................................................................................................... 2807
Table 22-15. SPIRXBUF Register Field Descriptions............................................................................................................ 2808
Table 22-16. SPITXBUF Register Field Descriptions............................................................................................................ 2809
Table 22-17. SPIDAT Register Field Descriptions................................................................................................................. 2810
Table 22-18. SPIFFTX Register Field Descriptions................................................................................................................2811
Table 22-19. SPIFFRX Register Field Descriptions...............................................................................................................2813
Table 22-20. SPIFFCT Register Field Descriptions............................................................................................................... 2815
Table 22-21. SPIPRI Register Field Descriptions.................................................................................................................. 2816
Table 23-1. SCI Module Signal Summary..............................................................................................................................2820
Table 23-2. Programming the Data Format Using SCICCR.................................................................................................. 2823
Table 23-3. Asynchronous Baud Register Values for Common SCI Bit Rates...................................................................... 2832
Table 23-4. SCI Interrupt Flags..............................................................................................................................................2834
Table 23-5. SCI Registers to Driverlib Functions................................................................................................................... 2836
Table 23-6. SCI Base Address Table..................................................................................................................................... 2840
Table 23-7. SCI_REGS Registers..........................................................................................................................................2841
Table 23-8. SCI_REGS Access Type Codes......................................................................................................................... 2841
Table 23-9. SCICCR Register Field Descriptions.................................................................................................................. 2842
Table 23-10. SCICTL1 Register Field Descriptions............................................................................................................... 2844
Table 23-11. SCIHBAUD Register Field Descriptions............................................................................................................2846
Table 23-12. SCILBAUD Register Field Descriptions............................................................................................................ 2847
Table 23-13. SCICTL2 Register Field Descriptions............................................................................................................... 2848
Table 23-14. SCIRXST Register Field Descriptions.............................................................................................................. 2850
Table 23-15. SCIRXEMU Register Field Descriptions........................................................................................................... 2853
Table 23-16. SCIRXBUF Register Field Descriptions............................................................................................................2854
Table 23-17. SCITXBUF Register Field Descriptions............................................................................................................ 2856
Table 23-18. SCIFFTX Register Field Descriptions............................................................................................................... 2857
Table 23-19. SCIFFRX Register Field Descriptions...............................................................................................................2859

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Table 23-20. SCIFFCT Register Field Descriptions...............................................................................................................2861

Table 23-21. SCIPRI Register Field Descriptions.................................................................................................................. 2862
Table 24-1. USB Memory Access from Software...................................................................................................................2877
Table 24-2. USB Memory Access from CCS IDE.................................................................................................................. 2878
Table 24-3. USB Registers to Driverlib Functions..................................................................................................................2880
Table 24-4. USB Base Address Table....................................................................................................................................2899
Table 24-5. USB_REGS Registers........................................................................................................................................ 2900
Table 24-6. USB_REGS Access Type Codes........................................................................................................................2902
Table 24-7. USBFADDR Register Field Descriptions............................................................................................................ 2904
Table 24-8. USBPOWER Register Field Descriptions........................................................................................................... 2905
Table 24-9. USBTXIS Register Field Descriptions.................................................................................................................2906
Table 24-10. USBRXIS Register Field Descriptions.............................................................................................................. 2907
Table 24-11. USBTXIE Register Field Descriptions............................................................................................................... 2908
Table 24-12. USBRXIE Register Field Descriptions.............................................................................................................. 2909
Table 24-13. USBIS Register Field Descriptions................................................................................................................... 2910
Table 24-14. USBIE Register Field Descriptions....................................................................................................................2911
Table 24-15. USBFRAME Register Field Descriptions.......................................................................................................... 2912
Table 24-16. USBEPIDX Register Field Descriptions............................................................................................................2913
Table 24-17. USBTEST Register Field Descriptions............................................................................................................. 2914
Table 24-18. USBFIFO0 Register Field Descriptions............................................................................................................ 2915
Table 24-19. USBFIFO1 Register Field Descriptions............................................................................................................ 2916
Table 24-20. USBFIFO2 Register Field Descriptions............................................................................................................ 2917
Table 24-21. USBFIFO3 Register Field Descriptions............................................................................................................ 2918
Table 24-22. USBDEVCTL Register Field Descriptions........................................................................................................ 2919
Table 24-23. USBTXFIFOSZ Register Field Descriptions..................................................................................................... 2921
Table 24-24. USBRXFIFOSZ Register Field Descriptions.....................................................................................................2922
Table 24-25. USBTXFIFOADD Register Field Descriptions.................................................................................................. 2923
Table 24-26. USBRXFIFOADD Register Field Descriptions..................................................................................................2932
Table 24-27. USBCONTIM Register Field Descriptions........................................................................................................ 2941
Table 24-28. USBFSEOF Register Field Descriptions...........................................................................................................2942
Table 24-29. USBLSEOF Register Field Descriptions...........................................................................................................2943
Table 24-30. USBTXFUNCADDR0 Register Field Descriptions............................................................................................2944
Table 24-31. USBTXHUBADDR0 Register Field Descriptions.............................................................................................. 2945
Table 24-32. USBTXHUBPORT0 Register Field Descriptions...............................................................................................2946
Table 24-33. USBTXFUNCADDR1 Register Field Descriptions............................................................................................2947
Table 24-34. USBTXHUBADDR1 Register Field Descriptions.............................................................................................. 2948
Table 24-35. USBTXHUBPORT1 Register Field Descriptions...............................................................................................2949
Table 24-36. USBRXFUNCADDR1 Register Field Descriptions........................................................................................... 2950
Table 24-37. USBRXHUBADDR1 Register Field Descriptions..............................................................................................2951
Table 24-38. USBRXHUBPORT1 Register Field Descriptions.............................................................................................. 2952
Table 24-39. USBTXFUNCADDR2 Register Field Descriptions............................................................................................2953
Table 24-40. USBTXHUBADDR2 Register Field Descriptions.............................................................................................. 2954
Table 24-41. USBTXHUBPORT2 Register Field Descriptions...............................................................................................2955
Table 24-42. USBRXFUNCADDR2 Register Field Descriptions........................................................................................... 2956
Table 24-43. USBRXHUBADDR2 Register Field Descriptions..............................................................................................2957
Table 24-44. USBRXHUBPORT2 Register Field Descriptions.............................................................................................. 2958
Table 24-45. USBTXFUNCADDR3 Register Field Descriptions............................................................................................2959
Table 24-46. USBTXHUBADDR3 Register Field Descriptions.............................................................................................. 2960
Table 24-47. USBTXHUBPORT3 Register Field Descriptions...............................................................................................2961
Table 24-48. USBRXFUNCADDR3 Register Field Descriptions........................................................................................... 2962
Table 24-49. USBRXHUBADDR3 Register Field Descriptions..............................................................................................2963
Table 24-50. USBRXHUBPORT3 Register Field Descriptions.............................................................................................. 2964
Table 24-51. USBCSRL0 Register Field Descriptions........................................................................................................... 2965
Table 24-52. USBCSRH0 Register Field Descriptions.......................................................................................................... 2967
Table 24-53. USBCOUNT0 Register Field Descriptions........................................................................................................2968
Table 24-54. USBTYPE0 Register Field Descriptions........................................................................................................... 2969
Table 24-55. USBNAKLMT Register Field Descriptions........................................................................................................ 2970
Table 24-56. USBTXMAXP1 Register Field Descriptions......................................................................................................2971
Table 24-57. USBTXCSRL1 Register Field Descriptions...................................................................................................... 2972
Table 24-58. USBTXCSRH1 Register Field Descriptions......................................................................................................2974
Table 24-59. USBRXMAXP1 Register Field Descriptions..................................................................................................... 2976

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Table 24-60. USBRXCSRL1 Register Field Descriptions...................................................................................................... 2977

Table 24-61. USBRXCSRH1 Register Field Descriptions..................................................................................................... 2979
Table 24-62. USBRXCOUNT1 Register Field Descriptions...................................................................................................2981
Table 24-63. USBTXTYPE1 Register Field Descriptions.......................................................................................................2982
Table 24-64. USBTXINTERVAL1 Register Field Descriptions...............................................................................................2983
Table 24-65. USBRXTYPE1 Register Field Descriptions...................................................................................................... 2984
Table 24-66. USBRXINTERVAL1 Register Field Descriptions.............................................................................................. 2985
Table 24-67. USBTXMAXP2 Register Field Descriptions......................................................................................................2986
Table 24-68. USBTXCSRL2 Register Field Descriptions...................................................................................................... 2987
Table 24-69. USBTXCSRH2 Register Field Descriptions......................................................................................................2989
Table 24-70. USBRXMAXP2 Register Field Descriptions..................................................................................................... 2991
Table 24-71. USBRXCSRL2 Register Field Descriptions...................................................................................................... 2992
Table 24-72. USBRXCSRH2 Register Field Descriptions..................................................................................................... 2994
Table 24-73. USBRXCOUNT2 Register Field Descriptions...................................................................................................2996
Table 24-74. USBTXTYPE2 Register Field Descriptions.......................................................................................................2997
Table 24-75. USBTXINTERVAL2 Register Field Descriptions...............................................................................................2998
Table 24-76. USBRXTYPE2 Register Field Descriptions...................................................................................................... 2999
Table 24-77. USBRXINTERVAL2 Register Field Descriptions.............................................................................................. 3000
Table 24-78. USBTXMAXP3 Register Field Descriptions......................................................................................................3001
Table 24-79. USBTXCSRL3 Register Field Descriptions...................................................................................................... 3002
Table 24-80. USBTXCSRH3 Register Field Descriptions......................................................................................................3004
Table 24-81. USBRXMAXP3 Register Field Descriptions..................................................................................................... 3006
Table 24-82. USBRXCSRL3 Register Field Descriptions...................................................................................................... 3007
Table 24-83. USBRXCSRH3 Register Field Descriptions..................................................................................................... 3009
Table 24-84. USBRXCOUNT3 Register Field Descriptions................................................................................................... 3011
Table 24-85. USBTXTYPE3 Register Field Descriptions.......................................................................................................3012
Table 24-86. USBTXINTERVAL3 Register Field Descriptions...............................................................................................3013
Table 24-87. USBRXTYPE3 Register Field Descriptions...................................................................................................... 3014
Table 24-88. USBRXINTERVAL3 Register Field Descriptions.............................................................................................. 3015
Table 24-89. USBRQPKTCOUNT1 Register Field Descriptions........................................................................................... 3016
Table 24-90. USBRQPKTCOUNT2 Register Field Descriptions........................................................................................... 3017
Table 24-91. USBRQPKTCOUNT3 Register Field Descriptions........................................................................................... 3018
Table 24-92. USBRXDPKTBUFDIS Register Field Descriptions...........................................................................................3019
Table 24-93. USBTXDPKTBUFDIS Register Field Descriptions........................................................................................... 3020
Table 24-94. USBEPC Register Field Descriptions............................................................................................................... 3021
Table 24-95. USBEPCRIS Register Field Descriptions......................................................................................................... 3023
Table 24-96. USBEPCIM Register Field Descriptions........................................................................................................... 3024
Table 24-97. USBEPCISC Register Field Descriptions......................................................................................................... 3025
Table 24-98. USBDRRIS Register Field Descriptions........................................................................................................... 3026
Table 24-99. USBDRIM Register Field Descriptions............................................................................................................. 3027
Table 24-100. USBDRISC Register Field Descriptions......................................................................................................... 3028
Table 24-101. USBGPCS Register Field Descriptions.......................................................................................................... 3029
Table 24-102. USBVDC Register Field Descriptions............................................................................................................. 3030
Table 24-103. USBVDCRIS Register Field Descriptions....................................................................................................... 3031
Table 24-104. USBVDCIM Register Field Descriptions......................................................................................................... 3032
Table 24-105. USBVDCISC Register Field Descriptions....................................................................................................... 3033
Table 24-106. USBIDVRIS Register Field Descriptions.........................................................................................................3034
Table 24-107. USBIDVIM Register Field Descriptions...........................................................................................................3035
Table 24-108. USBIDVISC Register Field Descriptions.........................................................................................................3036
Table 24-109. USBDMASEL Register Field Descriptions......................................................................................................3037
Table 24-110. USB_GLB_INT_EN Register Field Descriptions............................................................................................. 3039
Table 24-111. USB_GLB_INT_FLG Register Field Descriptions........................................................................................... 3040
Table 24-112. USB_GLB_INT_FLG_CLR Register Field Descriptions..................................................................................3041
Table 24-113. USBDMARIS Register Field Descriptions....................................................................................................... 3042
Table 24-114. USBDMAIM Register Field Descriptions......................................................................................................... 3043
Table 24-115. USBDMAISC Register Field Descriptions....................................................................................................... 3045
Table 25-1. FSI Receiver Core Signals..................................................................................................................................3051
Table 25-2. FSI Transmitter Core Signals..............................................................................................................................3051
Table 25-3. External Trigger Sources and Their Index.......................................................................................................... 3055
Table 25-4. Basic Frame Structure........................................................................................................................................ 3069
Table 25-5. Frame Types and the 4-bit Codes.......................................................................................................................3071

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Table 25-6. Ping Frame......................................................................................................................................................... 3071

Table 25-7. Error Frame.........................................................................................................................................................3072
Table 25-8. Data Frame......................................................................................................................................................... 3072
Table 25-9. Multi-Lane Frame Format................................................................................................................................... 3072
Table 25-10. Loopback Connections..................................................................................................................................... 3074
Table 25-11. RX_TRIGx Trigger Select Signals.....................................................................................................................3079
Table 25-12. FSI-SPI Compatibility Frame Structure.............................................................................................................3080
Table 25-13. Contents of Data Received by a Standard SPI.................................................................................................3080
Table 25-14. FSI as Controller Transmitter, SPI as Peripheral Receiver............................................................................... 3081
Table 25-15. SPI as Controller Transmitter, FSI as Peripheral Receiver............................................................................... 3082
Table 25-16. FSI Registers to Driverlib Functions................................................................................................................. 3087
Table 25-17. FSI Base Address Table................................................................................................................................... 3097
Table 25-18. FSI_TX_REGS Registers................................................................................................................................. 3098
Table 25-19. FSI_TX_REGS Access Type Codes.................................................................................................................3098
Table 25-20. TX_MAIN_CTRL Register Field Descriptions................................................................................................... 3100
Table 25-21. TX_CLK_CTRL Register Field Descriptions..................................................................................................... 3101
Table 25-22. TX_OPER_CTRL_LO Register Field Descriptions........................................................................................... 3102
Table 25-23. TX_OPER_CTRL_HI Register Field Descriptions............................................................................................ 3104
Table 25-24. TX_FRAME_CTRL Register Field Descriptions............................................................................................... 3105
Table 25-25. TX_FRAME_TAG_UDATA Register Field Descriptions.................................................................................... 3106
Table 25-26. TX_BUF_PTR_LOAD Register Field Descriptions........................................................................................... 3107
Table 25-27. TX_BUF_PTR_STS Register Field Descriptions.............................................................................................. 3108
Table 25-28. TX_PING_CTRL Register Field Descriptions................................................................................................... 3109
Table 25-29. TX_PING_TAG Register Field Descriptions......................................................................................................3110
Table 25-30. TX_PING_TO_REF Register Field Descriptions............................................................................................... 3111
Table 25-31. TX_PING_TO_CNT Register Field Descriptions...............................................................................................3112
Table 25-32. TX_INT_CTRL Register Field Descriptions.......................................................................................................3113
Table 25-33. TX_DMA_CTRL Register Field Descriptions.................................................................................................... 3115
Table 25-34. TX_LOCK_CTRL Register Field Descriptions...................................................................................................3116
Table 25-35. TX_EVT_STS Register Field Descriptions........................................................................................................3117
Table 25-36. TX_EVT_CLR Register Field Descriptions........................................................................................................3118
Table 25-37. TX_EVT_FRC Register Field Descriptions....................................................................................................... 3119
Table 25-38. TX_USER_CRC Register Field Descriptions....................................................................................................3120
Table 25-39. TX_ECC_DATA Register Field Descriptions.....................................................................................................3121
Table 25-40. TX_ECC_VAL Register Field Descriptions....................................................................................................... 3122
Table 25-41. TX_DLYLINE_CTRL Register Field Descriptions............................................................................................. 3123
Table 25-42. TX_BUF_BASE_y Register Field Descriptions.................................................................................................3124
Table 25-43. FSI_RX_REGS Registers................................................................................................................................. 3125
Table 25-44. FSI_RX_REGS Access Type Codes................................................................................................................ 3126
Table 25-45. RX_MAIN_CTRL Register Field Descriptions...................................................................................................3127
Table 25-46. RX_OPER_CTRL Register Field Descriptions................................................................................................. 3129
Table 25-47. RX_FRAME_INFO Register Field Descriptions................................................................................................3131
Table 25-48. RX_FRAME_TAG_UDATA Register Field Descriptions....................................................................................3132
Table 25-49. RX_DMA_CTRL Register Field Descriptions....................................................................................................3133
Table 25-50. RX_EVT_STS Register Field Descriptions....................................................................................................... 3134
Table 25-51. RX_CRC_INFO Register Field Descriptions.....................................................................................................3137
Table 25-52. RX_EVT_CLR Register Field Descriptions.......................................................................................................3138
Table 25-53. RX_EVT_FRC Register Field Descriptions.......................................................................................................3140
Table 25-54. RX_BUF_PTR_LOAD Register Field Descriptions...........................................................................................3143
Table 25-55. RX_BUF_PTR_STS Register Field Descriptions..............................................................................................3144
Table 25-56. RX_FRAME_WD_CTRL Register Field Descriptions....................................................................................... 3145
Table 25-57. RX_FRAME_WD_REF Register Field Descriptions......................................................................................... 3146
Table 25-58. RX_FRAME_WD_CNT Register Field Descriptions......................................................................................... 3147
Table 25-59. RX_PING_WD_CTRL Register Field Descriptions...........................................................................................3148
Table 25-60. RX_PING_TAG Register Field Descriptions..................................................................................................... 3149
Table 25-61. RX_PING_WD_REF Register Field Descriptions............................................................................................. 3150
Table 25-62. RX_PING_WD_CNT Register Field Descriptions.............................................................................................3151
Table 25-63. RX_INT1_CTRL Register Field Descriptions....................................................................................................3152
Table 25-64. RX_INT2_CTRL Register Field Descriptions....................................................................................................3155
Table 25-65. RX_LOCK_CTRL Register Field Descriptions..................................................................................................3158
Table 25-66. RX_ECC_DATA Register Field Descriptions.................................................................................................... 3159

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Table 25-67. RX_ECC_VAL Register Field Descriptions....................................................................................................... 3160

Table 25-68. RX_ECC_SEC_DATA Register Field Descriptions........................................................................................... 3161
Table 25-69. RX_ECC_LOG Register Field Descriptions......................................................................................................3162
Table 25-70. RX_FRAME_TAG_CMP Register Field Descriptions....................................................................................... 3163
Table 25-71. RX_PING_TAG_CMP Register Field Descriptions........................................................................................... 3164
Table 25-72. RX_TRIG_CTRL_0 Register Field Descriptions............................................................................................... 3165
Table 25-73. RX_TRIG_WIDTH_0 Register Field Descriptions.............................................................................................3166
Table 25-74. RX_DLYLINE_CTRL Register Field Descriptions............................................................................................. 3167
Table 25-75. RX_TRIG_CTRL_1 Register Field Descriptions............................................................................................... 3168
Table 25-76. RX_TRIG_CTRL_2 Register Field Descriptions............................................................................................... 3169
Table 25-77. RX_TRIG_CTRL_3 Register Field Descriptions............................................................................................... 3170
Table 25-78. RX_VIS_1 Register Field Descriptions............................................................................................................. 3171
Table 25-79. RX_UDATA_FILTER Register Field Descriptions............................................................................................. 3172
Table 25-80. RX_BUF_BASE_y Register Field Descriptions................................................................................................ 3173
Table 26-1. Dependency of Delay d on the Divide-Down Value IPSC................................................................................... 3179
Table 26-2. Operating Modes of the I2C Module................................................................................................................... 3181
Table 26-3. Controller-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR..................... 3182
Table 26-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR...........................................3188
Table 26-5. Ways to Generate a NACK Bit............................................................................................................................ 3194
Table 26-6. Descriptions of the Basic I2C Interrupt Requests............................................................................................... 3195
Table 26-7. I2C Registers to Driverlib Functions................................................................................................................... 3198
Table 26-8. I2C Base Address Table..................................................................................................................................... 3202
Table 26-9. I2C_REGS Registers.......................................................................................................................................... 3203
Table 26-10. I2C_REGS Access Type Codes....................................................................................................................... 3203
Table 26-11. I2COAR Register Field Descriptions................................................................................................................. 3204
Table 26-12. I2CIER Register Field Descriptions.................................................................................................................. 3205
Table 26-13. I2CSTR Register Field Descriptions................................................................................................................. 3206
Table 26-14. I2CCLKL Register Field Descriptions............................................................................................................... 3210
Table 26-15. I2CCLKH Register Field Descriptions............................................................................................................... 3211
Table 26-16. I2CCNT Register Field Descriptions................................................................................................................. 3212
Table 26-17. I2CDRR Register Field Descriptions.................................................................................................................3213
Table 26-18. I2CTAR Register Field Descriptions..................................................................................................................3214
Table 26-19. I2CDXR Register Field Descriptions.................................................................................................................3215
Table 26-20. I2CMDR Register Field Descriptions................................................................................................................ 3216
Table 26-21. I2CISRC Register Field Descriptions................................................................................................................3220
Table 26-22. I2CEMDR Register Field Descriptions..............................................................................................................3221
Table 26-23. I2CPSC Register Field Descriptions................................................................................................................. 3223
Table 26-24. I2CFFTX Register Field Descriptions............................................................................................................... 3224
Table 26-25. I2CFFRX Register Field Descriptions............................................................................................................... 3226
Table 27-1. PMBUS Registers to Driverlib Functions............................................................................................................ 3252
Table 27-2. PMBUS Base Address Table.............................................................................................................................. 3253
Table 27-3. PMBUS_REGS Registers...................................................................................................................................3254
Table 27-4. PMBUS_REGS Access Type Codes.................................................................................................................. 3254
Table 27-5. PMBCCR Register Field Descriptions................................................................................................................ 3255
Table 27-6. PMBTXBUF Register Field Descriptions............................................................................................................ 3257
Table 27-7. PMBRXBUF Register Field Descriptions............................................................................................................ 3258
Table 27-8. PMBACK Register Field Descriptions.................................................................................................................3259
Table 27-9. PMBSTS Register Field Descriptions................................................................................................................. 3260
Table 27-10. PMBINTM Register Field Descriptions............................................................................................................. 3262
Table 27-11. PMBTCR Register Field Descriptions............................................................................................................... 3264
Table 27-12. PMBHTA Register Field Descriptions............................................................................................................... 3266
Table 27-13. PMBCTRL Register Field Descriptions.............................................................................................................3267
Table 27-14. PMBTIMCTL Register Field Descriptions......................................................................................................... 3269
Table 27-15. PMBTIMCLK Register Field Descriptions......................................................................................................... 3270
Table 27-16. PMBTIMSTSETUP Register Field Descriptions............................................................................................... 3271
Table 27-17. PMBTIMBIDLE Register Field Descriptions......................................................................................................3272
Table 27-18. PMBTIMLOWTIMOUT Register Field Descriptions.......................................................................................... 3273
Table 27-19. PMBTIMHIGHTIMOUT Register Field Descriptions......................................................................................... 3274
Table 28-1. MCAN I/O Description.........................................................................................................................................3278
Table 28-2. MCAN Clocks and Resets.................................................................................................................................. 3280
Table 28-3. MCAN Hardware Requests.................................................................................................................................3280

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Table 28-4. Steps to Configure MCAN Module......................................................................................................................3283

Table 28-5. CAN FD Frame Description................................................................................................................................ 3284
Table 28-6. DLC Coding in CAN FD...................................................................................................................................... 3285
Table 28-7. Rx Buffer/Rx FIFO Element Size........................................................................................................................ 3301
Table 28-8. Example Filter Configuration for Rx Buffers........................................................................................................3303
Table 28-9. Possible Configurations for Message Transmission........................................................................................... 3303
Table 28-10. Tx Buffer, Tx FIFO, Tx Queue Element Size.....................................................................................................3304
Table 28-11. Rx Buffer/Rx FIFO Element Field Descriptions................................................................................................. 3309
Table 28-12. Tx Buffer Element Field Descriptions................................................................................................................ 3311
Table 28-13. Tx Event FIFO Element Field Descriptions.......................................................................................................3313
Table 28-14. Standard Message ID Filter Element Field Descriptions.................................................................................. 3315
Table 28-15. Extended Message ID Filter Element Field Descriptions..................................................................................3316
Table 28-16. MCAN Registers to Driverlib Functions............................................................................................................ 3318
Table 28-17. MCAN Base Address Table.............................................................................................................................. 3325
Table 28-18. MCANSS_REGS Registers.............................................................................................................................. 3326
Table 28-19. MCANSS_REGS Access Type Codes..............................................................................................................3326
Table 28-20. MCANSS_PID Register Field Descriptions.......................................................................................................3327
Table 28-21. MCANSS_CTRL Register Field Descriptions................................................................................................... 3328
Table 28-22. MCANSS_STAT Register Field Descriptions.................................................................................................... 3329
Table 28-23. MCANSS_ICS Register Field Descriptions.......................................................................................................3330
Table 28-24. MCANSS_IRS Register Field Descriptions.......................................................................................................3331
Table 28-25. MCANSS_IECS Register Field Descriptions.................................................................................................... 3332
Table 28-26. MCANSS_IE Register Field Descriptions......................................................................................................... 3333
Table 28-27. MCANSS_IES Register Field Descriptions.......................................................................................................3334
Table 28-28. MCANSS_EOI Register Field Descriptions...................................................................................................... 3335
Table 28-29. MCANSS_EXT_TS_PRESCALER Register Field Descriptions....................................................................... 3336
Table 28-30. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register Field Descriptions............................................... 3337
Table 28-31. MCAN_REGS Registers................................................................................................................................... 3338
Table 28-32. MCAN_REGS Access Type Codes.................................................................................................................. 3339
Table 28-33. MCAN_CREL Register Field Descriptions........................................................................................................3340
Table 28-34. MCAN_ENDN Register Field Descriptions....................................................................................................... 3341
Table 28-35. MCAN_DBTP Register Field Descriptions........................................................................................................3342
Table 28-36. MCAN_TEST Register Field Descriptions........................................................................................................ 3344
Table 28-37. MCAN_RWD Register Field Descriptions......................................................................................................... 3345
Table 28-38. MCAN_CCCR Register Field Descriptions....................................................................................................... 3346
Table 28-39. MCAN_NBTP Register Field Descriptions........................................................................................................3349
Table 28-40. MCAN_TSCC Register Field Descriptions........................................................................................................3351
Table 28-41. MCAN_TSCV Register Field Descriptions........................................................................................................3352
Table 28-42. MCAN_TOCC Register Field Descriptions....................................................................................................... 3353
Table 28-43. MCAN_TOCV Register Field Descriptions........................................................................................................3354
Table 28-44. MCAN_ECR Register Field Descriptions..........................................................................................................3355
Table 28-45. MCAN_PSR Register Field Descriptions.......................................................................................................... 3356
Table 28-46. MCAN_TDCR Register Field Descriptions....................................................................................................... 3359
Table 28-47. MCAN_IR Register Field Descriptions..............................................................................................................3360
Table 28-48. MCAN_IE Register Field Descriptions.............................................................................................................. 3364
Table 28-49. MCAN_ILS Register Field Descriptions............................................................................................................ 3366
Table 28-50. MCAN_ILE Register Field Descriptions............................................................................................................ 3369
Table 28-51. MCAN_GFC Register Field Descriptions..........................................................................................................3370
Table 28-52. MCAN_SIDFC Register Field Descriptions.......................................................................................................3371
Table 28-53. MCAN_XIDFC Register Field Descriptions.......................................................................................................3372
Table 28-54. MCAN_XIDAM Register Field Descriptions...................................................................................................... 3373
Table 28-55. MCAN_HPMS Register Field Descriptions....................................................................................................... 3374
Table 28-56. MCAN_NDAT1 Register Field Descriptions...................................................................................................... 3375
Table 28-57. MCAN_NDAT2 Register Field Descriptions...................................................................................................... 3378
Table 28-58. MCAN_RXF0C Register Field Descriptions......................................................................................................3381
Table 28-59. MCAN_RXF0S Register Field Descriptions......................................................................................................3382
Table 28-60. MCAN_RXF0A Register Field Descriptions......................................................................................................3383
Table 28-61. MCAN_RXBC Register Field Descriptions....................................................................................................... 3384
Table 28-62. MCAN_RXF1C Register Field Descriptions......................................................................................................3385
Table 28-63. MCAN_RXF1S Register Field Descriptions......................................................................................................3386
Table 28-64. MCAN_RXF1A Register Field Descriptions......................................................................................................3387

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Table 28-65. MCAN_RXESC Register Field Descriptions..................................................................................................... 3388

Table 28-66. MCAN_TXBC Register Field Descriptions........................................................................................................3390
Table 28-67. MCAN_TXFQS Register Field Descriptions..................................................................................................... 3392
Table 28-68. MCAN_TXESC Register Field Descriptions..................................................................................................... 3393
Table 28-69. MCAN_TXBRP Register Field Descriptions..................................................................................................... 3394
Table 28-70. MCAN_TXBAR Register Field Descriptions..................................................................................................... 3397
Table 28-71. MCAN_TXBCR Register Field Descriptions..................................................................................................... 3399
Table 28-72. MCAN_TXBTO Register Field Descriptions......................................................................................................3401
Table 28-73. MCAN_TXBCF Register Field Descriptions......................................................................................................3403
Table 28-74. MCAN_TXBTIE Register Field Descriptions.....................................................................................................3405
Table 28-75. MCAN_TXBCIE Register Field Descriptions.................................................................................................... 3409
Table 28-76. MCAN_TXEFC Register Field Descriptions......................................................................................................3413
Table 28-77. MCAN_TXEFS Register Field Descriptions......................................................................................................3414
Table 28-78. MCAN_TXEFA Register Field Descriptions...................................................................................................... 3415
Table 28-79. MCAN_ERROR_REGS Registers.................................................................................................................... 3416
Table 28-80. MCAN_ERROR_REGS Access Type Codes................................................................................................... 3416
Table 28-81. MCANERR_REV Register Field Descriptions.................................................................................................. 3418
Table 28-82. MCANERR_VECTOR Register Field Descriptions........................................................................................... 3419
Table 28-83. MCANERR_STAT Register Field Descriptions................................................................................................. 3420
Table 28-84. MCANERR_WRAP_REV Register Field Descriptions......................................................................................3421
Table 28-85. MCANERR_CTRL Register Field Descriptions................................................................................................ 3422
Table 28-86. MCANERR_ERR_CTRL1 Register Field Descriptions.....................................................................................3424
Table 28-87. MCANERR_ERR_CTRL2 Register Field Descriptions.....................................................................................3425
Table 28-88. MCANERR_ERR_STAT1 Register Field Descriptions......................................................................................3426
Table 28-89. MCANERR_ERR_STAT2 Register Field Descriptions......................................................................................3428
Table 28-90. MCANERR_ERR_STAT3 Register Field Descriptions......................................................................................3429
Table 28-91. MCANERR_SEC_EOI Register Field Descriptions.......................................................................................... 3430
Table 28-92. MCANERR_SEC_STATUS Register Field Descriptions...................................................................................3431
Table 28-93. MCANERR_SEC_ENABLE_SET Register Field Descriptions......................................................................... 3432
Table 28-94. MCANERR_SEC_ENABLE_CLR Register Field Descriptions......................................................................... 3433
Table 28-95. MCANERR_DED_EOI Register Field Descriptions.......................................................................................... 3434
Table 28-96. MCANERR_DED_STATUS Register Field Descriptions...................................................................................3435
Table 28-97. MCANERR_DED_ENABLE_SET Register Field Descriptions......................................................................... 3436
Table 28-98. MCANERR_DED_ENABLE_CLR Register Field Descriptions.........................................................................3437
Table 28-99. MCANERR_AGGR_ENABLE_SET Register Field Descriptions...................................................................... 3438
Table 28-100. MCANERR_AGGR_ENABLE_CLR Register Field Descriptions....................................................................3439
Table 28-101. MCANERR_AGGR_STATUS_SET Register Field Descriptions.....................................................................3440
Table 28-102. MCANERR_AGGR_STATUS_CLR Register Field Descriptions.................................................................... 3441
Table 29-1. Superfractional Bit Modulation for SCI Mode (Normal Configuration)................................................................ 3451
Table 29-2. Superfractional Bit Modulation for SCI Mode (Maximum Configuration)............................................................ 3452
Table 29-3. SCI Mode (Minimum Configuration)....................................................................................................................3452
Table 29-4. SCI/LIN Interrupts............................................................................................................................................... 3460
Table 29-5. SCI Receiver Status Flags..................................................................................................................................3461
Table 29-6. SCI Transmitter Status Flags.............................................................................................................................. 3461
Table 29-7. Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than v1.3................................ 3468
Table 29-8. Response Length with SCIFORMAT[18:16] Programming................................................................................. 3468
Table 29-9. Superfractional Bit Modulation for LIN Commander Mode and Responder Mode..............................................3470
Table 29-10. Timeout Values in Tbit Units.............................................................................................................................. 3478
Table 29-11. LIN Registers to Driverlib Functions..................................................................................................................3491
Table 29-12. LIN Base Address Table................................................................................................................................... 3496
Table 29-13. LIN_REGS Registers........................................................................................................................................ 3497
Table 29-14. LIN_REGS Access Type Codes....................................................................................................................... 3497
Table 29-15. SCIGCR0 Register Field Descriptions.............................................................................................................. 3499
Table 29-16. SCIGCR1 Register Field Descriptions.............................................................................................................. 3500
Table 29-17. SCIGCR2 Register Field Descriptions.............................................................................................................. 3505
Table 29-18. SCISETINT Register Field Descriptions........................................................................................................... 3507
Table 29-19. SCICLEARINT Register Field Descriptions.......................................................................................................3511
Table 29-20. SCISETINTLVL Register Field Descriptions..................................................................................................... 3514
Table 29-21. SCICLEARINTLVL Register Field Descriptions................................................................................................ 3517
Table 29-22. SCIFLR Register Field Descriptions................................................................................................................. 3520
Table 29-23. SCIINTVECT0 Register Field Descriptions.......................................................................................................3528

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Table 29-24. SCIINTVECT1 Register Field Descriptions.......................................................................................................3529

Table 29-25. SCIFORMAT Register Field Descriptions......................................................................................................... 3530
Table 29-26. BRSR Register Field Descriptions.................................................................................................................... 3531
Table 29-27. SCIED Register Field Descriptions................................................................................................................... 3533
Table 29-28. SCIRD Register Field Descriptions...................................................................................................................3534
Table 29-29. SCITD Register Field Descriptions................................................................................................................... 3535
Table 29-30. SCIPIO0 Register Field Descriptions................................................................................................................3536
Table 29-31. SCIPIO2 Register Field Descriptions................................................................................................................3537
Table 29-32. LINCOMP Register Field Descriptions..............................................................................................................3538
Table 29-33. LINRD0 Register Field Descriptions................................................................................................................. 3539
Table 29-34. LINRD1 Register Field Descriptions................................................................................................................. 3540
Table 29-35. LINMASK Register Field Descriptions.............................................................................................................. 3541
Table 29-36. LINID Register Field Descriptions.....................................................................................................................3542
Table 29-37. LINTD0 Register Field Descriptions..................................................................................................................3543
Table 29-38. LINTD1 Register Field Descriptions..................................................................................................................3544
Table 29-39. MBRSR Register Field Descriptions................................................................................................................. 3545
Table 29-40. IODFTCTRL Register Field Descriptions..........................................................................................................3546
Table 29-41. LIN_GLB_INT_EN Register Field Descriptions................................................................................................ 3549
Table 29-42. LIN_GLB_INT_FLG Register Field Descriptions.............................................................................................. 3550
Table 29-43. LIN_GLB_INT_CLR Register Field Descriptions.............................................................................................. 3551
Table 30-1. Example CLB Clocking Configuration.................................................................................................................3555
Table 30-2. Global Signals and Mux Selection...................................................................................................................... 3559
Table 30-3. Local Signals and Mux Selection........................................................................................................................ 3563
Table 30-4. CLB Output Signal Multiplexer Table.................................................................................................................. 3567
Table 30-5. Output Table........................................................................................................................................................3571
Table 30-6. Input Table.......................................................................................................................................................... 3572
Table 30-7. Ports Tied Off to Prevent Combinatorial Loops...................................................................................................3572
Table 30-8. Counter Block Operating Modes.........................................................................................................................3575
Table 30-9. HLC Event List.................................................................................................................................................... 3584
Table 30-10. HLC ALT Event List...........................................................................................................................................3585
Table 30-11. HLC Instruction Address Ranges...................................................................................................................... 3586
Table 30-12. HLC Instruction Format.....................................................................................................................................3586
Table 30-13. HLC Instruction Description.............................................................................................................................. 3586
Table 30-14. HLC Register Encoding.................................................................................................................................... 3587
Table 30-15. Non-Memory Mapped Register Addresses.......................................................................................................3589
Table 30-16. CLB to SPI RX Access......................................................................................................................................3590
Table 30-17. CLB Registers to Driverlib Functions................................................................................................................ 3591
Table 30-18. CLB Base Address Table.................................................................................................................................. 3600
Table 30-19. CLB_LOGIC_CONFIG_REGS Registers......................................................................................................... 3601
Table 30-20. CLB_LOGIC_CONFIG_REGS Access Type Codes.........................................................................................3602
Table 30-21. CLB_COUNT_RESET Register Field Descriptions.......................................................................................... 3603
Table 30-22. CLB_COUNT_MODE_1 Register Field Descriptions....................................................................................... 3604
Table 30-23. CLB_COUNT_MODE_0 Register Field Descriptions....................................................................................... 3605
Table 30-24. CLB_COUNT_EVENT Register Field Descriptions.......................................................................................... 3606
Table 30-25. CLB_FSM_EXTRA_IN0 Register Field Descriptions........................................................................................3607
Table 30-26. CLB_FSM_EXTERNAL_IN0 Register Field Descriptions.................................................................................3608
Table 30-27. CLB_FSM_EXTERNAL_IN1 Register Field Descriptions.................................................................................3609
Table 30-28. CLB_FSM_EXTRA_IN1 Register Field Descriptions........................................................................................3610
Table 30-29. CLB_LUT4_IN0 Register Field Descriptions..................................................................................................... 3611
Table 30-30. CLB_LUT4_IN1 Register Field Descriptions.....................................................................................................3612
Table 30-31. CLB_LUT4_IN2 Register Field Descriptions.....................................................................................................3613
Table 30-32. CLB_LUT4_IN3 Register Field Descriptions.....................................................................................................3614
Table 30-33. CLB_FSM_LUT_FN1_0 Register Field Descriptions........................................................................................3615
Table 30-34. CLB_FSM_LUT_FN2 Register Field Descriptions............................................................................................3616
Table 30-35. CLB_LUT4_FN1_0 Register Field Descriptions............................................................................................... 3617
Table 30-36. CLB_LUT4_FN2 Register Field Descriptions................................................................................................... 3618
Table 30-37. CLB_FSM_NEXT_STATE_0 Register Field Descriptions.................................................................................3619
Table 30-38. CLB_FSM_NEXT_STATE_1 Register Field Descriptions.................................................................................3620
Table 30-39. CLB_FSM_NEXT_STATE_2 Register Field Descriptions.................................................................................3621
Table 30-40. CLB_MISC_CONTROL Register Field Descriptions........................................................................................ 3622
Table 30-41. CLB_OUTPUT_LUT_0 Register Field Descriptions......................................................................................... 3625

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Table 30-42. CLB_OUTPUT_LUT_1 Register Field Descriptions......................................................................................... 3626

Table 30-43. CLB_OUTPUT_LUT_2 Register Field Descriptions......................................................................................... 3627
Table 30-44. CLB_OUTPUT_LUT_3 Register Field Descriptions......................................................................................... 3628
Table 30-45. CLB_OUTPUT_LUT_4 Register Field Descriptions......................................................................................... 3629
Table 30-46. CLB_OUTPUT_LUT_5 Register Field Descriptions......................................................................................... 3630
Table 30-47. CLB_OUTPUT_LUT_6 Register Field Descriptions......................................................................................... 3631
Table 30-48. CLB_OUTPUT_LUT_7 Register Field Descriptions......................................................................................... 3632
Table 30-49. CLB_HLC_EVENT_SEL Register Field Descriptions....................................................................................... 3633
Table 30-50. CLB_COUNT_MATCH_TAP_SEL Register Field Descriptions........................................................................ 3634
Table 30-51. CLB_OUTPUT_COND_CTRL_0 Register Field Descriptions.......................................................................... 3635
Table 30-52. CLB_OUTPUT_COND_CTRL_1 Register Field Descriptions.......................................................................... 3637
Table 30-53. CLB_OUTPUT_COND_CTRL_2 Register Field Descriptions.......................................................................... 3639
Table 30-54. CLB_OUTPUT_COND_CTRL_3 Register Field Descriptions.......................................................................... 3641
Table 30-55. CLB_OUTPUT_COND_CTRL_4 Register Field Descriptions.......................................................................... 3643
Table 30-56. CLB_OUTPUT_COND_CTRL_5 Register Field Descriptions.......................................................................... 3645
Table 30-57. CLB_OUTPUT_COND_CTRL_6 Register Field Descriptions.......................................................................... 3647
Table 30-58. CLB_OUTPUT_COND_CTRL_7 Register Field Descriptions.......................................................................... 3649
Table 30-59. CLB_MISC_ACCESS_CTRL Register Field Descriptions................................................................................3651
Table 30-60. CLB_SPI_DATA_CTRL_HI Register Field Descriptions................................................................................... 3652
Table 30-61. CLB_LOGIC_CONTROL_REGS Registers......................................................................................................3653
Table 30-62. CLB_LOGIC_CONTROL_REGS Access Type Codes..................................................................................... 3653
Table 30-63. CLB_LOAD_EN Register Field Descriptions.................................................................................................... 3655
Table 30-64. CLB_LOAD_ADDR Register Field Descriptions............................................................................................... 3656
Table 30-65. CLB_LOAD_DATA Register Field Descriptions................................................................................................ 3657
Table 30-66. CLB_INPUT_FILTER Register Field Descriptions............................................................................................ 3658
Table 30-67. CLB_IN_MUX_SEL_0 Register Field Descriptions...........................................................................................3661
Table 30-68. CLB_LCL_MUX_SEL_1 Register Field Descriptions........................................................................................3663
Table 30-69. CLB_LCL_MUX_SEL_2 Register Field Descriptions........................................................................................3664
Table 30-70. CLB_BUF_PTR Register Field Descriptions.....................................................................................................3665
Table 30-71. CLB_GP_REG Register Field Descriptions...................................................................................................... 3666
Table 30-72. CLB_OUT_EN Register Field Descriptions...................................................................................................... 3668
Table 30-73. CLB_GLBL_MUX_SEL_1 Register Field Descriptions..................................................................................... 3669
Table 30-74. CLB_GLBL_MUX_SEL_2 Register Field Descriptions..................................................................................... 3670
Table 30-75. CLB_PRESCALE_CTRL Register Field Descriptions...................................................................................... 3671
Table 30-76. CLB_INTR_TAG_REG Register Field Descriptions..........................................................................................3672
Table 30-77. CLB_LOCK Register Field Descriptions........................................................................................................... 3673
Table 30-78. CLB_HLC_INSTR_READ_PTR Register Field Descriptions............................................................................3674
Table 30-79. CLB_HLC_INSTR_VALUE Register Field Descriptions....................................................................................3675
Table 30-80. CLB_DBG_OUT_2 Register Field Descriptions................................................................................................3676
Table 30-81. CLB_DBG_R0 Register Field Descriptions.......................................................................................................3677
Table 30-82. CLB_DBG_R1 Register Field Descriptions.......................................................................................................3678
Table 30-83. CLB_DBG_R2 Register Field Descriptions.......................................................................................................3679
Table 30-84. CLB_DBG_R3 Register Field Descriptions.......................................................................................................3680
Table 30-85. CLB_DBG_C0 Register Field Descriptions.......................................................................................................3681
Table 30-86. CLB_DBG_C1 Register Field Descriptions.......................................................................................................3682
Table 30-87. CLB_DBG_C2 Register Field Descriptions.......................................................................................................3683
Table 30-88. CLB_DBG_OUT Register Field Descriptions....................................................................................................3684
Table 30-89. CLB_DATA_EXCHANGE_REGS Registers..................................................................................................... 3686
Table 30-90. CLB_DATA_EXCHANGE_REGS Access Type Codes.....................................................................................3686
Table 30-91. CLB_PUSH Register Field Descriptions........................................................................................................... 3687
Table 30-92. CLB_PULL Register Field Descriptions............................................................................................................ 3688
Table 31-1. AES Subsystem DMA Interface.......................................................................................................................... 3692
Table 31-2. Key-Block-Round Combinations......................................................................................................................... 3693
Table 31-3. Interrupts and Events..........................................................................................................................................3704
Table 31-4. AES Registers to Driverlib Functions..................................................................................................................3710
Table 31-5. AES_SS Registers to Driverlib Functions........................................................................................................... 3712
Table 31-6. AES Base Address Table....................................................................................................................................3714
Table 31-7. AES_REGS Registers........................................................................................................................................ 3715
Table 31-8. AES_REGS Access Type Codes........................................................................................................................3716
Table 31-9. AES_KEY2_6 Register Field Descriptions..........................................................................................................3717
Table 31-10. AES_KEY2_7 Register Field Descriptions........................................................................................................3718

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Table 31-11. AES_KEY2_4 Register Field Descriptions........................................................................................................ 3719

Table 31-12. AES_KEY2_5 Register Field Descriptions........................................................................................................3720
Table 31-13. AES_KEY2_2 Register Field Descriptions........................................................................................................3721
Table 31-14. AES_KEY2_3 Register Field Descriptions........................................................................................................3722
Table 31-15. AES_KEY2_0 Register Field Descriptions........................................................................................................3723
Table 31-16. AES_KEY2_1 Register Field Descriptions........................................................................................................3724
Table 31-17. AES_KEY1_6 Register Field Descriptions........................................................................................................3725
Table 31-18. AES_KEY1_7 Register Field Descriptions........................................................................................................3726
Table 31-19. AES_KEY1_4 Register Field Descriptions........................................................................................................3727
Table 31-20. AES_KEY1_5 Register Field Descriptions........................................................................................................3728
Table 31-21. AES_KEY1_2 Register Field Descriptions........................................................................................................3729
Table 31-22. AES_KEY1_3 Register Field Descriptions........................................................................................................3730
Table 31-23. AES_KEY1_0 Register Field Descriptions........................................................................................................3731
Table 31-24. AES_KEY1_1 Register Field Descriptions........................................................................................................3732
Table 31-25. AES_IV_IN_OUT_0 Register Field Descriptions.............................................................................................. 3733
Table 31-26. AES_IV_IN_OUT_1 Register Field Descriptions.............................................................................................. 3734
Table 31-27. AES_IV_IN_OUT_2 Register Field Descriptions.............................................................................................. 3735
Table 31-28. AES_IV_IN_OUT_3 Register Field Descriptions.............................................................................................. 3736
Table 31-29. AES_CTRL Register Field Descriptions........................................................................................................... 3737
Table 31-30. AES_C_LENGTH_0 Register Field Descriptions..............................................................................................3741
Table 31-31. AES_C_LENGTH_1 Register Field Descriptions..............................................................................................3742
Table 31-32. AES_AUTH_LENGTH Register Field Descriptions.......................................................................................... 3743
Table 31-33. AES_DATA_IN_OUT_0 Register Field Descriptions.........................................................................................3744
Table 31-34. AES_DATA_IN_OUT_1 Register Field Descriptions.........................................................................................3745
Table 31-35. AES_DATA_IN_OUT_2 Register Field Descriptions.........................................................................................3746
Table 31-36. AES_DATA_IN_OUT_3 Register Field Descriptions.........................................................................................3747
Table 31-37. AES_TAG_OUT_0 Register Field Descriptions................................................................................................ 3748
Table 31-38. AES_TAG_OUT_1 Register Field Descriptions................................................................................................ 3749
Table 31-39. AES_TAG_OUT_2 Register Field Descriptions................................................................................................ 3750
Table 31-40. AES_TAG_OUT_3 Register Field Descriptions................................................................................................ 3751
Table 31-41. AES_REV Register Field Descriptions............................................................................................................. 3752
Table 31-42. AES_SYSCONFIG Register Field Descriptions................................................................................................3753
Table 31-43. AES_SYSSTATUS Register Field Descriptions................................................................................................ 3755
Table 31-44. AES_IRQSTATUS Register Field Descriptions.................................................................................................3756
Table 31-45. AES_IRQENABLE Register Field Descriptions................................................................................................ 3757
Table 31-46. AES_DIRTY_BITS Register Field Descriptions................................................................................................ 3758
Table 31-47. AES_SS_REGS Registers................................................................................................................................3759
Table 31-48. AES_SS_REGS Access Type Codes............................................................................................................... 3759
Table 31-49. AES_GLB_INT_FLG Register Field Descriptions.............................................................................................3760
Table 31-50. AES_GLB_INT_CLR Register Field Descriptions.............................................................................................3761
Table 32-1. SIGGENx Active Register Loading..................................................................................................................... 3767
Table 32-2. EPG Data Input Connections..............................................................................................................................3770
Table 32-3. EPG Input Connections...................................................................................................................................... 3772
Table 32-4. EPG Output Connections....................................................................................................................................3772
Table 32-5. EPG Registers to Driverlib Functions................................................................................................................. 3777
Table 32-6. EPG Base Address Table................................................................................................................................... 3779
Table 32-7. EPG_REGS Registers........................................................................................................................................ 3780
Table 32-8. EPG_REGS Access Type Codes....................................................................................................................... 3780
Table 32-9. GCTL0 Register Field Descriptions.................................................................................................................... 3782
Table 32-10. GCTL1 Register Field Descriptions.................................................................................................................. 3784
Table 32-11. GCTL2 Register Field Descriptions...................................................................................................................3785
Table 32-12. GCTL3 Register Field Descriptions.................................................................................................................. 3787
Table 32-13. EPGLOCK Register Field Descriptions.............................................................................................................3791
Table 32-14. EPGCOMMIT Register Field Descriptions........................................................................................................3792
Table 32-15. GINTSTS Register Field Descriptions.............................................................................................................. 3793
Table 32-16. GINTEN Register Field Descriptions................................................................................................................ 3794
Table 32-17. GINTCLR Register Field Descriptions.............................................................................................................. 3795
Table 32-18. GINTFRC Register Field Descriptions.............................................................................................................. 3796
Table 32-19. CLKDIV0_CTL0 Register Field Descriptions.................................................................................................... 3797
Table 32-20. CLKDIV0_CLKOFFSET Register Field Descriptions........................................................................................3798
Table 32-21. CLKDIV1_CTL0 Register Field Descriptions.................................................................................................... 3799

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Table 32-22. CLKDIV1_CLKOFFSET Register Field Descriptions........................................................................................3800

Table 32-23. SIGGEN0_CTL0 Register Field Descriptions................................................................................................... 3801
Table 32-24. SIGGEN0_CTL1 Register Field Descriptions................................................................................................... 3803
Table 32-25. SIGGEN0_DATA0 Register Field Descriptions................................................................................................. 3804
Table 32-26. SIGGEN0_DATA1 Register Field Descriptions................................................................................................. 3805
Table 32-27. SIGGEN0_DATA0_ACTIVE Register Field Descriptions.................................................................................. 3806
Table 32-28. SIGGEN0_DATA1_ACTIVE Register Field Descriptions.................................................................................. 3807
Table 32-29. REVISION Register Field Descriptions.............................................................................................................3808
Table 32-30. EPG_MUX_REGS Registers............................................................................................................................ 3809
Table 32-31. EPG_MUX_REGS Access Type Codes........................................................................................................... 3809
Table 32-32. EPGMXSEL0 Register Field Descriptions........................................................................................................ 3810
Table 32-33. EPGMXSELLOCK Register Field Descriptions................................................................................................ 3813
Table 32-34. EPGMXSELCOMMIT Register Field Descriptions............................................................................................3814

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www.ti.com Read This First

Preface
Read This First

About This Manual

This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and
the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data sheet, rather a companion guide that can be used
alongside the device-specific data sheet to understand the details to program the device. The primary purpose
of the TRM is to abstract the programming details of the device from the data sheet. This allows the data sheet
to outline the high-level features of the device without unnecessary information about register descriptions or
programming models.

Note
Texas Instruments is transitioning to use more inclusive terminology. Some language may be different
than what you would expect to see for certain technology areas.

Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers can be shown with the suffix h or the prefix 0x. For example, the following number is
40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field
is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties with
default reset value below. A legend explains the notation used for the properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be avoided.
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For a complete listing of related documentation and development-support tools for these devices, visit the Texas
Instruments website at www.ti.com.
Additionally, the TMS320C28x DSP CPU and Instruction Set Reference Guide and the TMS320C28x Floating
Point Unit and Instruction Set Reference Guide must be used in conjunction with this TRM.
Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.

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Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Trademarks
TI E2E™, C2000™, Code Composer Studio™, and Texas Instruments™ are trademarks of Texas Instruments.
USB Specification Revision 2.0™ is a trademark of Compaq Computer Corp.
All trademarks are the property of their respective owners.

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www.ti.com C2000™ Microcontrollers Software Support

Chapter 1
C2000™ Microcontrollers Software Support

This chapter discusses the C2000Ware for the C2000™ microcontrollers. The C2000Ware can be downloaded
from: www.ti.com/tool/C2000WARE

1.1 Introduction.................................................................................................................................................................92
1.2 C2000Ware Structure................................................................................................................................................. 92
1.3 Documentation............................................................................................................................................................92
1.4 Devices........................................................................................................................................................................ 92
1.5 Libraries...................................................................................................................................................................... 92
1.6 Code Composer Studio™ Integrated Development Environment (IDE)................................................................92
1.7 SysConfig and PinMUX Tool......................................................................................................................................93

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1.1 Introduction
C2000Ware for the C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE
1.2 C2000Ware Structure
The C2000Ware software package is organized into the following directory structure as shown in Table 1-1.
Table 1-1. C2000Ware Root Directories
Directory Name Description
boards Contains the hardware design schematics, BOM, Gerber files, and documentation for C2000 controlCARDS.
device_support Contains all device-specific support files, bit field headers and device development user's guides.
docs Contains the C2000Ware package user's guides and the HTML index page of all package documentation.
driverlib Contains the device-specific driver library and driver-based peripheral examples.
libraries Contains the device-specific and core libraries.

1.3 Documentation
Within C2000Ware, there is an extensive amount of development documentation ranging from board design
documentation, to library user's guides, to driver API documentation. The "boards" directory contains all the
hardware design, BOM, Gerber files, and more for controlCARDs. To assist with locating the necessary
documentation, an HTML page is provided that contains a full list of all the documents in the C2000Ware
package. Locate this page in the "docs" directory.
1.4 Devices
C2000Ware contains the necessary software and documentation to jumpstart development for C2000™
microcontrollers. Each device includes device-specific common source files, peripheral example projects, bit
field headers, and if available, a device peripheral driver library. Additionally, documentation is provided for each
device on how to set up a CCS project, as well as give an overview of all the included example projects and
assist with troubleshooting. For devices with a driver library, documentation is also included that details all the
peripheral APIs available.
To learn more about C2000™ microcontrollers, visit: www.ti.com/c2000.
1.5 Libraries
The libraries included in C2000Ware range from fixed-point and floating-point math libraries, to specialized DSP
libraries, as well as calibration libraries. Each library includes documentation and examples, where applicable.
Additionally, the Flash API files and boot ROM source code are located in the "libraries" directory.
1.6 Code Composer Studio™ Integrated Development Environment (IDE)
Code Composer Studio™ is an integrated development environment (IDE) that supports TI's microcontroller and
embedded processors portfolio. The Code Composer Studio™ IDE comprises a suite of tools used to develop
and debug embedded applications. The latest version of Code Composer Studio™ IDE can be obtained at:
www.ti.com/ccstudio
All projects and examples in C2000Ware are built for and tested with the Code Composer Studio™ IDE.
Although the Code Composer Studio™ IDE is not included with the C2000Ware installer, Code Composer
Studio™ IDE is easily obtainable in a variety of versions.

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1.7 SysConfig and PinMUX Tool

To help simplify configuration challenges and accelerate software development, Texas Instruments™ created
SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring pins, peripherals,
subsystems, and other components. SysConfig helps you manage, expose, and resolve conflicts visually so that
you have more time to create differentiated applications.
The tool's output includes C header and code files that can be used with C2000Ware examples or used to
configure custom software.
The SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The
SysConfig tool is delivered integrated in the Code Composer Studio™ IDE, in the C2000Ware GPIO example,
as a standalone installer, or can be used by way of the cloud tools portal at: dev.ti.com

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Chapter 2
C28x Processor

This chapter contains a short description of the C28x processor and extended instruction sets.
Further information can be found in the following documents:
• TMS320C28x CPU and Instruction Set Reference Guide
• TMS320C28x Extended Instruction Sets Technical Reference Manual
• Accelerators: Enhancing the Capabilities of the C2000 MCU Family Technical Brief
• TMS320C28x FPU Primer Application Report

2.1 Introduction.................................................................................................................................................................95
2.2 C28X Related Collateral............................................................................................................................................. 95
2.3 Features.......................................................................................................................................................................95
2.4 Floating-Point Unit (FPU)...........................................................................................................................................96
2.5 Trigonometric Math Unit (TMU)................................................................................................................................. 96
2.6 VCRC Unit....................................................................................................................................................................97

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2.1 Introduction
The C28x CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing, reduced instruction set computing (RISC), microcontroller architectures, firmware, and tool sets.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
2.2 C28X Related Collateral

Foundational Materials
• C2000 Academy - C28x
• C2000 C28x Migration from COFF to EABI
• C2000 C28x Optimization Guide
• C2000 Performance Tips and Tricks
• C2000 Software Guide
• CGT Data Blocking C2000
• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report

Getting Started Materials

• C2000 Multicore Development User Guide
• C2000 VCU, Viterbi, Complex Math, and CRC (Video)
• C2000Ware - CLAMath
• C2000Ware - FPU Fast RTS
• C2000Ware - FPU Library
• C2000Ware - Fast Integer Division
• C2000Ware - Fixed Point Library
• C2000Ware - IQMath
• C2000Ware - VCU Library
• C28x Context Save and Restore
• CRC Engines in C2000 Devices Application Report
• Migrating Software From 8-Bit (Byte) Addressable CPU's to C28x CPU Application Report
• TMS320C28x Extended Instruction Sets Application Report
• TMS320C28x FPU Primer Application Report

Expert Materials
• Fast Integer Division - A Differentiated Offering From C2000 Product Family Application Report
2.3 Features
The CPU features include a modified Harvard architecture and circular addressing. The RISC features
are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,
and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while the CPU writes data simultaneously to
maintain the single-cycle instruction operation across the pipeline.

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2.4 Floating-Point Unit (FPU)

The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
2.5 Trigonometric Math Unit (TMU)
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions and
leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 2-1.
Table 2-1. TMU Supported Instructions
Instructions C Equivalent Operation Pipeline Cycles
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computation
of floating-point power function for the nonlinear proportional integral derivative control (NLPID) component of
the C2000 Digital Control Library. These two added instructions reduce the power function calculations from a
typical of 300 cycles using library emulation to less than 10 cycles.
No changes have been made to existing instructions, pipeline, or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out the operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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2.6 VCRC Unit

Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. A CRC result register contains the current CRC, which is updated whenever a CRC instruction
is executed.
The following are the CRC polynomials used by the CRC calculation logic of VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial1 = 0x8005
• CRC16 polynomial2 = 0x1021
• CRC24 polynomial = 0x5D 6DCB
• CRC32 polynomial1 = 0x04C1 1DB7
• CRC32 polynomial2 = 0x1EDC 6F41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24 and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to 3 cycles when using a custom polynomial.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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Chapter 3
System Control and Interrupts

The system-level functionality of this microcontroller configures the clocking, resets, and interrupts of the CPU
and peripherals, as well as the operation of the on-chip memories, timers, and security features.

3.1 Introduction.................................................................................................................................................................99
3.2 Power Management..................................................................................................................................................100
3.3 Device Identification and Configuration Registers............................................................................................... 100
3.4 Resets........................................................................................................................................................................100
3.5 Peripheral Interrupts................................................................................................................................................ 103
3.6 Exceptions and Non-Maskable Interrupts.............................................................................................................. 117
3.7 Clocking.....................................................................................................................................................................118
3.8 32-Bit CPU Timers 0/1/2........................................................................................................................................... 133
3.9 Watchdog Timer........................................................................................................................................................134
3.10 Low-Power Modes.................................................................................................................................................. 137
3.11 Memory Controller Module.................................................................................................................................... 140
3.12 JTAG........................................................................................................................................................................ 148
3.13 Live Firmware Update............................................................................................................................................ 148
3.14 System Control Register Configuration Restrictions......................................................................................... 153
3.15 Software.................................................................................................................................................................. 154
3.16 SYSCTRL Registers............................................................................................................................................... 178

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3.1 Introduction
System-level configuration is controlled by a group of submodules that are collectively referred to as the system
control module. The system control module provides the following capabilities:
• System-level resets, including power-on and brownout resets
• Clock source selection and PLL configuration
• Missing clock detection
• Clock-gating low-power modes
• Peripheral interrupt handling
• Non-maskable interrupts for certain fault conditions
• Three 32-bit timers
• Windowed watchdog timer, which can generate an interrupt or a reset
• RAM initialization, write protection, and controller control
• Flash memory ECC, wait state, and cache configuration
• Dual-zone code security module

3.1.1 SYSCTL Related Collateral

Foundational Materials
• C2000 MCU JTAG Connectivity Debug Application Report

Getting Started Materials

• C28x Interrupt Nesting
• Debugging JTAG
• Enhancing Device Security by Using JTAGLOCK Feature Application Report
• Interrupt FAQ for C2000
• XDS Target Connection Guide

Expert Materials
• C2000 CPU Memory Built-In Self-Test Application Report
• Live Firmware Update Without Device Reset on C2000 MCUs Application Report
• Programming of External Nonvolatile Memory Using SDFlash for TMS320C28x Devices Application Report
• Software Phased-Locked Loop (PLL) Design Using C2000 Microcontrollers Application Report
3.1.2 LOCK Protection on System Configuration Registers
Several system configuration registers are protected from spurious CPU writes by LOCK registers. Once these
associated LOCK register bits are set, the respective locked registers can no longer be modified by software.
See the register descriptions for details.
3.1.3 EALLOW Protection
Some registers in the system are protected from spurious CPU writes by the EALLOW protection mechanism.
This uses the special CPU instructions EALLOW and EDIS to enable and disable access to protected registers.
The current protection state is given by the EALLOW bit in the CPU ST1 register, as shown in Table 3-1.
Register protection is enabled by default at startup. While protected, all writes to protected registers by the CPU
are ignored. Only CPU reads, JTAG reads, and JTAG writes are allowed. If protection is disabled by executing
the EALLOW instruction, the CPU is allowed to write freely to protected registers. After modifying registers, the
registers can once again be protected by executing the EDIS instruction to clear the EALLOW bit.
Writes to the clock configuration and peripheral clock enable registers can be disabled until the next reset by
writing to special lock registers.

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Table 3-1. Access to EALLOW-Protected Registers

EALLOW Bit CPU Writes CPU Reads JTAG Writes JTAG Reads
0 Ignored Allowed(1) Allowed Allowed
1 Allowed Allowed Allowed Allowed

(1) The EALLOW bit is overridden by way of the JTAG port, allowing full access of protected registers during debug from the Code
Composer Studio™ IDE interface.

3.2 Power Management

The TMS320F28P55x MCU supports both internal generation of the 1.2V rail for single-supply operation or
externally supplied 1.2V into the device. The internal VREG is controlled using the VREGENZ pin: if enabled,
the 1.2V rail is generated by the device; if disabled, the 1.2V rail is supplied from an external source. For more
details, see TMS320F28P55x Real-Time Microcontrollers.
3.3 Device Identification and Configuration Registers
The device identification registers and configuration registers provide information on the part number, product
family, revision, pin count, qualification status, and feature availability of the device.
All of the device information is part of the DEV_CFG_REGS space. The identification registers are PARTIDL,
PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
• UID_PSRAND0-4: 160 bits of pseudo-random data
• UID_UNIQUE: 64-bit unique data; the value in this register is unique across all devices in the same PARTIDH
• UID_CHECKSUM: 32-bit Fletcher checksum of UID_PSRAND0-4 and UID_UNIQUE and calculated as either
little-endian or big-endian during factory testing

3.4 Resets
This section explains the types and effects of the different resets on this device.
3.4.1 Reset Sources
Table 3-2 summarizes the various reset signals and the effect on the device.
Table 3-2. Reset Signals
Reset Source CPU Core Reset Peripherals JTAG / Debug IOs XRS Output
(C28x, FPU, VCU) Reset Logic Reset
POR Yes Yes Yes Hi-Z Yes
BOR Yes Yes Yes Hi-Z Yes
XRS Pin Yes Yes No Hi-Z -
WDRS Yes Yes No Hi-Z Yes
NMIWDRS Yes Yes No Hi-Z Yes
SYSRS (Debugger Reset) Yes Yes No Hi-Z No
SCCRESET Yes Yes No Hi-Z No
SIMRESET.XRS Yes Yes No Hi-Z Yes
SIMRESET.CPU1RS Yes Yes No Hi-Z No

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The resets can be divided into two groups:

• Chip-level resets (XRS, POR, BOR, WDRS, SIMRESET.XRS, and NMIWDRS), which reset all or almost all
of the device.
• System resets (SYSRS, SIMRESET.CPU1RS, and SCCRESET), which reset a large subset of the device but
maintain some system-level configuration.

After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register maintain
the state across multiple resets. The bits can only be cleared by a power-on reset (POR) or by writing ones to
the RESCCLR register. Some are cleared by the boot ROM as part of the start-up routines.
Many peripheral modules have individual resets accessible through the SOFTPRESx registers. For information
about a module's reset state, refer to the appropriate chapter for that module.
After any reset, the CPU begins execution from address 0x3FFFC0 (the reset vector), which is in the boot ROM.
After running the boot ROM code, the CPU typically branches to the start of the Flash memory at address
0x80000. For more information on controlling the boot process, see Chapter 4 .

Note
After a POR, the boot ROMs clear the M0/M1, LSx, GSx, and message RAMs to make sure that the
memories contain valid ECC or parity.

3.4.2 External Reset (XRS)

The external reset (XRS) is the main chip-level reset for the device and resets the CPU, all peripherals and I/O
pin configurations, and most of the system control registers. There is a dedicated open-drain pin for XRS. This
pin can be used to drive reset pins for other ICs in the application, and can be driven by an external source. The
XRS is driven internally during watchdog, NMI, and power-on resets.
The XRSn bit in the RESC register is set whenever XRS is driven low for any reason. This bit is then cleared by
the boot ROM.
3.4.3 Simulate External Reset (SIMRESET.XRS)
In some cases, the user can need to simulate the external reset (XRS) in software. This can be done using
software by setting XRSn bit to 1 in SIMRESET register. This toggles the XRS pin and resets the full device (just
like an external reset).
After this reset, the SIMRESET_XRSn and XRSn bits in the RESC register are set. Software can read these bits
to know the cause of reset and clear the status by writing a 1 into corresponding bits in RESCCLR register.
3.4.4 Power-On Reset (POR)
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up, suppressing
glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most applications, XRS is held
low long enough to reset other system ICs, but some applications can require a longer pulse. In these cases,
the XRS pin can be driven low externally to provide the correct reset duration. A POR resets everything that
XRS does, along with a few other registers – the reset cause register (RESC), the NMI shadow flag register
(NMISHDFLG), and the X1 clock counter register (X1CNT). A POR also resets the debug logic used by the
JTAG port.
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.

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3.4.5 Brown-Out Reset (BOR)

The brown-out reset (BOR) is an internal supply voltage supervisor (SVS) circuit that monitors the VDDIO
supply for glitches or supply interruptions. If the VDDIO supply voltage drops below operational voltage range,
this circuit forces the XRSn pin low until the fault is removed and the supply voltage returns to the minimum
operational voltage. A BOR resets everything in the same manner as a POR reset.
The BOR circuit is enabled by default and is always active during power up or after any type of reset. To disable
the BOR circuit, set the BORLVMONDIS bit in the VMONCTL register.
3.4.6 Debugger Reset (SYSRS)
During development, it is sometimes necessary to reset the CPU and the peripherals without disconnecting the
debugger or disrupting the system-level configuration. To facilitate this, the CPU has a subsystem reset, which
can be triggered by a debugger using Code Composer Studio™ IDE. This reset (SYSRS) resets the CPU, the
peripherals, many system control registers (including the clock gating and LPM configuration), and all I/O pin
configurations.
The SYSRS does not reset the ICEPick debug module, the device capability registers, the clock source and PLL
configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI flags, the
analog trims, or anything reset only by a POR (see Section 3.4.4).
3.4.7 Simulate CPU Reset (SIMRESET)
In some cases, you can simulate the CPU reset (SYSRS) in software. This can be done by setting the CPU1RSn
bit to 1 in the SIMRESET register by CPU1 software. This toggles CPU1.SYSRS signals, resetting the CPU (just
like the debugger reset).
After this reset, the SIMRESET_CPU1RSn bit in the RESC register is set. Software can read this bit to know the
cause of the reset and clear the status by writing a 1 into the corresponding bit in the RESCCLR register.
3.4.8 Watchdog Reset (WDRS)
The device has a watchdog timer that can optionally trigger a reset if it is not serviced by the CPU within a
user-specified amount of time. This watchdog reset (WDRS) produces an XRS that lasts for 512 INTOSC1
cycles.
After a watchdog reset, the WDRSn and XRSn bits in RESC are set.
3.4.9 NMI Watchdog Reset (NMIWDRS)
The device has a non-maskable interrupt (NMI) module that detects hardware errors in the system. The NMI
module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a user-specified
amount of time. This NMI watchdog reset (NMIWDRS) produces an XRS that lasts for 512 INTOSC1 cycles.
After an NMI watchdog reset, the NMIWDRSn and XRSn bits in RESC are set.
3.4.10 DCSM Safe Code Copy Reset (SCCRESET)
The device has a dual-zone code security module (DCSM) that blocks read access to certain areas of the
Flash memory. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely
access those memory areas. To prevent security breaches, interrupts must be disabled before calling these
functions. If a vector fetch occurs in a safe copy or CRC function, the DCSM triggers a reset. This security reset
(SCCRESET) is similar to a SYSRS. However, the security reset also resets the debug logic to deny access to a
potential attacker.
After a security reset, the SCCRESETn bit in RESC is set.

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3.5 Peripheral Interrupts

This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered in
Section 3.6. Software interrupts and emulation interrupts are not covered in this chapter (see the TMS320C28x
CPU and Instruction Set Reference Guide).
3.5.1 Interrupt Concepts
An interrupt is a signal that causes the CPU to pause the current execution and branch to a different piece of
code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral events,
and involves less CPU overhead or program complexity than register polling. However, because interrupts are
asynchronous to the program flow, care must be taken to avoid conflicts over resources that are accessed both
in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until the interrupt is processed. The enable registers block the propagation of the interrupt. When an
interrupt signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the vector
table.
3.5.2 Interrupt Architecture
The C28x CPU has 14 peripheral interrupt lines. Two of the interrupts (INT13 and INT14) are connected directly
to CPU timers 1 and 2, respectively. The remaining 12 interrupts are connected to peripheral interrupt signals
through the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened version). The PIE
multiplexes up to 16 peripheral interrupts into each CPU interrupt line and also expands the vector table to allow
each interrupt to have an ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages: the peripheral, the PIE, and the CPU. Each stage has enable
and flag registers. This system allows the CPU to handle one interrupt while others are pending, implement and
prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 3-1 shows the interrupt architecture for this device.
TINT0
TIMER0

LPM Logic LPMINT

WAKEINT
WDINT NMI module NMI
WD

INPUTXBAR4 XINT1 Control CPU

INPUTXBAR5 XINT2 Control
GPIO0 ePIE INT1
Input
to INPUTXBAR6 XINT3 Control to
X-BAR
GPIOx INT12
INPUTXBAR13 XINT4 Control
INPUTXBAR14 XINT5 Control

TIMER1 INT13

TIMER2 INT14
Peripherals
See ePIE Table

Figure 3-1. Device Interrupt Architecture

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3.5.2.1 Peripheral Stage

Each peripheral has a unique interrupt configuration, which is described in that peripheral's chapter. Some
peripherals allow multiple events to trigger the same interrupt signal. For example, a communications peripheral
can use the same interrupt to indicate that data has been received or that there has been a transmission error.
The cause of the interrupt can be determined by reading the peripheral's status register. Often, the bits in the
status register must be cleared manually before another interrupt is generated.
3.5.2.2 PIE Stage
The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which are
sometimes called PIE channels. These channels are grouped according to the associated CPU interrupt. Each
PIE group has one 8-bit enable register (PIEIERx), one 8-bit flag register (PIEIFRx) , and one bit in the PIE
acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt mask for the entire PIE
group.
When the CPU receives an interrupt, the CPU fetches the address of the ISR from the PIE. The PIE returns
the vector for the lowest-numbered channel in the group that is both flagged and enabled. This gives lower-
numbered interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition does not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 3.5.4 contains
procedures for safely modifying the PIE configuration once interrupts have been enabled.
3.5.2.3 CPU Stage
Like the PIE, the CPU provides flag and enable register bits for each of the interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared using
the CPU's SETC and CLRC instructions. In C code, C2000Ware's DINT and EINT macros can be used for this
purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is set, the next instruction in the pipeline
runs with interrupts disabled. No software delays are needed.

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3.5.3 Interrupt Entry Sequence

Figure 3-2 shows how peripheral interrupts propagate to the CPU.

Figure 3-2. Interrupt Propagation Path

When a peripheral generates an interrupt (on PIE group x, channel y), the interrupt triggers the following
sequence of events:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier stages
are flushed.
8. The CPU saves the context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.

The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction entering
the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles. Wait states on the
ISR or stack memories add to the latency. External interrupts add a minimum of two SYSCLK cycles for GPIO
synchronization plus extra time for input qualification (if used). Loops created using the C28x RPT instruction
cannot be interrupted.

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3.5.4 Configuring and Using Interrupts

At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is set.
The application code is responsible for configuring and enabling all peripheral interrupts.
3.5.4.1 Enabling Interrupts
To enable a peripheral interrupt, perform the following steps:
1. Disable interrupts globally (DINT or SETC INTM).
2. Enable the PIE by setting the ENPIE bit of the PIECTRL register.
3. Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be found
in Section 3.5.8. Note that the vector table is EALLOW-protected.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be found in
Section 3.5.8.
5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
3.5.4.2 Handling Interrupts
ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the TMS320C28x
Optimizing C/C++ Compiler v6.2.4 User's Guide. For information on writing assembly code to handle interrupts,
see the Standard Operation for Maskable Interrupts section of the TMS320C28x CPU and Instruction Set
Reference Guide.
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at the end
of the ISR. If the PIEACK bit is not cleared, the CPU does not receive any further interrupts from that group. This
does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.
3.5.4.3 Disabling Interrupts
To disable all interrupts, set the CPUs global interrupt mask using DINT or SETC INTM. It is not necessary to
add NOPs after setting INTM or modifying IER – the next instruction executes with interrupts disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, the interrupt signal
can reach the CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no special
procedure is needed.

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The PIEIFR bits must never be cleared in software since the read/modify/write operation can cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The following
procedure can be used to bypass the normal ISR:
1. Disable interrupts globally (DINT or SETC INTM).
2. Modify the PIE vector table to map the PIEIFR bit's interrupt vector to an empty ISR. This ISR only contains
a return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
4. Enable interrupts globally (EINT or CLRC INTM).
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to the original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.

3.5.4.4 Nesting Interrupts

By default, interrupts do not nest. It is possible to nest and prioritize interrupts using software control of the
IER and PIEIERx registers. Example code can be found in C2000Ware and documentation is available at
software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html.
3.5.4.5 Vector Address Validity Check
The ePIE vector table memory is protected using a parity check. Upon each vector fetch from the ePIE, a parity
check is performed. If a parity failure occurs during vector fetch, the ePIE returns either a user defined error
handler routine (if PIEVERRADDR is defined with a non 0x003FFFFF value), or the default boot ROM handler at
address 0x3FFFBE. The ePIE also sends trip signals to the EPWMs.
The parity check only returns the error handler value if the failure occurs during vector fetch. Parity errors
during data read is handled by the memory controller module and logged by UCERRFLG register in
MEMORY_ERROR_REGS. The address that caused the error is located in the UCCPUREADDR register. If
the error address logged is between 0xD00 to 0xDFF, then the error is a PIE parity error. Additionally, a parity
error during vector fetch does not flag an uncorrectable error NMI.

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3.5.5 PIE Channel Mapping

Table 3-3 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within that
group. When multiple interrupts are pending, the lowest-numbered channel is the lowest-numbered group is serviced first. Thus, the interrupts at the top
of the table have the highest priority, and the interrupts at the bottom have the lowest priority.

Note
Cells that are empty are Reserved.

Table 3-3. PIE Channel Mapping

INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 INTx.9 INTx.10 INTx.11 INTx.12 INTx.13 INTx.14 INTx.15 INTx.16
SYS_ER
INT1.y ADCA1 ADCB1 ADCC1 XINT1 XINT2 TIMER0 WAKE ADCD1 ADCE1
R
EPWM1 EPWM2_ EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10_ EPWM11_ EPWM12_
INT2.y
_TZ TZ _TZ _TZ _TZ _TZ _TZ _TZ _TZ TZ TZ TZ
INT3.y EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10 EPWM11 EPWM12
INT4.y ECAP1 ECAP2
INT5.y EQEP1 EQEP2 EQEP3 CLB1 CLB2
SPIA_R SPIB_R
INT6.y SPIA_TX SPIB_TX DCC0 DCC1
X X
DMA_C DMA_CH DMA_C DMA_C DMA_C DMA_C PMBUS FSITXA_I FSITXA_I FSIRXA_I FSIRXA_I
INT7.y
H1 2 H3 H4 H5 H6 A NT1 NT2 NT1 NT2
I2CA_FI I2CB_FI SCIC_R SCIC_T
INT8.y I2CA I2CB LINA_0 LINA_1
FO FO X X
MCANBS
MCANBS
SCIA_R SCIB_R MCANA MCANA MCANB MCANBS S_WAKE_
INT9.y SCIA_TX SCIB_TX S_ECC_C USB NPU
X X SS0 SS1 SS0 S1 AND_TS_
ORR_PLS
PLS
ADCA_E ADCB_E ADCC_E ADCD_EV
INT10.y ADCA2 ADCA3 ADCA4 ADCB2 ADCB3 ADCB4 ADCC2 ADCC3 ADCC4 ADCD2 ADCD3 ADCD4
VT VT VT T
ADCE_E
INT11.y CLA1_1 CLA1_2 CLA1_3 CLA1_4 CLA1_5 CLA1_6 CLA1_7 CLA1_8 ADCE2 ADCE3 ADCE4
VT
MCANA MCANA
FLSS_IN SS_WAK SS_ECC
INT12.y XINT3 XINT4 XINT5 AES_INT
T E_AND_ _CORR_
TS_PLS PLS

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3.5.6 PIE Interrupt Priority

3.5.6.1 Channel Priority
For every PIE group, the low number channels in the group have the highest priority. For instance in PIE group
1, channel 1.1 has priority over channel 1.3. If those two enabled interrupts occurred simultaneously, channel
1.1 is serviced first with channel 1.3 left pending. Once the ISR for channel 1.1 completes and provided there
are no other enabled and pending interrupts for PIE group 1, channel 1.3 is serviced. However, for the CPU to
service any more interrupts from a PIE group, PIEACK for the group must be cleared. For this specific example,
for channel 1.3 to be serviced, channel 1.1’s ISR has to clear PIEACK for group 1.
The following example describes an alternative scenario: channel 1.1 is currently being serviced by the CPU,
channel 1.3 is pending and before channel 1.1’s ISR completes, channel 1.2 that is enabled also comes in.
Since channel 1.2 has a higher priority than channel 1.3, the CPU services channel 1.2 and channel 1.3 is
still left pending. Using the steps from the Interrupt Entry Sequence (Section 3.5.3), channel 1.2 interrupt can
happen as late as step 10 (the CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared) and the channel
is still serviced ahead of channel 1.3.
3.5.6.2 Group Priority
Generally, the lowest channel in the lowest PIE group has the highest priority. An example of this is channels
1.1 and 2.1. Those two channels have the highest priority in the respective groups. If the interrupts for those two
enabled channels happened simultaneously and provided there are no other enabled and pending interrupts,
channel 1.1 is serviced first by the CPU with channel 2.1 left pending.
However, there are cases where channel priority supersedes group priority. This special case happens
depending on which step the CPU is currently at in the Interrupt Entry Sequence (Section 3.5.3).
The following illustrates an example of this special case.
The CPU is about to service channel 2.3 and is currently going through the steps in the Interrupt Entry Sequence
(Section 3.5.3).
1. As the CPU reaches step 10 (the CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared), two
enabled interrupts: channel 1.1 and channel 2.1 come in.
2. Due to channel priority, channel 2.1 is serviced ahead of channel 2.3. However, group priority dictates that
channel 1.1 be serviced ahead of channels 2.1 and 2.3.
3. Channel priority supersedes here and channel 2.1 is serviced ahead of channels 1.1 and 2.3.
4. After channel 2.1 completes, channel 1.1 is serviced followed by channel 2.3.
Group priority is only specified if no interrupts are currently being serviced, that is, the Interrupt Entry Sequence
(Section 3.5.3) is not executing.

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3.5.7 System Error

SYS_ERR consolidate several sources of interrupts (see Figure 3-3). These sources set the respective bit in
the SYS_ERR_INT_FLG register. Any set bit in the SYS_ERR_INT_FLG register also sets the global interrupt
(GINT) bit. The GINT bit has to be cleared before any SYS_ERR interrupt is generated. If the GINT bit is cleared
with the source flags still set, another SYS_ERR interrupt is fired; therefore, it is recommended to clear the
source flags before clearing the GINT bit.

Figure 3-3. System Error

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3.5.8 Vector Tables

Table 3-4 shows the CPU interrupt vector table. The vectors for INT1–INT12 are not used in this device. The
reset vector is fetched from the boot ROM instead of from this table. All vectors are EALLOW-protected.
Table 3-5 shows the PIE vector table.
Table 3-4. CPU Interrupt Vectors
Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
Reset 0 0x0000 0D00 2 Reset is always fetched from location 1 (Highest) -
0x003F_FFC0 in Boot ROM
INT1 1 0x0000 0D02 2 Not used. See PIE Group 1 5 -
INT2 2 0x0000 0D04 2 Not used. See PIE Group 2 6 -
INT3 3 0x0000 0D06 2 Not used. See PIE Group 3 7 -
INT4 4 0x0000 0D08 2 Not used. See PIE Group 4 8 -
INT5 5 0x0000 0D0A 2 Not used. See PIE Group 5 9 -
INT6 6 0x0000 0D0C 2 Not used. See PIE Group 6 10 -
INT7 7 0x0000 0D0E 2 Not used. See PIE Group 7 11 -
INT8 8 0x0000 0D10 2 Not used. See PIE Group 8 12 -
INT9 9 0x0000 0D12 2 Not used. See PIE Group 9 13 -
INT10 10 0x0000 0D14 2 Not used. See PIE Group 10 14 -
INT11 11 0x0000 0D16 2 Not used. See PIE Group 11 15 -
INT12 12 0x0000 0D18 2 Not used. See PIE Group 12 16 -
INT13 13 0x0000 0D1A 2 CPU TIMER1 Interrupt 17 -
INT14 14 0x0000 0D1C 2 CPU TIMER2 Interrupt 18 -
DATALOG 15 0x0000 0D1E 2 CPU Data Logging Interrupt 19 (lowest) -
RTOSINT 16 0x0000 0D20 2 CPU Real-Time OS Interrupt 4 -
RSVD 17 0x0000 0D22 2 Reserved 2 -
NMI 18 0x0000 0D24 2 Non-Maskable Interrupt 3 -
ILLEGAL 19 0x0000 0D26 2 Illegal Instruction (ITRAP) - -
USER 1 20 0x0000 0D28 2 User-Defined Trap - -
USER 2 21 0x0000 0D2A 2 User-Defined Trap - -
USER 3 22 0x0000 0D2C 2 User-Defined Trap - -
USER 4 23 0x0000 0D2E 2 User-Defined Trap - -
USER 5 24 0x0000 0D30 2 User-Defined Trap - -
USER 6 25 0x0000 0D32 2 User-Defined Trap - -
USER 7 26 0x0000 0D34 2 User-Defined Trap - -
USER 8 27 0x0000 0D36 2 User-Defined Trap - -
USER 9 28 0x0000 0D38 2 User-Defined Trap - -
USER 10 29 0x0000 0D3A 2 User-Defined Trap - -
USER 11 30 0x0000 0D3C 2 User-Defined Trap - -
USER 12 31 0x0000 0D3E 2 User-Defined Trap - -

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Table 3-5. PIE Interrupt Vectors

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1 32 0x0000 0D40 2 ADCA1 interrupt 5 1 (Highest)
INT1.2 33 0x0000 0D42 2 ADCB1 interrupt 5 2
INT1.3 34 0x0000 0D44 2 ADCC1 interrupt 5 3
INT1.4 35 0x0000 0D46 2 XINT1 interrupt 5 4
INT1.5 36 0x0000 0D48 2 XINT2 interrupt 5 5
INT1.6 37 0x0000 0D4A 2 SYS_ERR interrupt 5 6
INT1.7 38 0x0000 0D4C 2 TIMER0 interrupt 5 7
INT1.8 39 0x0000 0D4E 2 WAKE interrupt 5 8
INT1.9 128 0x0000 0E00 2 ADCD1 interrupt 5 9
INT1.10 129 0x0000 0E02 2 ADCE1 interrupt 5 10
INT1.11 130 0x0000 0E04 2 Reserved 5 11
INT1.12 131 0x0000 0E06 2 Reserved 5 12
INT1.13 132 0x0000 0E08 2 Reserved 5 13
INT1.14 133 0x0000 0E0A 2 Reserved 5 14
INT1.15 134 0x0000 0E0C 2 Reserved 5 15
INT1.16 135 0x0000 0E0E 2 Reserved 5 16 (Lowest)
PIE Group 2 Vectors - Muxed into CPU INT2
INT2.1 40 0x0000 0D50 2 EPWM1 trip zone interrupt 6 1 (Highest)
INT2.2 41 0x0000 0D52 2 EPWM2 trip zone interrupt 6 2
INT2.3 42 0x0000 0D54 2 EPWM3 trip zone interrupt 6 3
INT2.4 43 0x0000 0D56 2 EPWM4 trip zone interrupt 6 4
INT2.5 44 0x0000 0D58 2 EPWM5 trip zone interrupt 6 5
INT2.6 45 0x0000 0D5A 2 EPWM6 trip zone interrupt 6 6
INT2.7 46 0x0000 0D5C 2 EPWM7 trip zone interrupt 6 7
INT2.8 47 0x0000 0D5E 2 EPWM8 trip zone interrupt 6 8
INT2.9 136 0x0000 0E10 2 EPWM9 trip zone interrupt 6 9
INT2.10 137 0x0000 0E12 2 EPWM10 trip zone interrupt 6 10
INT2.11 138 0x0000 0E14 2 EPWM11 trip zone interrupt 6 11
INT2.12 139 0x0000 0E16 2 EPWM12 trip zone interrupt 6 12
INT2.13 140 0x0000 0E18 2 Reserved 6 13
INT2.14 141 0x0000 0E1A 2 Reserved 6 14
INT2.15 142 0x0000 0E1C 2 Reserved 6 15
INT2.16 143 0x0000 0E1E 2 Reserved 6 16 (Lowest)
PIE Group 3 Vectors - Muxed into CPU INT3
INT3.1 48 0x0000 0D60 2 EPWM1 interrupt 7 1 (Highest)
INT3.2 49 0x0000 0D62 2 EPWM2 interrupt 7 2
INT3.3 50 0x0000 0D64 2 EPWM3 interrupt 7 3
INT3.4 51 0x0000 0D66 2 EPWM4 interrupt 7 4
INT3.5 52 0x0000 0D68 2 EPWM5 interrupt 7 5
INT3.6 53 0x0000 0D6A 2 EPWM6 interrupt 7 6
INT3.7 54 0x0000 0D6C 2 EPWM7 interrupt 7 7
INT3.8 55 0x0000 0D6E 2 EPWM8 interrupt 7 8
INT3.9 144 0x0000 0E20 2 EPWM9 interrupt 7 9

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
INT3.10 145 0x0000 0E22 2 EPWM10 interrupt 7 10
INT3.11 146 0x0000 0E24 2 EPWM11 interrupt 7 11
INT3.12 147 0x0000 0E26 2 EPWM12 interrupt 7 12
INT3.13 148 0x0000 0E28 2 Reserved 7 13
INT3.14 149 0x0000 0E2A 2 Reserved 7 14
INT3.15 150 0x0000 0E2C 2 Reserved 7 15
INT3.16 151 0x0000 0E2E 2 Reserved 7 16 (Lowest)
PIE Group 4 Vectors - Muxed into CPU INT4
INT4.1 56 0x0000 0D70 2 ECAP1 interrupt 8 1 (Highest)
INT4.2 57 0x0000 0D72 2 ECAP2 interrupt 8 2
INT4.3 58 0x0000 0D74 2 Reserved 8 3
INT4.4 59 0x0000 0D76 2 Reserved 8 4
INT4.5 60 0x0000 0D78 2 Reserved 8 5
INT4.6 61 0x0000 0D7A 2 Reserved 8 6
INT4.7 62 0x0000 0D7C 2 Reserved 8 7
INT4.8 63 0x0000 0D7E 2 Reserved 8 8
INT4.9 152 0x0000 0E30 2 Reserved 8 9
INT4.10 153 0x0000 0E32 2 Reserved 8 10
INT4.11 154 0x0000 0E34 2 Reserved 8 11
INT4.12 155 0x0000 0E36 2 Reserved 8 12
INT4.13 156 0x0000 0E38 2 Reserved 8 13
INT4.14 157 0x0000 0E3A 2 Reserved 8 14
INT4.15 158 0x0000 0E3C 2 Reserved 8 15
INT4.16 159 0x0000 0E3E 2 Reserved 8 16 (Lowest)
PIE Group 5 Vectors - Muxed into CPU INT5
INT5.1 64 0x0000 0D80 2 EQEP1 interrupt 9 1 (Highest)
INT5.2 65 0x0000 0D82 2 EQEP2 interrupt 9 2
INT5.3 66 0x0000 0D84 2 EQEP3 interrupt 9 3
INT5.4 67 0x0000 0D86 2 Reserved 9 4
INT5.5 68 0x0000 0D88 2 CLB1 interrupt 9 5
INT5.6 69 0x0000 0D8A 2 CLB2 interrupt 9 6
INT5.7 70 0x0000 0D8C 2 Reserved 9 7
INT5.8 71 0x0000 0D8E 2 Reserved 9 8
INT5.9 160 0x0000 0E40 2 Reserved 9 9
INT5.10 161 0x0000 0E42 2 Reserved 9 10
INT5.11 162 0x0000 0E44 2 Reserved 9 11
INT5.12 163 0x0000 0E46 2 Reserved 9 12
INT5.13 164 0x0000 0E48 2 Reserved 9 13
INT5.14 165 0x0000 0E4A 2 Reserved 9 14
INT5.15 166 0x0000 0E4C 2 Reserved 9 15
INT5.16 167 0x0000 0E4E 2 Reserved 9 16 (Lowest)

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
PIE Group 6 Vectors - Muxed into CPU INT6
INT6.1 72 0x0000 0D90 2 SPIA RX interrupt 10 1 (Highest)
INT6.2 73 0x0000 0D92 2 SPIA TX interrupt 10 2
INT6.3 74 0x0000 0D94 2 SPIB RX interrupt 10 3
INT6.4 75 0x0000 0D96 2 SPIB TX interrupt 10 4
INT6.5 76 0x0000 0D98 2 Reserved 10 5
INT6.6 77 0x0000 0D9A 2 Reserved 10 6
INT6.7 78 0x0000 0D9C 2 DCC0 interrupt 10 7
INT6.8 79 0x0000 0D9E 2 DCC1 interrupt 10 8
INT6.9 168 0x0000 0E50 2 Reserved 10 9
INT6.10 169 0x0000 0E52 2 Reserved 10 10
INT6.11 170 0x0000 0E54 2 Reserved 10 11
INT6.12 171 0x0000 0E56 2 Reserved 10 12
INT6.13 172 0x0000 0E58 2 Reserved 10 13
INT6.14 173 0x0000 0E5A 2 Reserved 10 14
INT6.15 174 0x0000 0E5C 2 Reserved 10 15
INT6.16 175 0x0000 0E5E 2 Reserved 10 16 (Lowest)
PIE Group 7 Vectors - Muxed into CPU INT7
INT7.1 80 0x0000 0DA0 2 DMA CH1 Interrupt 11 1 (Highest)
INT7.2 81 0x0000 0DA2 2 DMA CH2 Interrupt 11 2
INT7.3 82 0x0000 0DA4 2 DMA CH3 Interrupt 11 3
INT7.4 83 0x0000 0DA6 2 DMA CH4 Interrupt 11 4
INT7.5 84 0x0000 0DA8 2 DMA CH5 Interrupt 11 5
INT7.6 85 0x0000 0DAA 2 DMA CH6 Interrupt 11 6
INT7.7 86 0x0000 0DAC 2 PMBUSA 11 7
INT7.8 87 0x0000 0DAE 2 Reserved 11 8
INT7.9 176 0x0000 0E60 2 Reserved 11 9
INT7.10 177 0x0000 0E62 2 Reserved 11 10
INT7.11 178 0x0000 0E64 2 FSITX INT1 Interrupt 11 11
INT7.12 179 0x0000 0E66 2 FSITX INT2 Interrupt 11 12
INT7.13 180 0x0000 0E68 2 FSIRX INT1 Interrupt 11 13
INT7.14 181 0x0000 0E6A 2 FSIRX INT2 Interrupt 11 14
INT7.15 182 0x0000 0E6C 2 Reserved 11 15
INT7.16 183 0x0000 0E6E 2 Reserved 11 16 (Lowest)
PIE Group 8 Vectors - Muxed into CPU INT8
INT8.1 88 0x0000 0DB0 2 I2CA interrupt 12 1 (Highest)
INT8.2 89 0x0000 0DB2 2 I2CA FIFO interrupt 12 2
INT8.3 90 0x0000 0DB4 2 I2CB interrupt 12 3
INT8.4 91 0x0000 0DB6 2 I2CB FIFO interrupt 12 4
INT8.5 92 0x0000 0DB8 2 SCIC RX interrupt 12 5
INT8.6 93 0x0000 0DBA 2 SCIC TX interrupt 12 6
INT8.7 94 0x0000 0DBC 2 Reserved 12 7
INT8.8 95 0x0000 0DBE 2 Reserved 12 8
INT8.9 184 0x0000 0E70 2 LINA INT1 Interrupt 12 9

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
INT8.10 185 0x0000 0E72 2 LINA INT2 Interrupt 12 10
INT8.11 186 0x0000 0E74 2 Reserved 12 11
INT8.12 187 0x0000 0E76 2 Reserved 12 12
INT8.13 188 0x0000 0E78 2 Reserved 12 13
INT8.14 189 0x0000 0E7A 2 Reserved 12 14
INT8.15 190 0x0000 0E7C 2 Reserved 12 15
INT8.16 191 0x0000 0E7E 2 Reserved 12 16 (Lowest)
PIE Group 9 Vectors - Muxed into CPU INT9
INT9.1 96 0x0000 0DC0 2 SCIA RX interrupt 13 1 (Highest)
INT9.2 97 0x0000 0DC2 2 SCIA TX interrupt 13 2
INT9.3 98 0x0000 0DC4 2 SCIB RX interrupt 13 3
INT9.4 99 0x0000 0DC6 2 SCIB TX interrupt 13 4
INT9.5 100 0x0000 0DC8 2 Reserved 13 5
INT9.6 101 0x0000 0DCA 2 Reserved 13 6
INT9.7 102 0x0000 0DCC 2 MCANA INT0 interrupt 13 7
INT9.8 103 0x0000 0DCE 2 MCANA INT1 interrupt 13 8
INT9.9 192 0x0000 0E80 2 MCANB INT0 interrupt 13 9
INT9.10 193 0x0000 0E82 2 MCANB INT1 interrupt 13 10
INT9.11 194 0x0000 0E84 2 MCANB ECC interrupt 13 11
INT9.12 195 0x0000 0E86 2 MCANB WAKE interrupt 13 12
INT9.13 196 0x0000 0E88 2 Reserved 13 13
INT9.14 197 0x0000 0E8A 2 Reserved 13 14
INT9.15 198 0x0000 0E8C 2 USB Interrupt 13 15
INT9.16 199 0x0000 0E8E 2 NPU Interrupt 13 16 (Lowest)
PIE Group 10 Vectors - Muxed into CPU INT10
INT10.1 104 0x0000 0DD0 2 ADCA event interrupt 14 1 (Highest)
INT10.2 105 0x0000 0DD2 2 ADCA2 interrupt 14 2
INT10.3 106 0x0000 0DD4 2 ADCA3 interrupt 14 3
INT10.4 107 0x0000 0DD6 2 ADCA4 interrupt 14 4
INT10.5 108 0x0000 0DD8 2 ADCB event interrupt 14 5
INT10.6 109 0x0000 0DDA 2 ADCB2 interrupt 14 6
INT10.7 110 0x0000 0DDC 2 ADCB3 interrupt 14 7
INT10.8 111 0x0000 0DDE 2 ADCB4 interrupt 14 8
INT10.9 200 0x0000 0E90 2 ADCC event interrupt 14 9
INT10.10 201 0x0000 0E92 2 ADCC2 interrupt 14 10
INT10.11 202 0x0000 0E94 2 ADCC3 interrupt 14 11
INT10.12 203 0x0000 0E96 2 ADCC4 interrupt 14 12
INT10.13 204 0x0000 0E98 2 ADCD event interrupt 14 13
INT10.14 205 0x0000 0E9A 2 ADCD2 interrupt 14 14
INT10.15 206 0x0000 0E9C 2 ADCD3 interrupt 14 15
INT10.16 207 0x0000 0E9E 2 ADCD4 interrupt 14 16 (Lowest)

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
PIE Group 11 Vectors - Muxed into CPU INT11
INT11.1 112 0x0000 0DE0 2 CLA_1 interrupt 15 1 (Highest)
INT11.2 113 0x0000 0DE2 2 CLA_2 interrupt 15 2
INT11.3 114 0x0000 0DE4 2 CLA_3 interrupt 15 3
INT11.4 115 0x0000 0DE6 2 CLA_4 interrupt 15 4
INT11.5 116 0x0000 0DE8 2 CLA_5 interrupt 15 5
INT11.6 117 0x0000 0DEA 2 CLA_6 interrupt 15 6
INT11.7 118 0x0000 0DEC 2 CLA_7 interrupt 15 7
INT11.8 119 0x0000 0DEE 2 CLA_8 interrupt 15 8
INT11.9 208 0x0000 0EA0 2 ADCE event interrupt 15 9
INT11.10 209 0x0000 0EA2 2 ADCE2 interrupt 15 10
INT11.11 210 0x0000 0EA4 2 ADCE3 interrupt 15 11
INT11.12 211 0x0000 0EA6 2 ADCE4 interrupt 15 12
INT11.13 212 0x0000 0EA8 2 Reserved 15 13
INT11.14 213 0x0000 0EAA 2 Reserved 15 14
INT11.15 214 0x0000 0EAC 2 Reserved 15 15
INT11.16 215 0x0000 0EAE 2 Reserved 15 16 (Lowest)
PIE Group 12 Vectors - Muxed into CPU INT12
INT12.1 120 0x0000 0DF0 2 XINT3 interrupt 16 1 (Highest)
INT12.2 121 0x0000 0DF2 2 XINT4 interrupt 16 2
INT12.3 122 0x0000 0DF4 2 XINT5 interrupt 16 3
INT12.4 123 0x0000 0DF6 2 Reserved 16 4
INT12.5 124 0x0000 0DF8 2 FLSS_INT interrupt 16 5
INT12.6 125 0x0000 0DFA 2 VCRC 16 6
INT12.7 126 0x0000 0DFC 2 MCANA ECC interrupt 16 7
INT12.8 127 0x0000 0DFE 2 MCANA WAKE interrupt 16 8
INT12.9 216 0x0000 0EB0 2 Reserved 16 9
INT12.10 217 0x0000 0EB2 2 Reserved 16 10
INT12.11 218 0x0000 0EB4 2 Reserved 16 11
INT12.12 219 0x0000 0EB6 2 Reserved 16 12
INT12.13 220 0x0000 0EB8 2 AES Interrupt 16 13
INT12.14 221 0x0000 0EBA 2 Reserved 16 14
INT12.15 222 0x0000 0EBC 2 Reserved 16 15
INT12.16 223 0x0000 0EBE 2 Reserved 16 16 (Lowest)

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3.6 Exceptions and Non-Maskable Interrupts

This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.
3.6.1 Configuring and Using NMIs
An incoming NMI sets a status bit in the NMIFLG register and starts the NMI watchdog counter. This counter is
clocked by the SYSCLK, and if the count reaches the value in the NMIWDPRD register, the counter triggers an
NMI watchdog reset (NMIWDRS). To prevent this, the NMI handler must clear the flag bit using the NMIFLGCLR
register. Once all flag bits are clear, the NMIINT bit in the NMIFLG register can also be cleared to allow future
NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI handler
vector must be written to the PIE vector table.
3.6.2 Emulation Considerations
The NMI watchdog counter behaves as follows under debug conditions:

CPU Suspended When the CPU is suspended, the NMI watchdog counter is suspended.
Run-Free Mode When the CPU is placed in run-free mode, the NMI watchdog counter
resumes operation as normal.
Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the NMI watchdog
counter is suspended. The counter remains suspended even within real-
time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the NMI watchdog counter
operates as normal.

3.6.3 NMI Sources

There are several types of hardware errors that can trigger an NMI. Additional information about the error is
usually available from the module that detects it.
3.6.3.1 Missing Clock Detection
The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and an NMI is fired to the CPU. For more information on missing
clock detection, see Section 3.7.12.1.
3.6.3.2 RAM Uncorrectable Error
A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read triggers an
NMI. This applies to CPU and DMA reads. Single-bit ECC data errors do not trigger an NMI, but can optionally
trigger a normal peripheral interrupt. For more information on RAM error detection, see Section 3.11.1.9.
3.6.3.3 Flash Uncorrectable ECC Error
A double-bit ECC data error or single-bit ECC address error in a Flash read triggers an NMI. Single-bit ECC data
errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt.
3.6.3.4 Software-Forced Error
There is a special NMI source that can only be triggered by writing to the SWERR bit in the NMIFLGFRC
register. Since the SWERR flag is never set by a real hardware fail, it can be used to implement a self-test mode
for the NMI subsystem.

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3.6.3.5 ERAD NMI

The ERAD module can generate NMI based on different events. This is configurable in the GLBL_NMI_CTL
register.
3.6.4 Illegal Instruction Trap (ITRAP)
If the CPU tries to execute an illegal instruction, the CPU generates a special interrupt called an illegal
instruction trap (ITRAP). This interrupt is non-maskable and has a vector in the PIE vector table. For more
information about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and Instruction
Set Reference Guide.

Note
A RAM fetch access violation triggers an ITRAP in addition to the normal peripheral interrupt for RAM
access violations. The CPU handles the ITRAP first.

3.6.5 ERRORSTS Pin

The ERRORSTS pin is an ‘always output’ pin and remains high until an error is detected inside the chip. On
an error, the ERRORSTS pin goes low (default polarity) until the corresponding internal error status flag for that
error source is cleared. Figure 3-4 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin is tri-stated until the chip power rails ramp up to the lower operational limit. As the
ERRORSTS pin is an active-low pin (default polarity), users who care about the state of this pin during power-up
can connect an external pull-down on this pin.
Following enhancement has been made on this device for ERRORSTS pin logic:
• Polarity of Error pin has been made configurable through the ERRORCTL register (default setting is active-
low polarity).
• To enable testing of the Error pin, capability to force and clear the Error pin from software has been provided.
• Additional sources of Error have been added to ERRORSTS:
– CPU1 Watchdog reset
– Error on a PIE vector fetch
CPU1's NMI Shadow flags
(Cleared by PORn or Software)

NMISHDFLG.Bit-0
PGIO
NMISHDFLG.Bit-1
3.3 1.2 IN (not used)
ERROR
3.3 1.2 ERR
Edge
STS
detect
REG

‘0’
NMISHDFLG.Bit-15
(Always
Output)

PGIO_33
(from PMM)

Figure 3-4. ERRORSTS Pin Diagram

3.7 Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 3-5 and Figure 3-6 provide an overview of the device's clocking system.

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WDCLK Watchdog
Timer
PERCLKDIVSEL.USBCLKDIV

/1 CLBCLKCTL
/2
. SYSCLK
USBBITCLK
.
.
/8 CLB_TILE_CLK
/1 /1 or /2
PLLCLK
/2
.
.
CLB_REG_CLK
.
SYSCLKDIVSEL /8
SYSCLK
SYS PLLSYSCLK
Divider NMIWD
INTOSC1 SYSPLL PLLRAWCLK

INTOSC2 OSCCLK
PLLCLKEN
X1 (XTAL)

OSCCLKRCSEL CPUCLK
CPU FPU
TMU

GSx RAMs
Boot ROM CLA ROM LSx RAMs
SYSCLK SYSCLK ePIE DCSM Mx RAMs
FLASH XINT Message RAM
GPIO WD System Control
KDIV

Flash Wrapper Clock FLCLK

Flash Wrapper
Divider

One per SYSCLK peripheral

ADC
CLA AES
PCLKCRx CMPSS
CPUTIMERs CLB
PERx.SYSCLK GPDAC
EPWM ERAD
PGA
ECAP EPG
DCC
EQEP FSI
PMBUS
HRCAL I2C
USB
One per SYSCLK peripheral
LSPCLKDIV
PCLKCRx
LSP LSPCLK PERx.LSPCLK SCI
Divider SPI

One per SYSCLK peripheral

LINACLKDIV PLLRAWCLK LIN Xmit
PCLKCRx Clock Gen
PERx.LINACLK
LIN Clock LINACLK LIN
Divider

One per SYSCLK peripheral

NPUCLKDIV
PCLKCRx
PERx.NPUCLK
NPU Clock NPUCLK NPU
Divider

AUXCLKDIVSEL.MCANxCLKDIV

/1
0
/2
Reserved 1
.
AUXCLKIN(GPIO29) MCAN Bit Clock
2 .
PLLRAWCLK 3 .
/20

CLKSRCCTL2.MCANxBCLKSEL

Figure 3-5. Clocking System

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SYSPLL

OSCCLK ÷ INTCLK VCOCLK ÷ PLLRAWCLK

VCO
(REFDIV+1) (ODIV+1)

÷
IMULT

Figure 3-6. System PLL

fOSCCLK
fPLLRAWCLK = × IMULT (1)
REFDIV + 1 ODIV + 1

3.7.1 Clock Sources

All of the clocks in the device are derived from one of four clock sources.
3.7.1.1 Primary Internal Oscillator (INTOSC2)
At power-up, the device is clocked from an on-chip 10MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source and is the default system clock at reset. INTOSC2 is used to run the boot ROM and can be
used as the system clock source for the application. Note that the INTOSC2 frequency tolerance is too loose to
meet the timing requirements for CAN. Use of the CAN modules requires an external oscillator. When INTOSC2
is used as the system clock source, GPIO19 (X1) and GPIO18 (X2) are available as GPIO pins.
3.7.1.2 Backup Internal Oscillator (INTOSC1)
The device also includes a redundant on-chip 10MHz oscillator (INTOSC1). INTOSC1 is a backup clock source
that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is enabled
and a missing system clock is detected, the system PLL is bypassed and all system clocks are connected
to INTOSC1 automatically. INTOSC1 can also be manually selected as the system clock source for debug
purposes.

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3.7.1.3 Auxiliary Clock Input (AUXCLKIN)

An additional external clock source is supported on GPIO29 (AUXCLKIN). This must be a single-ended 3.3V
external clock as shown in Figure 3-7 and can be used as the clock source for MCAN. Frequency limits and
timing requirements are found in the TMS320F28P55x Real-Time Microcontrollers Data Sheet. The external
clock can be connected directly to the GPIO29 pin.
Microcontroller

GPIO29
VSS (AUXCLKIN)

+3.3 V

VDD Out

3.3-V Oscillator

Gnd

Figure 3-7. AUXCLKIN

3.7.1.4 External Oscillator (XTAL)

The device supports an external clock source (XTAL), which can be used as the main system and CAN
bit clock source. Frequency limits and timing requirements can be found in the TMS320F28P55x Real-Time
Microcontrollers Data Sheet. External clock sources use the X1/GPIO19 and X2/GPIO18 pins. After power-up,
the X1 and X2 pin functionality can be enabled by following the procedure in Section 3.7.6.

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Three types of external clock sources are supported:

• A single-ended 3.3V external clock. The clock signal can be connected to X1, as shown in Figure 3-8.

Figure 3-8. Single-ended 3.3V External Clock

• An external crystal. The crystal can be connected across X1 and X2 with the load capacitors connected to
VSS as shown in Figure 3-9.

Figure 3-9. External Crystal

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• An external resonator. The resonator can be connected across X1 and X2 with the ground connected to VSS
as shown in Figure 3-10.

Figure 3-10. External Resonator

Table 3-6. ALT Modes

XTALCR Bit(1)
GPIO19 Available on GPIO18 Available on
OSCOFF SE Operating Mode X1? X2?
0 0 Crystal Mode: Quartz crystal connected to X1/X2 No No
0 1 Single-Ended Mode: External clock on X1 No Yes
1 0 Oscillator off Yes Yes
1 1 Single-Ended Mode: External clock on X1(2) No Yes

(1) OSCOFF and SE determine the ALT mode of GPIO18 and GPIO19.
(2) There is an approximately 1Kohm pull-down on X1 in this mode, external single-ended clock must be able to drive this load.

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3.7.2 Derived Clocks

The clock sources discussed in the previous section can be multiplied (using PLL) and divided down to produce
the desired clock frequencies for the application. This process produces a set of derived clocks, which are
described in this section.
3.7.2.1 Oscillator Clock (OSCCLK)
One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the reference clock (OSCCLK) for the CPU and
most of the peripherals. OSCCLK can be used directly or applied through the system PLL to reach a higher
frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.
3.7.2.2 System PLL Output Clock (PLLRAWCLK)
The system PLL allows the device to run at the maximum rated operating frequency, and in most applications
generates the main system clock. This PLL uses OSCCLK as a reference. PLLRAWCLK is the output of the PLL
voltage-controlled oscillator (VCO). For configuration instructions, see Section 3.7.6.
3.7.3 Device Clock Domains
The device clock domains feed the clock inputs of the various modules in the device. They are connected to the
derived clocks, either directly or through an additional divider.
3.7.3.1 System Clock (PLLSYSCLK)
The NMI watchdog timer has a clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK can be connected
to the system PLL (PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider,
which is configured using the SYSCLKDIVSEL register. PLLSYSCLK is gated in HALT mode.
3.7.3.2 CPU Clock (CPUCLK)
The CPU has a clock (CPUCLK) that is used to clock the CPU and Flash wrapper. This clock is identical to
PLLSYSCLK, but is gated when the CPU enters IDLE or HALT mode.
3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
Each peripheral clock has independent clock gating that is controlled by the PCLKCRx registers.

Note
The application needs to wait for 5 SYSCLK cycles after enabling the clock to the peripherals when
using PCLKCRx.

3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)

The SCI and SPI modules can communicate at bit rates that are much slower than the CPU frequency. These
modules are connected to a shared clock divider, which generates a low-speed peripheral clock (LSPCLK)
derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can be changed using the LOSPCP
register. Each SCI and SPI module's clock (PERx.LSPCLK) can be gated independently using the PCLKCRx
registers.
3.7.3.5 USB Bit Clock
The USB module requires a fixed 60MHz clock for bit sampling. When the PLLSYSCLK equals 150MHz, the
PLLCLK output is 300MHz, which can be divided down evenly by 5 to achieve the 60MHz requirement.
USB clock tolerances are very tight. As stated in section 7.1.11 of the USB 2.0 specification, low-speed devices
(1.50 b/s) have a tolerance of ±1.5% , while high-speed devices (12.000Mb/s) have a tolerance of ±0.25%.
Typically these tolerances are achieved by using an external crystal or resonator as the clock source for the
device.

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3.7.3.6 CAN Bit Clock

The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network
configuration, and can be as tight as 0.1%. Since the main system clock (in the form of SYSCLK) can not
be precise, the bit clock can also be connected to the AUXCLKIN path using the CLKSRCCTL2 register. There is
an independent selection for each CAN module.
To maintain correct operation, the frequency of the CAN bit clock must be less than or equal to the SYSCLK
frequency.
3.7.3.7 CLB Clock
Both the CLB registers and CLB tiles can be clocked directly from SYSCLK domain. There is additional option to
divide down PLLCLK directly and feed to one or both of the above depending on the system need.
3.7.3.8 LIN Clock
To give further granularity for the LIN module, an additional divider from SYSCLK can be implemented before the
clock reaches the LIN peripheral.
3.7.3.9 CPU Timer2 Clock (TIMER2CLK)
CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default, but
can also be connected to INTOSC1, INTOSC2, or XTAL using the TMR2CLKCTL register. This register also
provides a separate prescale divider for timer 2. If a non-SYSCLK source is used, the source must be divided
down to no more than half the SYSCLK frequency.
The main reason to use a non-SYSCLK source is for internal frequency measurement. In most applications,
timer 2 runs off of SYSCLK.
3.7.4 XCLKOUT
It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock
output (XCLKOUT) feature supports this by connecting a clock to an external pin, which can be GPIO16,
GPIO18, or GPIO71. GPIO16 has digital input and output functionality; so, to use it for monitoring XCLKOUT, the
register GPAAMSEL should be set to 0. The available clock sources are PLLSYSCLK, PLLRAWCLK, SYSCLK,
INTOSC1, INTOSC2, and XTAL.
To use XCLKOUT, first select the clock source using the CLKSRCCTL3 register. Next, select the desired output
divider using the XCLKOUTDIVSEL register. Finally, connect GPIO16 or GPIO18 to mux channel 11 using the
GPIO configuration registers.
3.7.5 Clock Connectivity
Table 3-7 shows the clock connections sorted by the clock domain and Table 3-8 shows the clock connections
sorted by the module name.

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Table 3-7. Clock Connections Sorted by Clock Domain

Clock Domain Module Name
CPUCLK FPU
TMU
SYSCLK ePIE
Boot ROM
CAN Bit Clock
DCSM
Flash
GPIO Input Sync and Qual
GSx RAMs
LSx RAMs
Mx RAMs
WD
XINT
PLLCLK CLB REG Clock
CLB TILE Clock
USB Bit Clock
PLLSYSCLK CPU
NMIWD
PERx.SYSCLK ADCA,B,C,D,E
AES
CLB
CMPSS1-4
DCC0-1
eCAP1-2
ePWM1-12
eQEP1-3
EPG
ERAD
FSI
GPDACA
HRCAL
I2CA,B
MCANA,B
PGA1-3
PMBUSA
Timer0-2
PERx.LSPCLK SCIA,B,C
SPIA,B
LINACLK LINA
CAN Bit Clock MCANA,B
USB Bit Clock USB
WDCLK (INTOSC1) Watchdog Timer

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Table 3-8. Clock Connections Sorted by Module Name

Module Name Clock Domain
ADCA,B,C,D,E PERx.SYSCLK
AES PERx.SYSCLK
Boot ROM SYSCLK
CAN Bit Clock SYSCLK
CLB PERx.SYSCLK
CLB_REG_CLK PLLCLK
CLB_TILE_CLK PLLCLK
CMPSS1-4 PERx.SYSCLK
CPU PLLSYSCLK
CPU Timers (0-2) PERx.SYSCLK
DCC0 PERx.SYSCLK
DCSM SYSCLK
eCAP1-2 PERx.SYSCLK
ePIE SYSCLK
ePWM1-12 PERx.SYSCLK
eQEP1-3 PERx.SYSCLK
EPG PERx.SYSCLK
ERAD PERx.SYSCLK
Flash SYSCLK
FPU CPUCLK
FSI PERx.SYSCLK
GPDAC PERx.SYSCLK
GPIO Input Sync and Qual SYSCLK
GSx RAMs SYSCLK
I2CA,B PERx.SYSCLK
LINA LINACLK
LSx RAMs SYSCLK
Mx RAMs SYSCLK
MCANA,B PERx.SYSCLK
NMIWD PLLSYSCLK
SCIA,B,C PERx.LSPCLK
SPIA,B PERx.LSPCLK
TMU CPUCLK
USB USBBITCLK
USB Bit Clock PLLCLK
Watchdog Timer WDCLK (INTOSC1)

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3.7.6 Clock Source and PLL Setup

The needs of the application are what ultimately determine the clock configuration. Specific concerns such
as application performance, power consumption, total system cost, and EMC are beyond the scope of this
document, but can provide answers to the following questions:
1. What is the desired CPU frequency?
2. Is CAN required?
3. What types of external oscillators or clock sources are available?
If CAN is required, an external clock source with a precise frequency must be used as a reference
clock;.otherwise, use only INTOSC2 and avoid the need for more external components.
3.7.7 Using an External Crystal or Resonator
The X1 and X2 pins double as GPIO19 and GPIO18. At power-up, these pins are in GPIO mode and the on-chip
crystal oscillator is powered off. The following procedure can be used to switch the pins to X1 and X2 mode and
enable the oscillator:
1. Clear the XTALCR.OSCOFF bit.
2. Wait for the crystal to power up. 1ms is the typical wait time but this depends on the crystal that is being
used.
3. Clear the X1 counter by writing a 1 to X1CNT.CLR and keep clearing until the X1 counter value in the
X1CNT register is no longer saturated 2047 (0x7FF).
4. Repeat steps 3-4 three additional times.
5. Wait for the X1 counter value in the X1CNT register to reach 2047 (0x7FF). Repeat steps 3-4 three
additional times.
6. Select XTAL as the OSCCLK source by writing a 1 to CLKSRCCTL1.OSCCLKSRCSEL.
7. Check the MCLKSTS bit in the MCDCR register. If it's set, the oscillator has not finished powering up, and
more time is required:
a. Clear the missing clock status by writing a 1 to MCDCR.MCLKCLR.
b. Repeat steps 2-7. Do not reset the device. Doing so powers down the oscillator, which requires the
procedure to be restarted from step 1.
c. If the oscillator has not finished powering up in 10 milliseconds, there is a real clock failure.
8. If MCDCR.MCLKSTS is clear, the oscillator startup is a success. The system clock is now derived from
XTAL.
3.7.7.1 X1/X2 Precondition Circuit
The GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of the crystal by as
much as 30% if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a
known state before the XTAL is turned on.
The steps below outline the procedure to precondition X1/X2 before turning on the XTAL:
1. ClkCfgRegs.XTALCR2.bit.XIF = 1; // Precondition X1 to High
2. ClkCfgRegs.XTALCR2.bit.XOF = 1; // Precondition X2 to High
3. ClkCfgRegs.XTALCR2.bit.FEN = 1; // Enable X1/X2 Precondition
4. DEVICE_DELAY_US(1);
5. ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Removes Precondition and Turns on the XTAL
6. ClkCfgRegs.XTALCR2.bit.FEN = 0; // Disables X1/X2 Precondition

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3.7.8 Using an External Oscillator

The procedure for using an external oscillator connected to the X1 pin is similar to the procedure for using a
crystal or resonator:
1. Clear the XTALCR.OSCOFF bit.
2. Set the XTALCR.SE bit to enable single-ended mode.
3. Clear the X1 counter by writing a 1 to X1CNT.CLR and keep clearing until the X1 counter value in the
X1CNT register is no longer saturated 2047 (0x7FF).
4. Wait for the X1 counter value in the X1CNT register to reach 2047 (0x7FF).
5. Repeat steps 3 and 4 three additional times.
6. Select XTAL as the OSCCLK source by writing a 1 to CLKSRCCTL1.OSCCLKSRCSEL.
7. Check the MCLKSTS bit in the MCDCR register. If the bit is set, either the external oscillator or the device
has failed.
8. If MCLKSTS is clear, the switch to the external clock is a success. The system clock is now derived from
XTAL.
3.7.9 Choosing PLL Settings
The equation shown in Figure 3-6 can be used to configure the PLL.
• IMULT is the integer value of the multiplier
• REFDIV is the reference divider for the OSCCLK
• ODIV is the output divider of the PLLRAWCLK
• PLLSYSCLKDIV is the system clock divider
For the permissible values of the multipliers and dividers, see the documentation for the respective registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the product of the
reference clock frequency and the multiplier (known as the VCO frequency) must be in the range specified in the
TMS320F28P55x Real-Time Microcontrollers Data Sheet.

Note
The system clock frequency (PLLSYSCLK) can not exceed the limit specified in the TMS320F28P55x
Real-Time Microcontrollers Data Sheet. This limit does not allow for oscillator tolerance.

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3.7.10 System Clock Setup

Once the application requirements are understood, a specific clock configuration can be determined. The default
configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1. The following
procedure can be used to set up the desired application configuration:
Refer to your device SysCtl_setClock() function inside C2000Ware installation for an example.
Recommended sequence to set up the system PLL:
1. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN]. Allow at least 60 NOP instructions for this to take
effect.
2. Power down the PLL by writing to SYSPLLCTL1.PLLEN = 0 and allow at least 60 NOP instructions for this to
take effect.
3. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL. Allow at least
300 NOP instructions for this to take effect.
4. Set the system clock divider to /1 to make sure the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
5. Set the IMULT, REFDIV, and ODIV simultaneously by writing 32-bit value in SYSPLLMULT at once. This
automatically enables the PLL. Be sure the settings for multiplier and dividers do not violate the frequency
specifications as defined in the TMS320F28P55x Real-Time Microcontrollers Data Sheet.
6. Wait for PLL to lock by polling for lock status bit to go high, SYSPLLSTS.LOCKS = 1
7. Configure DCC with reference clock as OSCCLK and clock under measurement as PLLRAWCLK, and verify
the frequency of the PLL. If the frequency is out of range, do not enable PLLRAWCLK as SYSCLK, stop
here and troubleshoot. Refer to Chapter 9 for more information on the configuration and usage.
8. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].

Note
1. SYSPLL must be bypassed and powered down manually before changing the OSCCLK source.
2. At least 60 CPU clock cycles delay is needed after bypassing PLL, SYSPLLCTL1.PLLCLKEN = 0.
3. At least 60 CPU clock cycles delay is needed after PLL is powered down, that is,
SYSPLLCTL1.PLLEN = 0.
4. At least 300 CPU clock cycles delay is needed after OSSCLK source is changed.
5. PLL SLIP bit is not supported. The DCC can be used to check the validity of the PLL clock. This
feature is included as part of SysCtl_setClock() function inside C2000Ware.

3.7.11 SYS PLL Bypass

If the application requires the PLL clock to be bypassed from the system, configure
SYSPLLCTL1.PLLCLKEN=0. It takes up to 60 CPU clock cycles before the bypass is effective. In the meantime
if PLLSYSCLKDIV is reduced to a lower value (for example from /2 to /1 or /4 to /2), the device can be clocked
above the maximum rated frequency and can lead to unpredictable device behavior. Hence, a delay of 60 CPU
clock cycles is required after bypassing the PLL from the enable state, that is, going from PLLCLKEN=1 to
PLLCLKEN=0.

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3.7.12 Clock (OSCCLK) Failure Detection

To achieve safety diagnostic, Missing Clock Detection (MCD) can be used. Table 3-9 lists the details.
Table 3-9. Clock Source (OSCCLK) Failure Detection
Clock Failure Time for Detection
Clocks Detected Limitations
Detection Circuitry (in Cycles)
Missing Clock Detection (MCD) INTOSC2, XTAL/X1 8192 INTOSC1 cycles Cannot detect INTOSC1 clock failure.

3.7.12.1 Missing Clock Detection

The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock source.
This circuit only detects complete loss of OSCCLK and does not perform any detection of frequency drift on the
OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10MHz clock provided by the INTOSC1 (secondary
clock) as a backup clock. This circuit functions as:
1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter is
asynchronously reset with XRSn.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This counter is
asynchronously reset with XRSn.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or is not
slower than INTOSC1 by a factor of 64, MCDSCNT never overflows.
4. If OSCCLK stops for some reason, or is slower than INTOSC1 by at least a factor of 64, the MCDSCNT
overflows and a missing clock condition is detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making the
MCLKOFF bit 1)
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCDSTS flag is set
• The MCDSCNT counter is frozen to prevent further missing clock detection
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs to
CPU1.NMIWD.
• PLL is forcefully bypassed and OSCCLK source is switched to INTOSC1 (New, System Clock Frequency
= INTOSC1 Freq 10MHz)/SYSDIV). In the meantime when the clock switches to INTOSC1, the System
runs on PLL limp Clock.
• SYSPLLMULT.IMULT is zeroed out automatically in this case.
• While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically
7. If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit is cleared and OSCCLK source is decided
by the OSCCLKSRCSEL bits. Writing to MCLKCLR also clears the MCDPCNT and MCDSCNT counters
to allow the circuit to re-evaluate missing clock detection. If the user wants to lock the PLL after missing
clock detection, switch the clock source to INTOSC1 (using OSCCLKSRCSEL register), do a MCLKCLR,
and re-lock the PLL.
8. The MCD is enabled at power up.
Figure 3-11 shows the missing clock logic functional flow.

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Figure 3-11. Missing Clock Detection Logic

Note
On a complete clock failure when OSCCLK is dead, it can take a maximum time of 8192 INTOSC1
cycles (that is, 0.8192ms) before the CLOCKFAIL signal goes high, after which:
• NMI is generated
• OSCCLK is switched to INTOSC1
• PWM Trip happens

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3.8 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU timers (TIMER0/1/2) shown in Figure 3-12.
Timer0 and Timer1 can be used in user applications. Timer2 is reserved for real-time operating system uses (for
example, TI-RTOS). If the application is not using an operating system that utilizes this timer, then Timer2 can be
used in the application. timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 3-13.
The general operation of a CPU timer is as follows:
• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD
• The counter decrements once every (TPR[TDDRH:TDDR] + 1) SYSCLK cycles, where TDDRH:TDDR is the
timer divider.
• When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 3.16 are used to configure the timers.

Figure 3-12. CPU Timers

A. The timer registers are connected to the memory bus of the C28x processor.
B. The CPU timers are synchronized to SYSCLKOUT.

Figure 3-13. CPU Timer Interrupt Signals and Output Signal

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3.9 Watchdog Timer

The watchdog module consists of an 8-bit counter sourced from a prescaled clock (WDCLK, which is
connected to INTOSC1). When the counter reaches the maximum value, the module generates an output pulse
512 WDCLKs wide. This pulse can generate an interrupt or a reset. The CPU must periodically write a 0x55 +
0xAA sequence into the watchdog key register to reset the watchdog counter. The counter can also be disabled.
The counter's clock is divided down from WDCLK by two dividers. The prescaler is adjustable from /1 to /64 in
powers of two. The pre-divider defaults to /512 for backwards compatibility, but is adjustable from /2 to /4096 in
powers of two. This allows a wide range of timeout values for safety-critical applications.
Figure 3-14 shows the various functional blocks within the watchdog module.

Figure 3-14. Watchdog Timer Module

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3.9.1 Servicing the Watchdog Timer

The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register before
the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is written to the
WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is reset. Any value
written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55 and 0xAA values can
be written to the WDKEY without causing a system reset; only a write of 0x55 followed by a write of 0xAA to the
WDKEY resets the WDCNTR.
The first action that enables the WDCNTR to be reset is shown in Step 3 in Table 3-10. The WDCNTR is not
actually reset until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR.
Step 10 again re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes no action, however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now has no
effect.
If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to the
WDCR[WDCHK] bits resets the device and sets the watchdog flag (WDRSn) in the reset cause register (RESC).
After a reset, the program can read the state of this flag to determine whether the reset was caused by the
watchdog. After doing this, the program can clear WDRSn to allow subsequent watchdog resets to be detected.
Watchdog resets are not prevented when the flag is set.
Table 3-10. Example Watchdog Key Sequences
Step Value Written to WDKEY Result
1 0xAA No action
2 0xAA No action
3 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
4 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
5 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
6 0xAA WDCNTR is reset.
7 0xAA No action
8 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
9 0xAA WDCNTR is reset.
10 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
11 0x32 Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.
12 0xAA No action due to previous invalid value.
13 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
14 0xAA WDCNTR is reset.

3.9.2 Minimum Window Check

To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that bypass
large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This value
takes effect after the next WDKEY sequence. From then on, any attempt to service the watchdog when
WDCNTR is less than WDWCR triggers a watchdog interrupt or reset. When WDCNTR is greater than or equal
to WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.

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3.9.3 Watchdog Reset or Watchdog Interrupt Mode

The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an interrupt
(WDINT), if the watchdog counter reaches the maximum value. The behavior of each condition is:
• Reset mode: If the watchdog is configured to reset the device, then the WDRST signal pulls the device reset
(XRS) pin low for 512 INTOSC1 cycles when the watchdog counter reaches the maximum value.
• Interrupt mode: When the watchdog counter expires, the counter asserts an interrupt by driving the WDINT
signal low for 512 INTOSC1 cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE, if
the interrupt is enabled. Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active
does not produce a duplicate interrupt.
To avoid unexpected behavior, software must not change the configuration of the watchdog while WDINT is
active. For example, changing from interrupt mode to reset mode while WDINT is active immediately resets
the device. Disabling the watchdog while WDINT is active causes a duplicate interrupt, if the watchdog is
later re-enabled. If a debug reset is issued while WDINT is active, the reset cause register (RESC) shows a
watchdog reset. The WDINTS bit in the SCSR register can be read to determine the current state of WDINT.

3.9.4 Watchdog Operation in Low-Power Modes

Note
If the watchdog interrupt is used to wake-up from an IDLE low-power mode condition, software must
make sure that the WDINT signal goes back high before attempting to reenter the IDLE mode. The
WDINT signal is held low for 512 INTOSC1 cycles when the watchdog interrupt is generated. The
current state of WDINT can be determined by reading the watchdog interrupt status bit (WDINTS) bit
in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.

In IDLE mode, the watchdog interrupt (WDINT) signal can generate an interrupt to the CPU to take the CPU out
of IDLE mode. As with any other peripheral, the watchdog interrupt triggers a WAKE interrupt in the PIE during
IDLE mode. User software must determine which peripheral caused the interrupt.
In HALT mode, the internal oscillators and watchdog timer are kept active if the user sets
CLKSRCCTL1.WDHALTI = 1. A watchdog reset can wake the system from HALT mode, but a watchdog
interrupt cannot.
3.9.5 Emulation Considerations
The watchdog module behaves as follows under various debug conditions:

CPU Suspended When the CPU is suspended, the watchdog clock (WDCLK) is
suspended.
Run-Free Mode When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the watchdog clock
(WDCLK) is suspended. The watchdog remains suspended even within
real-time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the watchdog operates as
normal.

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3.10 Low-Power Modes

This device has HALT, IDLE, and STANDBY as clock-gating low-power modes.
All low-power modes are entered by setting the LPMCR register and executing the IDLE instruction. More
information about this instruction can be found in the TMS320C28x CPU and Instruction Set Reference Guide.
Low-power modes must not be entered into while a Flash program or erase operation is ongoing. Entering
HALT stops all CPU and peripheral activities. This includes active transmissions and control algorithms. When
preparing to enter HALT mode, the application must make sure that the system is prepared to enter a period of
inactivity.
Before entering HALT mode, check the value of the GPIODAT register of the pin selected for HALT wake-up
(GPIOLPMSEL0/1) prior to entering the low-power mode to make sure that the wake event has not already been
asserted.
3.10.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 3-11 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 3-11. Effect of Clock-Gating Low-Power Modes on the Device
Modules/
IDLE STANDBY HALT
Clock Domain
SYSCLK Active Gated Gated
CPUCLK Gated Gated Gated
Clock to modules connected Active Gated Gated
to PERx.SYSCLK
WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
PLL Powered Powered Software must power down PLL before entering HALT.
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash(1) Powered Powered Powered
XTAL(2) Powered Powered Powered

(1) The Flash module is not powered down by hardware in any LPM. The Flash module can be powered down using software if required
by the application. For more information, see the Flash Module chapter.
(2) The XTAL is not powered down by hardware in any LPM. The XTAL can be powered down using software by setting the
XTALCR.OSCOFF bit to 1. This can be done at any time during the application if the XTAL is not required.

3.10.2 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral clocks are
left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral events.
Any enabled interrupt wakes up the CPU from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.
The CPU resumes normal operations upon any enabled interrupt event.

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3.10.3 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU's SYSCLK. The watchdog however, is left active. STANDBY is best suited for an
application where the wake-up signal comes from an external system (or CPU subsystem) rather than a
peripheral input.
An NMI (or optionally) a watchdog interrupt or a configured GPIO can wake the CPU from STANDBY mode.
Each GPIO can be configured to wake up the CPU when the GPIOs are driven active low. Upon wake up, the
CPU receives the WAKEINT interrupt if configured.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from STANDBY mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; the signal must remain low for the number of OSCCLK cycles specified
in the QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count
restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt is
latched in the PIE block.
The CPU is now out of STANDBY mode and can resume normal execution.

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3.10.4 HALT
HALT is a global low-power mode that gates almost all system clocks and allows for power-down of oscillators
and analog blocks.
Unlike on other C2000™ devices, HALT mode does not automatically power down the XTAL upon HALT entry.
Additionally, if the XTAL is not powered on, waking up from HALT mode does not automatically power on the
XTAL. The XTALCR.OSCOFF bit has been added to power on and off the XTAL circuitry when not needed
through application software.
For applications that require minimal power consumption during HALT mode, application software can power off
the XTAL prior to entering HALT. If the OSCCLK source is configured to be XTAL, the application can first switch
the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.
Each GPIO can be configured to wake up the system from HALT. No other wake up option is available. However,
the watchdog timer can still be clocked, and can be configured to produce a watchdog reset if a timeout
mechanism is needed. On wake up, the CPU receives a WAKEINT interrupt.
To enter HALT mode:
1. Enable the WAKEINT interrupt in the PIE.
2. Set LPMCR.LPM to 0x2. Set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module.
3. Set CLKSRCCTL1.WDHALTI to 1 to keep the watchdog timer active and INTOSC1 and INTOSC2 powered
up in HALT.
4. Set CLKSRCCTL1.WDHALTI to 0 to disable the watchdog timer and power down INTOSC1 and INTOSC2 in
HALT.
5. Execute the IDLE instruction to enter HALT.
If an interrupt or NMI is received while the IDLE instruction is in the pipeline, the system begins executing the
WAKEINT ISR. After HALT wake up, ISR execution resumes where execution left off.

Note
Before entering HALT mode, if the system PLL is locked (SYSPLL.LOCKS = 1), the PLL must also be
connected to the system clock (PLLCTL1.PLLCLKEN = 1). Otherwise, the device never wakes up.

To wake up from HALT mode:

1. Drive the selected GPIO low for a minimum 5µs. This activates the WAKEINT PIE interrupt.
2. Drive the wake-up GPIO high again to initiate the powering up of the SYSPLL.
3. Wait 16µs plus 1024 OSCLK cycles to allow the PLLs to lock and the WAKEINT ISR to be latched.
4. Execute the WAKEINT ISR.
The device is now out of HALT mode and can resume normal execution.

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3.11 Memory Controller Module

On this device, the RAMs have different characteristics. These are:
• Dedicated to the CPU: M0 and M1 RAMs
• Shared between the CPU and CLA: LSx RAMs
• Shared between the CPU, DMA, and NPU: GSx RAMs
• Used to send and receive messages between the processors: MSG RAMs
All these RAMs are highly configurable to achieve control for write access and fetch access from different
peripherals. All dedicated RAMs are enabled with the ECC feature (both data and address) and shared RAMs
are enabled with the parity feature (both data and address). Some of the dedicated memories are secure
memory as well. Refer to Chapter 5 for more details. Each RAM has a controller that takes care of the
access protection and security related checks and ECC/Parity features for that RAM. Figure 3-15 shows the
configuration of these RAMs.

LSx RAM GSx RAM

CPU
CPU TO CLA MSGRAM M0/M1
CLA
CLA TO CPU MSGRAM RAM
DMA TO CLA MSGRAM
DMA NPU
CLA TO DMA MSGRAM

Figure 3-15. Memory Architecture

3.11.1 Functional Description

This section further defines and discusses the dedicated and shared RAMs on this device.
3.11.1.1 Dedicated RAM (Mx RAM)
This device has two dedicated RAM blocks: M0 and M1. M0 and M1 memories are small blocks of memory
which are tightly coupled with the CPU. Only the CPU has access to these memories.
All dedicated RAMs have the ECC feature.
3.11.1.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are secure memories and have ECC. These memories are shared between
the CPU and CLA but are by default dedicated to the CPU only. CLA access can be enabled by configuring
MSEL_LSx bit field in the LSxMSEL register.
Further, when these memories are shared between the CPU and CLA, the user can choose to use these
memories as CLA program memory by configuring the CLAPGM_LSx bit field in the LSxCLAPGM registers.
CPU access to all memory blocks, which are programmed as CLA program memory, are blocked.
All these RAMs have the access protection (CPU write and CPU fetch) feature. Each type of access protection
for each RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM access
protection registers, mapped to each CPU subsystem. Table 3-12 shows the LSx RAM features.

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Table 3-12. Local Shared RAM

MSEL_LSx CLAPGM_LSx CPUx CPUx.CLA1 Comment
Allowed Access Allowed Access

00 X All - LSx memory is configured as CPU dedicated RAM

01 0 All Data Read LSx memory is shared between CPU and CLA1
Data Write

01 1 Emulation Read Fetch Only LSx memory is CLA1 program memory

Emulation Write Emulation Read
Emulation Write

3.11.1.3 Global Shared RAM (GSx RAM)

RAM blocks that are accessible from the CPU and DMA are called global shared RAMs (GSx RAMs). Table 3-13
shows the features of the GSx RAM.
Table 3-13. Global Shared RAM
CPU (Fetch) CPU (Read) CPU (Write) CPU.DMA CPU.DMA NPU (Read) NPU (Write)
(Read) (Write)
Yes Yes Yes Yes Yes Yes Yes

The shared RAM has different levels of access protection that can be enabled or disabled by configuring specific
bits in the GSxACCPROT registers.
Access protection configuration for the GSx RAM block can be locked by the user to prevent further updates to
this bit field. The user can also choose to permanently lock the configuration to individual bit fields by setting
the specific bit fields in the GSxCOMMIT register (refer to the register description for more details). Once a
configuration is committed for a particular GSx RAM block, the configuration can not be changed further until
CPU.SYSRS is issued.

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3.11.1.4 CAN Message RAM

Note
Control of the CAN message RAMs can only be given to the CPU if the MCAN module is not used by
the system. The reset source for the MCANRAMACC register is PORSn (Power On Reset) and not
XRSn. This is to align the behavior with other CPU controlled RAMs. It is not recommended to change
the MCANRAMACC bit once the bit is set, as the contents of the RAM are not compatible with the
MCAN module. Even if the MCAN module is only used for boot purposes, it is not recommended to
change the ownership to the CPU.

Each MCAN module has 4KB of message RAM embedded locally and exclusively accessible by the MCAN
module.
In systems that do not use one or both MCAN modules, there is the ability to re-assign the RAM to the CPU
memory domain in data space only. The MCANRAMACC register in the Section 3.16.11 provides control of each
MCAN instance RAM assignment individually. Once set, the MCAN module has no access to these RAMs. If the
MCAN module is used at all in the system, it is not recommended to allocate this RAM to the CPU.
The C28x is a 16-bit word based CPU, as such the addressable memory is reduced to 2KB in size as shown in
Table 3-14.
Table 3-14. Addressable Memory Range for MCAN Message RAMs
MCANRAMACC MCANA Memory Addresses MCANB Memory Addresses
0 (owned by MCAN) 0x58000-0x58FFF 0x5A000-0x5AFFF
1 (owned by C28x) 0x58000-0x587FF 0x5A000-0x5A7FF

3.11.1.5 CLA-CPU Message RAM

These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU
and CLA both have read access to both MSGRAMs.
3.11.1.6 CLA-DMA Message RAM
These RAMs blocks can be used to share data between CLA and DMA. The CLA has read and write access to
the "CLA to DMA MSGRAM." The DMA has read and write access to the "DMA to CLA MSGRAM." The CLA
and DMA both have read access to both MSGRAMs.

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3.11.1.7 Access Arbitration

For a shared RAM, multiple accesses can happen at any given time. The maximum number of accesses to any
shared RAM at any given time depends on the type of shared RAM. On this device, a combination of a fixed and
alternating scheme is followed to arbitrate multiple access at any given time.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch
Figure 3-16 represents the arbitration scheme on local shared memories.
Figure 3-17 represents the arbitration scheme on global shared memories

Figure 3-16. Arbitration Scheme on Local Shared Memories

C28x CPU
Fixed Round Robin Arbitra
on
DATA WRITE

CPU RR CPU
DATA READ Fixed
Priority
Arbiter
PROGRAM
READ/FETCH

RR NPU RR DMA

DMA READ/WRITE

Figure 3-17. Arbitration Scheme on Global Shared Memories

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3.11.1.8 Access Protection

All RAM blocks except for M0/M1 have different levels of protection. This feature allows the user to enable
or disable specific access to individual RAM blocks from individual controllers. There is no protection for read
accesses, hence reads are always allowed from all the controllers which have access to that RAM block.
The following sections describe the different kinds of protection available for RAM blocks on this device.

Note
For debug accesses, all the protections are disabled.

3.11.1.8.1 CPU Fetch Protection

Fetch accesses from the CPU can be protected by setting the FETCHPROTx bit of the specific register to 1. If
fetch access is done by the CPU to a memory where CPU fetch protection is enabled, a fetch protection violation
occurs.
If a fetch protection violation occurs, the violation results in an ITRAP for the CPU. A flag gets set in the
appropriate access violation flag register, and the memory address for which the access violation occurred, gets
latched into the appropriate CPU fetch access violation address register.
3.11.1.8.2 CPU Write Protection
Write accesses from the CPU can be protected by setting the CPUWRPROTx bit of the specific register to 1. If
write access is done by a CPU to memory where the write is protected, a write protection violation occurs.
If a write protection violation occurs, the write gets ignored, a flag gets set in the appropriate access violation flag
register, and the memory address for which the access violation occurred, gets latched into the appropriate CPU
write access violation address register. Also, an access violation interrupt is generated if enabled in the interrupt
enable register.
3.11.1.8.3 CPU Read Protection
If a read protection violation occurs, a flag gets set in the appropriate access violation flag register, and the
memory address for which the access violation occurred, gets latched in the appropriate CPU read access
violation address register. Also, an access violation interrupt is generated, if enabled in the interrupt enable
register.
3.11.1.8.4 CLA Fetch Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as data RAM for
the CLA, any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation,
which is a non-controller access violation.
If a CLA fetch protection violation occurs, the violation results in a MSTOP. A flag gets set in the appropriate
access violation flag register, and the memory address for which the access violation occurred, gets latched in
the appropriate CLA fetch access violation address register. Also, an access violation interrupt is generated to
the CPU if enabled in the interrupt enable register.
3.11.1.8.5 CLA Write Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as program RAM
for the CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection
violation, which is a non-controller access violation.
If a CLA write protection violation occurs, the write gets ignored, a flag gets set in the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched in the
appropriate CLA write access violation address register. Also, an access violation interrupt is generated to the
CPU if enabled in the interrupt enable register.

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3.11.1.8.6 CLA Read Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as program RAM
for the CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection
violation, which is a non-controller access violation.
If a CLA read protection violation occurs, a flag gets set in the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched in the appropriate CLA read access
violation address register. Also, an access violation interrupt is generated to the CPU if enabled in the interrupt
enable register.
3.11.1.8.7 DMA Write Protection
Write accesses from the DMA can be protected by setting the DMAWRPROTx bit of a specific register to 1. If a
write access is done by the DMA to protected memory, a write protection violation occurs.
If a write access is made to a dedicated or shared memory by a DMA, and DMAWRPROTx is set to 1 for that
memory, the write is called a DMA write protection violation.
A flag gets set in the DMA access violation flag register, and the memory address where the violation happened
gets latched in the DMA fetch access violation address register. These are dedicated registers for each
subsystem.

Note 1: All access protections are ignored during debug accesses. Write access to a protected
memory go through when the write is done using the debugger, irrespective of the write
protection configuration for that memory.
Note 2: Access protection is not implemented for M0 and M1 memories.

3.11.1.8.8 NPU Write Protection

Write accesses from the NPU module can be protected by setting the NPUWRPROTx bit of a specific register to
1. If a write access is done by the NPU module to protected memory, a write protection violation occurs.
If a write access is made to a dedicated or shared memory by the NPU module, and NPUWRPROTx is set to 1
for that memory, the write is called a NPU write protection violation.
A flag gets set in the NPU access violation flag register, and the memory address where the violation happened
gets latched in the NPU fetch access violation address register. These are dedicated registers for each
subsystem.

Note 1: All access protections are ignored during debug accesses. Write access to a protected
memory go through when the write is done using the debugger, irrespective of the write
protection configuration for that memory.

3.11.1.9 Memory Error Detection, Correction, and Error Handling

These devices have memory error detection and correction features to satisfy safety standards requirements.
These requirements warrant the addition of detection mechanisms for finite dangerous failures.
In this device, all dedicated RAMs support error correction code (ECC) protection and the shared RAMs have
parity protection. The ECC scheme used is Single Error Correction Double Error Detection (SECDED). The
parity scheme used is even parity. ECC/Parity covers the data bits stored in memory as well as address.
ECC/Parity calculation is done inside the memory controller module and calculated. ECC/Parity is written into the
memory along with the data. ECC/Parity is computed for 16-bit data; hence, for each 32-bits of data, there are
three 7-bit ECC codes (or 3-bit parity), two of which are for data and a third one for the address.

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3.11.1.9.1 Error Detection and Correction

Error detection is done while reading the data from memory. The error detection is performed for data as well as
address. For parity memory, only a single-bit error gets detected, whereas in case of ECC memory, along with
a single-bit error, a double-bit error also gets detected. These errors are called correctable and uncorrectable
errors. The following are characteristics of these errors:
• Parity errors are always uncorrectable errors
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors
• Address ECC errors are also uncorrectable errors
Correctable errors get corrected by the memory controller module and then the correct data is given back as
read data. The correct data is also written back into the memory to prevent a double-bit error due to another
single-bit error at the same memory address.
3.11.1.9.2 Error Handling
For each correctable error, the count in the correctable error count register increments by one. When the value in
this count register becomes equal to the value configured in the correctable error threshold register, an interrupt
is generated to the CPU, if the interrupt is enabled in the correctable interrupt enable register. The user needs to
configure the correctable error threshold register based on the system requirements. Also, the address for which
the error occurred, gets latched into a register and a flag also gets set in a status register.
If there are uncorrectable errors, an NMI gets generated for the CPU. In this case also, the address for which the
error occurred gets latched into a register, and a flag gets set in a status register.
Table 3-15 summarizes different error situations that can arise. These need to be handled appropriately in the
software, using the status and interrupt indications provided.
Table 3-15. Error Handling in Different Scenarios
Access Type Error Found In Error Type Status Indication Error Notification
Reads Data read from Uncorrectable Error Yes - CPU Read Error Address Register NMI for CPU access
memory (Single-bit error for Data returned to CPU is incorrect
Parity RAMs OR
Double bit Error for
ECC RAMs)
Reads Data read from Single-bit error for Yes - CPU Read Error Address Register Interrupt when error counter reaches the
memory ECC RAMs Increment single error counter user programmable threshold for single
errors
Reads Data read from PIE Parity error Yes - PIE Parity Error sets bit in Bit set in MEM_CFG_REGS
memory MEM_CFG_REGS
Reads Address Address error Yes - CPU Read Address Error Register NMI to CPU for CPU access
Data returned to CPU is incorrect

Note
In the case of an uncorrectable error during fetch on the CPU, there is the possibility of getting an
ITRAP before an NMI exception, since garbage instructions enter into the CPU pipeline before the
NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.

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3.11.1.10 Application Test Hooks for Error Detection and Correction

Since error detection and correction logic is part of safety critical logic, safety applications need to make sure
that the logic is always working fine (during run time also). To enable this, a test mode is provided, in which
a user can modify the data bits (without modifying the ECC/Parity bits) or ECC/Parity bits directly. Using this
feature, an ECC/Parity error can be injected into data.

Note
The memory map for ECC/Parity bits and data bits are the same. The user must choose a different
test mode to access ECC/Parity bits. In test mode, all access to memories (data as well as ECC/
Parity) can be done as 32-bit access only.

Table 3-16 and Table 3-17 show the bit mapping for the ECC/Parity bits when the bits are read in RAMTEST
mode using the respective addresses.
Table 3-16. Mapping of ECC Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (ECC Memory)
6:0 ECC Code for lower 16 bits of data
7 Not Used
14:8 ECC Code for upper 16 bits of data
15 Not Used
22:16 ECC Code for address
31:23 Not Used

Table 3-17. Mapping of Parity Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (Parity Memory)
0 Parity for lower 16 bits of data
7:1 Not Used
8 Parity for upper 16 bits of data
15:9 Not Used
16 Parity for address
31:17 Not Used

3.11.1.11 RAM Initialization

To make sure that a read/fetch from uninitialized RAM locations do not cause ECC or parity errors, the
RAM_INIT feature is provided for each memory block. Using this feature, any RAM block can be initialized
with 0x0 data and the respective ECC/Parity bits accordingly. This can be initiated by setting the INIT bit to 1
for the specific RAM block in INIT registers. To check the status of RAM initialization, software must poll for the
INITDONE bit for that RAM block in the INITDONE register to be set. Unless this bit gets set, no access can be
made to that RAM memory block.

Note
None of the hosts must access the memory while initialization is taking place. If memory is accessed
before RAMINITDONE is set, the memory read/write as well as initialization does not happen
correctly.

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3.12 JTAG
Gel files perform certain initialization tasks. This helps the users in a debug environment. However, when
executed standalone (without the emulator connected) the application can not work as expected, since there is
no gel file to perform those initializations. For example, gel file disables watchdog. If user code does not service
the watchdog in the application (or fails to disable the watchdog), there is a difference in how the application
behaves with the debugger and without the debugger.
Common tasks performed by the gel files (but not boot-ROM):
• On Reset:
– Disable Flash ECC on some devices.
• Disabling ECC only when using Flash API functions, see the Flash API User Guide for details.
Otherwise, TI suggests to always program ECC and enable ECC-check.
– Disable Watchdog
– Enable CLA clock
– Select real-time mode or C28x mode
• On Restart:
– Select real-time mode or C28x mode
– Clear IER and IFR
• On Target Connect:
– Select real-time mode or C28x mode

For more information, see C2000 MCU JTAG Connectivity Debug.

3.12.1 JTAG Noise and TAP_STATUS
The TAP_STATUS register reflects the status of the JTAG TAP at any given time. Normally when no JTAG
is connected to the device, the status can be IDLE. In some cases with excessive PCB noise, there can be
unwanted TMS and TCK toggles that take JTAG out of the IDLE state. When persistent, this can ultimately
lead to unwanted activation of the JTAG Boundary Scan or some other JTAG mode that can interfere with the
intended application. To avoid this scenario, place strong enough pull resistors on the board to prevent noise
from activating JTAG. As a debug tool, the TAP_STATUS register can be polled by the application code to detect
if this is a cause of device disturbance. The SOFTPRES40[JTAG_nTRST] register can also be used to reset the
JTAG TAP through software. Use this reset register with caution, as this prevents connecting a debugger unless
the code qualifies writes to this register with some other GPIO state or other means to distinguish between noise
and debugger accesses.
The TAP_CONTROL register can be used to disable the TAP state machine's control of the device. Using the
TAP_CONTROL register can help to prevent noise from activating JTAG.
3.13 Live Firmware Update
This device includes hardware hooks to streamline firmware updates. These hardware hooks enable seamless
switching from the old firmware to the new firmware without resetting the application.
This section discusses the Live Firmware Update (LFU) and the hardware features present on the device to
support LFU.
3.13.1 LFU Background
End equipment like Server Power Supply (PSU) are high availability systems that need to have minimum
downtime, even during firmware upgrades. Firmware upgrades are essential to add additional functionality,
enhance performance and fix software bugs/vulnerabilities. LFU helps update firmware while the application
is running, thus eliminating downtime (with respect to critical real-time interrupts) and also providing a more
cost-effective alternative compared to manually updating firmware.
LFU has traditionally been implemented in the C2000 family of MCUs using software-only techniques. This
impacts LFU switchover time, which is the time to switchover to new firmware once the transition has begun.

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User application code initiates this transition, typically by jumping to an entry point in the new firmware. There,
a compiler provided initialization routine specific to LFU is called. This initializes user-specified data variables.
When execution arrives in main() of the new application, user application code performs minimal initialization to
get the new application running.
3.13.2 LFU Switchover Steps
A simplified representation of the LFU switchover is shown in Figure 3-18 and is described in the following steps:
1. In typical systems, a host – typically a PC or another MCU, initiates the LFU (depicted as LFU Request) on
the application MCU (in this case, the C2000 MCU) that is executing the real-time control application. This
initiates the Flash Program sequence in the application MCU. This runs as a background process even as
the application MCU continues executing firmware (depicted as Firmware - 1).
2. Since the compiler can move existing PIE vectors and function pointers to new locations between firmware
versions, PIE vectors or function pointers can get added or removed between firmware versions. User
application code needs to manage these properly and efficiently during LFU. In the absence of Flash
remapping (where different Flash memory banks can be mapped to the same address), PIE vector table
remapping, that is “swapping” and RAM memory block swapping are features supported on the device.
Without swapping, user application code needs to individually update each PIE vector and each function
pointer, adding valuable cycles to the LFU switchover time. With swapping, prior to LFU switchover, user
application code can populate a different PIE vector table (depicted as PIE Swap Memory Update) and a
different LS RAM region (depicted as LSx Swap Memory Update).
3. When complete (depicted as LFU Switchover – waiting for appropriate time), user application code initiates
the transition to new firmware. Once the compiler LFU initialization routine completes and transfers
execution to the new application (depicted as Firmware – 2), user application code needs to perform
necessary initialization before the new application can begin running. Since PIE vectors and function
pointers have already been populated in the “swap” locations, all that is required is a PIE vector table
swap and LSx RAM Memory Swap (depicted as PIE Vector Swap, LSx Memory Swap).

LFU switchover - waiting PIE vector swap

LFU Request for appropriate time LSx Memory swap

PIE swap LSx swap

Flash Program
Memory update Memory update
Compiler LFU
Firmware - 1 Initialization Firmware - 2
Routine

Figure 3-18. Simplified LFU Representation

3.13.3 Device Features Supporting LFU

The new hardware capabilities implemented in the device to support LFU are:
1. Multi-Bank Flash
2. PIE Vector Table Swap
3. LS0/LS1 RAM Memory Swap

3.13.3.1 Multi-Bank Flash

The device has up to five Flash banks, the maximum bank size is 256KB, with support for 128KB and 64KB
banks based on the device part number (see the TMS320F28P55x Real-Time Microcontrollers Data Sheet for
this information). With multiple banks, you can Program/Erase a bank while other banks are in read mode.

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3.13.3.2 PIE Vector Table Swap

The device contains an additional PIE vector table, in addition to the typical PIE vector table that is present.
This allows PIE vector addresses for the new firmware to be populated prior to the LFU switchover. During LFU
switchover, a simple swap operation which activates the PIE vector swap table and deactivates the previously
active PIE vector table is initiated by user application code, and this operation takes just 1 CPU clock cycle. To
initiate the swap, user application code sets LFUConfig.PieVectorSwap = 1. The PIE vector table swap features
are also implemented on a redundant PIE vector table implemented for safety. Therefore, to implement PIE
vector table swap, the sizes of PIE vector memory and redundant PIE vector memory are both doubled.
The changes are summarized in Figure 3-19. In this device, there exists a duplicate PIE RAM mapped to
a different memory address. There are now two physical PIE vector RAM memories – PIE-1 and PIE-2. By
default, PIE-1 is active, and mapped to addresses 0x0000_0D00-0x0000_0EFF. PIE-2 is inactive, and mapped
to addresses 0x0100_0900-0x0100_0AFF.
When user application code initiates a PIE vector table swap by setting LFUConfig.PieVectorSwap = 1, PIE-2
becomes active, and is mapped to addresses 0x0000_0D00-0x0000_0EFF. PIE-1 becomes inactive, and is
mapped to addresses 0x0100_0900-0x0100_0AFF.
Note that the PIE vector RAM active addresses are always 0x0000_0D00-0x0000_0EFF. The inactive addresses
are always 0x0100_0900-0x0100_0AFF. As mentioned above, prior to the LFU switchover, user application code
needs to write to the inactive addresses with the PIE vector locations corresponding to the new firmware.
The register bit LFUStatus.PieVectorSwap provides the status of Pie Vector Swap.
The PIE vector RAM utilizes a parity scheme to detect address and data errors.
PIE Vector Map PIE Vector Map
Before Swap A er Swap

0x0000 0D00 0x0100 0900

Ac
ve Vector Table

PIE-1 PIE-1 Inac ve Vector Table,

ready for swap

0x0000 0EFF 0x0100 0AFF

0x0100 0900 0x0000 0D00

PIE-2 PIE-2

0x0100 0AFF 0x0000 0EFF

Figure 3-19. PIE Vector Table Swap

3.13.3.3 LS0/LS1 RAM Memory Swap

Similar to PIE Vector Table Swap, LS0 and LS1 physical RAM memory blocks can also be swapped. The
memory architecture is similar to PIE vector table swap, and is shown in Figure 3-20. By default, physical Block
1 is assigned to addresses 0x8000-0x87FF (that is, the address range for LS0), and physical Block 2 is assigned
to addresses 0x8800-0x8FFF (that is, the address range for LS1). By configuring LFUConfig.LS01Swap
= 1, user application code can execute a swap, where physical Block 2 is now assigned to addresses
0x8000-0x87FF (that is, the address range for LS0), and physical Block 1 is now assigned to addresses
0x8800-0x8FFF (that is, the address range for LS1).

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If physical memory Block 1 contains function pointers for the current firmware, the same relative locations in
physical memory Block 2 can be populated with function pointers for the new firmware prior to LFU switchover.
During LFU switchover, a simple swap operation is initiated by user application code, and this operation takes
just 1 CPU clock cycle. This allows user application code to always have function pointers in LS0, yet have two
different physical blocks that can map to the LS0 address range.
For example, if current firmware contains 10 function pointers present at the start of Block 1 (LS0 address
space). If the new firmware contains the same 10 function pointers that now need to be updated, user
application code can place these at the start of Block 2 (LS1 address space) prior to LFU switchover. During
LFU switchover, user application code executes a LS0/LS1 RAM memory swap, where the physical RAM block
previously mapped to the LS1 address space can now be mapped to the LS0 address space, and hence can be
used seamlessly for function pointer addressing for the new firmware.
The register bit LFUStatus.LS01Swap provides the status of LS0/LS1 RAM memory swap.

Figure 3-20. LS0/LS1 RAM Memory Swap

Additional points pertaining to LS0/LS1 RAM memory swap are:

1. LFU registers can be accessed from both CPU and CLA.
2. Only LS0 and LS1 blocks can be swapped. LS2 to LS7 blocks cannot be swapped.
3. LS0 and LS1 blocks have parity protection. Address parity is computed based on the physical address and
hence the address does not change based on the memory swap.
4. A number of LSx RAM registers are available to the user application code
to configure options such as select (LSxMSEL.MSEL_LS0, LSxMSEL.MSEL_LS1), fetch
protect (LSxACCPROT0.FETCHPROT_LS0, LSxACCPROT0.FETCHPROT_LS1), write protect
(LSxACCPROT0.CPUWRPROT_LS0, LSxACCPROT0.CPUWRPROT_LS1), CLA program memory
LSxCLAPGM.CLAPGM_LS0, LSxCLAPGM.CLAPGM_LS1). These register bits indicate the status of the
memory block that is deemed as LS0 (CPU address 0x8000 to 0x87FF) and LS1 (CPU address 0x8800 to
0x8FFF) at any point of time. When a LS0/LS1 RAM memory swap occurs, the corresponding control/status
bits also automatically swap.
5. Service all pending errors (access violation and parity) associated with the memory before initiating a
LS0/LS1 RAM memory swap.
6. LS0/LS1 RAM memory swap shall be initiated only after completion of RAM initialization for both LS0 and
LS1 memories (LSxINITDONE.INITDONE_LS0 = 1 and LSxINITDONE.INITDONE_LS1 = 1).

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7. LS0/LS1 RAM memory swap shall not be initiated when RAM-test (LSxTEST.TEST_LS0 = 1 or
LSxTEST.TEST_LS1 = 1) is in progress for LS0 or LS1 blocks.
8. With DCSM security on the device, in general, LS0 and LS1 RAM blocks can be assigned to different
security zones. However, with LS0/LS1 RAM memory swaps, different physical RAM blocks can get mapped
to the same address space. Application software shall therefore make sure that both LS0 and LS1 have the
same security settings (for example, zone, EXE protection), if there is a plan to implement LS0/LS1 RAM
memory swap. Hardware logic is implemented on the device to prevent swap of LS0 and LS1 if the blocks
have different security configurations.
9. To prevent security vulnerabilities, LS0/LS1 RAM memory swap is not allowed if the memory swap is
initiated by code from a different zone. For example:
• if LS0 and LS1 are part of Zone1, the swap is not allowed if the code that initiates the swap resides in
Zone2 or unsecure zone
• if LS0 and LS1 are part of Zone2, the swap is not allowed if the code that initiates the swap resides in
Zone1 or unsecure zone
• if LS0 and LS1 are part of the same zone that is unsecure, the swap is allowed in all cases irrespective of
where the code that initiates the swap resides
• if LS0 and LS1 are part of the same zone and is unlocked, the swap can be initiated from code residing
anywhere (including from the debugger)
10. Once the swap is initiated, the swap happens in the next cycle, subject to the swap meeting the security
requirements previously mentioned. After initiation of a swap, application software shall check if the swap
was correctly configured by checking the LFUStatus.LS01Swap status register. Consistency between
LFUStatus.LS01Swap and LFUConfig.LS01Swap helps determine if the swap was correctly configured. If
LFUStatus.LS01Swap does not match LFUConfig.LS01Swap, LFUConfig.LS01Swap needs to be cleared by
user application code.

3.13.3.3.1 Applicability to CLA LFU

The device does not support a swap table for the CLA task vectors (MVECTs). CLA LFU is implemented typically
on the CPU side, where the MVECTs are updated sequentially at an appropriate time. The techniques for
when to update the MVECTs are described in the LFU system reference design guide, but noted here that the
approach is different from the CPU PIE vector table case, where a simple single cycle swap achieves the switch
to the new PIE vector table.
For the LS0/LS1 RAM memory swap feature to be useful for CLA LFU switchover, two conditions need to be
satisfied:
• CLA code has to fit into a single LSx block. The MVECT table contains CLA task vectors, whose addresses
correspond to locations in the LSx block. For example, if the current firmware CLA code is present in LS0,
MVECTs point to various locations in LS0. If the new firmware CLA code is present in LS1, MVECTs point to
various locations in LS1.
• When switching over from current to new firmware, the MVECTs need to be updated, unless the MVECTs
reside at the same relative location in both LS0 and LS1. If that is the case, then simply swapping LS0/LS1
RAM memory blocks effectively updates the MVECT table, without the need to sequentially update the
MVECTs.

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3.13.4 LFU Switchover

After the new firmware has been programmed to Flash, the user application code needs to determine when
appropriate to switchover to the new firmware. The techniques to determine this difference between real-time
critical firmware running on the CPU and CLA and these techniques are beyond the scope of this document. The
techniques are described in the LFU system reference design guide.
The device supports two register bits that can be set or reset to indicate that LFU switchover is in progress on
the CPU (LFUConfig.LFU_CPU) and CLA (LFUConfig.LFU_CLA1). These bits do not impact any hardware logic
on the device. For example, LFUConfig.LFU_CPU can be set by user application code at the start of switchover,
and then tested in the initialization code in main(). This can enable only LFU switchover specific initialization
to be performed (for example, PIE vector table swap, LS0/LS1 RAM memory swap), while bypassing all other
initialization that typically happens after a device reset.
3.13.5 LFU Resources
The following are additional LFU resources available:
• Live Firmware Update Without Device Reset on C2000™ MCUs User's Guide
• Live Firmware Update With Device Reset on C2000™ MCUs User's Guide
• Live Firmware Update Reference Design with C2000™ Real-Time MCUs

3.14 System Control Register Configuration Restrictions

Memory-mapped registers in the system control operate on INTOSC1 clock domain. Any CPU writes to these
registers requires a delay in between subsequent writes; otherwise, a second write can be lost. The application
needs to take this into consideration and add a delay in terms of the number of NOP instructions after every
write to the registers listed in Table 3-18. The formula to compute the delay between subsequent writes:
Delay (in SYSCLK cycles) = 3 × (FSYSCLK ÷ FINTOSC1) + 9

For Example: for SYSCLK = 100MHz

Delay (in SYSCLK cycles) = 3 × (100MHz ÷ 10MHz) + 9 = 39 SYSCLK cycles

Table 3-18. System Control Registers Impacted

Registers requiring delay after every write
AUXCLKDIVSEL
CLBCLKCTL
PERCLKDIVSEL
SYSCLKDIVSEL
SYSPLLCTL1
SYSPLLMULT
WDCR
XCLKOUTDIVSEL
XTALCR
CLKSRCCTL1
CLKSRCCTL2
CLKSRCCTL3
CPU1TMR2CTL

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3.15 Software
3.15.1 SYSCTL Registers to Driverlib Functions
Table 3-19. SYSCTL Registers to Driverlib Functions
File Driverlib Function
PARTIDL
sysctl.c SysCtl_getDeviceParametric
PARTIDH
sysctl.c SysCtl_getDeviceParametric
REVID
sysctl.h SysCtl_getDeviceRevision
TRIMERRSTS
-
SOFTPRES0
sysctl.h SysCtl_resetPeripheral
SOFTPRES2
- See SOFTPRES0
SOFTPRES3
- See SOFTPRES0
SOFTPRES4
- See SOFTPRES0
SOFTPRES7
- See SOFTPRES0
SOFTPRES8
- See SOFTPRES0
SOFTPRES9
- See SOFTPRES0
SOFTPRES10
- See SOFTPRES0
SOFTPRES11
- See SOFTPRES0
SOFTPRES13
- See SOFTPRES0
SOFTPRES14
- See SOFTPRES0
SOFTPRES15
- See SOFTPRES0
SOFTPRES16
- See SOFTPRES0
SOFTPRES17
-
SOFTPRES18
-
SOFTPRES19
-
SOFTPRES20
-

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
SOFTPRES21
-
SOFTPRES26
-
SOFTPRES27
-
SOFTPRES28
-
SOFTPRES30
-
TAP_STATUS
-
TAP_CONTROL
-
USBTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
ECAPTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
MCUCNF3
sysctl.c SysCtl_emulateDevice
MCUCNF8
sysctl.c SysCtl_emulateDevice
MCUCNF11
sysctl.c SysCtl_emulateDevice
MCUCNF12
sysctl.c SysCtl_emulateDevice
MCUCNF14
sysctl.c SysCtl_emulateDevice
MCUCNF16
sysctl.c SysCtl_emulateDevice
MCUCNF18
sysctl.c SysCtl_emulateDevice
MCUCNF20
sysctl.c SysCtl_emulateDevice
MCUCNF21
sysctl.c SysCtl_emulateDevice
MCUCNF23
sysctl.c SysCtl_emulateDevice
MCUCNF31
sysctl.c SysCtl_emulateDevice
MCUCNF32
sysctl.c SysCtl_emulateDevice
MCUCNF33

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.c SysCtl_emulateDevice
MCUCNF34
sysctl.c SysCtl_emulateDevice
MCUCNF35
sysctl.c SysCtl_emulateDevice
MCUCNFLOCK
-
CLKCFGLOCK1
sysctl.c SysCtl_lockClkConfig
CLKSRCCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.c SysCtl_selectOscSource
sysctl.h SysCtl_enableWatchdogInHalt
sysctl.h SysCtl_disableWatchdogInHalt
CLKSRCCTL2
-
CLKSRCCTL3
sysctl.h SysCtl_selectClockOutSource
SYSPLLCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLMULT
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLSTS
sysctl.c SysCtl_setClock
SYSCLKDIVSEL
sysctl.c SysCtl_getClock
sysctl.h SysCtl_setPLLSysClk
AUXCLKDIVSEL
sysctl.h SysCtl_setMCANClk
PERCLKDIVSEL
sysctl.h SysCtl_setUSBClockDivider
sysctl.h SysCtl_setLINAClockDivider
sysctl.h SysCtl_setTINIEClockDivider
XCLKOUTDIVSEL
sysctl.h SysCtl_setXClk
CLBCLKCTL
sysctl.h SysCtl_setCLBClk
sysctl.h SysCtl_setCLBClkDivider
sysctl.h SysCtl_CLBClkConfig
LOSPCP

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.c SysCtl_getLowSpeedClock
sysctl.h SysCtl_setLowSpeedClock
MCDCR
sysctl.h SysCtl_enableMCD
sysctl.h SysCtl_disableMCD
sysctl.h SysCtl_isMCDClockFailureDetected
sysctl.h SysCtl_resetMCD
sysctl.h SysCtl_connectMCDClockSource
sysctl.h SysCtl_disconnectMCDClockSource
X1CNT
sysctl.c SysCtl_pollX1Counter
sysctl.h SysCtl_getExternalOscCounterValue
sysctl.h SysCtl_clearExternalOscCounterValue
XTALCR
sysctl.c SysCtl_setClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.h SysCtl_setExternalOscMode
sysctl.h SysCtl_turnOnOsc
sysctl.h SysCtl_turnOffOsc
XTALCR2
sysctl.c SysCtl_selectXTAL
CLKFAILCFG
-
CPUSYSLOCK1
sysctl.c SysCtl_lockSysConfig
CPUSYSLOCK2
-
PIEVERRADDR
sysctl.h SysCtl_getPIEVErrAddr
PCLKCR0
sysctl.h SysCtl_enablePeripheral
sysctl.h SysCtl_disablePeripheral
PCLKCR2
- See PCLKCR0
PCLKCR3
- See PCLKCR0
PCLKCR4
- See PCLKCR0
PCLKCR7
- See PCLKCR0
PCLKCR8
- See PCLKCR0
PCLKCR9
- See PCLKCR0

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
PCLKCR10
- See PCLKCR0
PCLKCR11
- See PCLKCR0
PCLKCR12
- See PCLKCR0
PCLKCR13
- See PCLKCR0
PCLKCR14
- See PCLKCR0
PCLKCR15
- See PCLKCR0
PCLKCR16
- See PCLKCR0
PCLKCR17
-
PCLKCR18
-
PCLKCR19
-
PCLKCR20
-
PCLKCR21
-
PCLKCR26
-
PCLKCR27
-
SIMRESET
sysctl.h SysCtl_simulateReset
LPMCR
sysctl.h SysCtl_enterIdleMode
sysctl.h SysCtl_enterStandbyMode
sysctl.h SysCtl_enterHaltMode
sysctl.h SysCtl_setStandbyQualificationPeriod
sysctl.h SysCtl_enableWatchdogStandbyWakeup
sysctl.h SysCtl_disableWatchdogStandbyWakeup
GPIOLPMSEL0
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
GPIOLPMSEL1
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
TMR2CLKCTL
cputimer.h CPUTimer_selectClockSource

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_setCputimer2Clk
RESCCLR
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_clearWatchdogResetStatus
RESC
sysctl.h SysCtl_getResetCause
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_getWatchdogResetStatus
sysctl.h SysCtl_clearWatchdogResetStatus
CMPSSLPMSEL
sysctl.h SysCtl_enableCMPSSLPMWakeupPin
sysctl.h SysCtl_disableCMPSSLPMWakeupPin
MCANRAMACC
-
MCANWAKESTATUS
sysctl.h SysCtl_isMCANWakeStatusSet
sysctl.h SysCtl_clearMCANWakeStatus
MCANWAKESTATUSCLR
sysctl.h SysCtl_clearMCANWakeStatus
CLKSTOPREQ
-
CLKSTOPACK
-
USER_REG1_SYSRSN
sysctl.h SysCtl_setUserRegister
sysctl.h SysCtl_getUserRegister
USER_REG2_SYSRSN
-
USER_REG1_XRSN
-
USER_REG2_XRSN
-
USER_REG1_PORESETN
-
USER_REG2_PORESETN
-
USER_REG3_PORESETN
-
USER_REG4_PORESETN
-
SCSR
sysctl.h SysCtl_setWatchdogMode
sysctl.h SysCtl_isWatchdogInterruptActive
sysctl.h SysCtl_clearWatchdogOverride
WDCNTR

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_getWatchdogCounterValue
WDKEY
sysctl.h SysCtl_serviceWatchdog
sysctl.h SysCtl_enableWatchdogReset
sysctl.h SysCtl_resetWatchdog
WDCR
sysctl.h SysCtl_resetDevice
sysctl.h SysCtl_disableWatchdog
sysctl.h SysCtl_enableWatchdog
sysctl.h SysCtl_isWatchdogEnabled
sysctl.h SysCtl_setWatchdogPredivider
sysctl.h SysCtl_setWatchdogPrescaler
WDWCR
sysctl.h SysCtl_setWatchdogWindowValue
CLA1TASKSRCSELLOCK
-
DMACHSRCSELLOCK
-
CLA1TASKSRCSEL1
cla.c CLA_setTriggerSource
CLA1TASKSRCSEL2
cla.c CLA_setTriggerSource
DMACHSRCSEL1
dma.c DMA_configMode
DMACHSRCSEL2
dma.c DMA_configMode
ADCA_AC
-
ADCB_AC
-
ADCC_AC
-
ADCD_AC
-
ADCE_AC
-
CMPSS1_AC
-
CMPSS2_AC
-
CMPSS3_AC
-
CMPSS4_AC
-
DACA_AC

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
-
PGA1_AC
-
PGA2_AC
-
PGA3_AC
-
EPWM1_AC
-
EPWM2_AC
-
EPWM3_AC
-
EPWM4_AC
-
EPWM5_AC
-
EPWM6_AC
-
EPWM7_AC
-
EPWM8_AC
-
EPWM9_AC
-
EPWM10_AC
-
EPWM11_AC
-
EPWM12_AC
-
EQEP1_AC
-
EQEP2_AC
-
EQEP3_AC
-
ECAP1_AC
-
ECAP2_AC
-
CLB1_AC
-
CLB2_AC
-

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
SCIA_AC
-
SCIB_AC
-
SCIC_AC
-
SPIA_AC
-
SPIB_AC
-
I2CA_AC
-
I2CB_AC
-
PMBUS_A_AC
-
LIN_A_AC
-
MCANA_AC
-
MCANB_AC
-
FSIATX_AC
-
FSIARX_AC
-
USBA_AC
-
HRPWM_A_AC
-
AESA_AC
-
PERIPH_AC_LOCK
sysctl.h SysCtl_lockAccessControlRegs
SYNCSELECT
sysctl.h SysCtl_setSyncOutputConfig
ADCSOCOUTSELECT
sysctl.h SysCtl_enableExtADCSOCSource
sysctl.h SysCtl_disableExtADCSOCSource
SYNCSOCLOCK
sysctl.h SysCtl_lockExtADCSOCSelect
sysctl.h SysCtl_lockSyncSelect
LFUCONFIG
sysctl.h SysCtl_setLFUCPU
sysctl.h SysCtl_getLFUCPU

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_setLFUCLA1
sysctl.h SysCtl_getLFUCLA1
sysctl.h SysCtl_swapPieVectorAndLS01
sysctl.h SysCtl_swapPieVector
sysctl.h SysCtl_swapLS01
LFUSTATUS
sysctl.h SysCtl_isPieVectorSwap
sysctl.h SysCtl_isLS01Swap
LFU_LOCK
sysctl.h SysCtl_lockLFUConfigRegister
sysctl.h SysCtl_lockLFUUserRegister
sysctl.h SysCtl_unlockLFUConfigRegister
sysctl.h SysCtl_unlockLFUUserRegister
LFU_COMMIT
sysctl.h SysCtl_commitLFUConfigRegister
sysctl.h SysCtl_commitLFUUserRegister
SYS_ERR_INT_FLG
sysctl.h SysCtl_getInterruptStatus
SYS_ERR_INT_CLR
sysctl.h SysCtl_clearInterruptStatus
SYS_ERR_INT_SET
sysctl.h SysCtl_setInterruptStatus
SYS_ERR_MASK
sysctl.h SysCtl_getInterruptStatusMask
sysctl.h SysCtl_setInterruptStatusMask

3.15.2 CPUTIMER Registers to Driverlib Functions

Table 3-20. CPUTIMER Registers to Driverlib Functions
File Driverlib Function
TIM
cputimer.h CPUTimer_getTimerCount
PRD
cputimer.h CPUTimer_setPeriod
TCR
cputimer.c CPUTimer_setEmulationMode
cputimer.h CPUTimer_clearOverflowFlag
cputimer.h CPUTimer_disableInterrupt
cputimer.h CPUTimer_enableInterrupt
cputimer.h CPUTimer_reloadTimerCounter
cputimer.h CPUTimer_stopTimer
cputimer.h CPUTimer_resumeTimer
cputimer.h CPUTimer_startTimer
cputimer.h CPUTimer_getTimerOverflowStatus
TPR
cputimer.h CPUTimer_setPreScaler

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Table 3-20. CPUTIMER Registers to Driverlib Functions (continued)

File Driverlib Function
TPRH
cputimer.h CPUTimer_setPreScaler

3.15.3 MEMCFG Registers to Driverlib Functions

Table 3-21. MEMCFG Registers to Driverlib Functions
File Driverlib Function
DXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
DXCOMMIT
memcfg.c MemCfg_commitConfig
DXACCPROT0
memcfg.c MemCfg_setProtection
DXACCPROT1
-
DXTEST
memcfg.c MemCfg_setTestMode
DXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
DXINITDONE
memcfg.c MemCfg_getInitStatus
DXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
LSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
LSXCOMMIT
memcfg.c MemCfg_commitConfig
LSXMSEL
memcfg.c MemCfg_setLSRAMControllerSel
LSXCLAPGM
memcfg.h MemCfg_setCLAMemType
LSXACCPROT0
memcfg.c MemCfg_setProtection
LSXACCPROT1
-
LSXACCPROT2(i)
-
LSXTEST
memcfg.c MemCfg_setTestMode
LSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus

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Table 3-21. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
LSXINITDONE
memcfg.c MemCfg_getInitStatus
LSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
GSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
GSXCOMMIT
memcfg.c MemCfg_commitConfig
GSXACCPROT0
memcfg.c MemCfg_setProtection
GSXTEST
memcfg.c MemCfg_setTestMode
GSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
GSXINITDONE
memcfg.c MemCfg_getInitStatus
GSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
MSGXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
MSGXCOMMIT
memcfg.c MemCfg_commitConfig
MSGXTEST
memcfg.c MemCfg_setTestMode
MSGXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
MSGXINITDONE
memcfg.c MemCfg_getInitStatus
MSGXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_TEST
memcfg.c MemCfg_setTestMode
ROM_FORCE_ERROR
memcfg.c MemCfg_forceMemError
NMAVFLG

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Table 3-21. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.h MemCfg_getViolationInterruptStatus
NMAVSET
memcfg.h MemCfg_forceViolationInterrupt
NMAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
NMAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
NMCPURDAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUWRAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUFAVADDR
-
NMDMAWRAVADDR
-
NMCLA1RDAVADDR
-
NMCLA1WRAVADDR
-
NMCLA1FAVADDR
-
NMDMARDAVADDR
-
MAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
MAVSET
memcfg.h MemCfg_forceViolationInterrupt
MAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
MAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
MCPUFAVADDR
memcfg.c MemCfg_getViolationAddress
MCPUWRAVADDR
-
MDMAWRAVADDR
-
NMTINIERDAVADDR
-
NMTINIEWRAVADDR
-
UCERRFLG
memcfg.h MemCfg_getUncorrErrorStatus

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Table 3-21. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
UCERRSET
memcfg.h MemCfg_forceUncorrErrorStatus
UCERRCLR
memcfg.h MemCfg_clearUncorrErrorStatus
UCCPUREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCDMAREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCCLA1READDR
-
UCTINIEREADDR
-
FLUCERRSTATUS
-
FLCERRSTATUS
-
CERRFLG
memcfg.h MemCfg_getCorrErrorStatus
CERRSET
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_forceCorrErrorStatus
CERRCLR
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_clearCorrErrorStatus
CCPUREADDR
memcfg.c MemCfg_getCorrErrorAddress
CDMAREADDR
-
CCLA1READDR
-
CERRCNT
memcfg.h MemCfg_getCorrErrorCount
CERRTHRES
memcfg.h MemCfg_setCorrErrorThreshold
CEINTFLG
memcfg.h MemCfg_getCorrErrorInterruptStatus
CEINTCLR
memcfg.h MemCfg_clearCorrErrorInterruptStatus
CEINTSET
memcfg.h MemCfg_forceCorrErrorInterrupt
CEINTEN
memcfg.h MemCfg_enableCorrErrorInterrupt
memcfg.h MemCfg_disableCorrErrorInterrupt
CPU_RAM_TEST_ERROR_STS
memcfg.h MemCfg_getDiagErrorStatus

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Table 3-21. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_STS_CLR
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_ADDR
memcfg.h MemCfg_getDiagErrorAddress

3.15.4 PIE Registers to Driverlib Functions

Table 3-22. PIE Registers to Driverlib Functions
File Driverlib Function
CTRL
interrupt.c Interrupt_initModule
interrupt.c Interrupt_defaultHandler
interrupt.h Interrupt_enablePIE
interrupt.h Interrupt_disablePIE
ACK
interrupt.c Interrupt_disable
interrupt.h Interrupt_clearACKGroup
IER1
interrupt.c Interrupt_initModule
interrupt.c Interrupt_enable
interrupt.c Interrupt_disable
IFR1
interrupt.c Interrupt_initModule
IER2
interrupt.c Interrupt_initModule
IFR2
interrupt.c Interrupt_initModule
IER3
interrupt.c Interrupt_initModule
IFR3
interrupt.c Interrupt_initModule
IER4
interrupt.c Interrupt_initModule
IFR4
interrupt.c Interrupt_initModule
IER5
interrupt.c Interrupt_initModule
IFR5
interrupt.c Interrupt_initModule
IER6
interrupt.c Interrupt_initModule
IFR6
interrupt.c Interrupt_initModule
IER7
interrupt.c Interrupt_initModule

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Table 3-22. PIE Registers to Driverlib Functions (continued)

File Driverlib Function
IFR7
interrupt.c Interrupt_initModule
IER8
interrupt.c Interrupt_initModule
IFR8
interrupt.c Interrupt_initModule
IER9
interrupt.c Interrupt_initModule
IFR9
interrupt.c Interrupt_initModule
IER10
interrupt.c Interrupt_initModule
IFR10
interrupt.c Interrupt_initModule
IER11
interrupt.c Interrupt_initModule
IFR11
interrupt.c Interrupt_initModule
IER12
interrupt.c Interrupt_initModule
IFR12
interrupt.c Interrupt_initModule

3.15.5 NMI Registers to Driverlib Functions

Table 3-23. NMI Registers to Driverlib Functions
File Driverlib Function
CFG
sysctl.h SysCtl_enableNMIGlobalInterrupt
FLG
sysctl.h SysCtl_getNMIStatus
sysctl.h SysCtl_getNMIFlagStatus
sysctl.h SysCtl_isNMIFlagSet
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
sysctl.h SysCtl_forceNMIFlags
FLGCLR
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
FLGFRC
sysctl.h SysCtl_forceNMIFlags
WDCNT
sysctl.h SysCtl_getNMIWatchdogCounter
WDPRD
sysctl.h SysCtl_setNMIWatchdogPeriod
sysctl.h SysCtl_getNMIWatchdogPeriod

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Table 3-23. NMI Registers to Driverlib Functions (continued)

File Driverlib Function
SHDFLG
sysctl.h SysCtl_getNMIShadowFlagStatus
sysctl.h SysCtl_isNMIShadowFlagSet
ERRORSTS
sysctl.h SysCtl_isErrorTriggered
sysctl.h SysCtl_getErrorPinStatus
sysctl.h SysCtl_forceError
sysctl.h SysCtl_clearError
ERRORSTSCLR
sysctl.h SysCtl_clearError
ERRORSTSFRC
sysctl.h SysCtl_forceError
ERRORCTL
sysctl.h SysCtl_selectErrPinPolarity
ERRORLOCK
sysctl.h SysCtl_lockErrControl

3.15.6 XINT Registers to Driverlib Functions

Table 3-24. XINT Registers to Driverlib Functions
File Driverlib Function
1CR
gpio.c GPIO_setInterruptPin
gpio.h GPIO_setInterruptType
gpio.h GPIO_getInterruptType
gpio.h GPIO_enableInterrupt
gpio.h GPIO_disableInterrupt
gpio.h GPIO_getInterruptCounter
2CR
- See 1CR
3CR
- See 1CR
4CR
- See 1CR
5CR
- See 1CR
1CTR
gpio.h GPIO_getInterruptCounter
2CTR
-
3CTR
-

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3.15.7 WWD Registers to Driverlib Functions

Table 3-25. WWD Registers to Driverlib Functions
File Driverlib Function
SCSR
sysctl.h SysCtl_setWatchdogMode
sysctl.h SysCtl_isWatchdogInterruptActive
sysctl.h SysCtl_clearWatchdogOverride
WDCNTR
sysctl.h SysCtl_getWatchdogCounterValue
WDKEY
sysctl.h SysCtl_serviceWatchdog
sysctl.h SysCtl_enableWatchdogReset
sysctl.h SysCtl_resetWatchdog
WDCR
sysctl.h SysCtl_resetDevice
sysctl.h SysCtl_disableWatchdog
sysctl.h SysCtl_enableWatchdog
sysctl.h SysCtl_isWatchdogEnabled
sysctl.h SysCtl_setWatchdogPredivider
sysctl.h SysCtl_setWatchdogPrescaler
WDWCR
sysctl.h SysCtl_setWatchdogWindowValue

3.15.8 SYSCTL Examples

NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/sysctl
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.8.1 Missing clock detection (MCD)
FILE: sysctl_ex1_missing_clock_detection.c
This example demonstrates the missing clock detection functionality and the way to handle it. Once the MCD is
simulated by disconnecting the OSCCLK to the MCD module an NMI would be generated. This NMI determines
that an MCD was generated due to a clock failure which is handled in the ISR.
Before an MCD the clock frequency would be as per device initialization (150Mhz). Post MCD the frequency
would move to 10Mhz or INTOSC1.
The example also shows how we can lock the PLL after missing clock, detection, by first explicitly switching the
clock source to INTOSC1, resetting the missing clock detect circuit and then re-locking the PLL. Post a re-lock
the clock frequency would be 150Mhz but using the INTOSC1 as clock source.
External Connections
• None.
Watch Variables
• fail - Indicates that a missing clock was either not detected or was not handled correctly.
• mcd_clkfail_isr - Indicates that the missing clock failure caused an NMI to be triggered and called an the ISR
to handle it.
• mcd_detect - Indicates that a missing clock was detected.
• result - Status of a successful handling of missing clock detection

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3.15.8.2 XCLKOUT (External Clock Output) Configuration

FILE: sysctl_ex2_xclkout_config.c
This example demonstrates how to configure the XCLKOUT pin for observing internal clocks through an external
pin, for debugging and testing purposes.
In this example, we are using INTOSC1 as the XCLKOUT clock source and configuring the divider as 8.
Expected frequency of XCLKOUT = (INTOSC1 freq)/8 = 10/8 = 1.25MHz
View the XCLKOUT on GPIO16 using an oscilloscope.
3.15.9 TIMER Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/timer
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.9.1 CPU Timers
FILE: timer_ex1_cputimers.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt. In order to migrate the project within syscfg to any device, click the swtich button under the device view
and select your
corresponding device to migrate, saving the project will auto-migrate your project settings.
External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.15.9.2 CPU Timers
FILE: timer_ex1_cputimers_sysconfig.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.
This example project has support for migration across our C2000 device families. If you are wanting to build this
project from launchpad or controlCARD, please specify in the .syscfg file the board you're using. At any time you
can select another device to migrate this example. External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.15.10 MEMCFG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/memcfg
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.10.1 Correctable & Uncorrectable Memory Error Handling
FILE: memcfg_ex1_error_handling.c

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This example demonstrates error handling in case of various erroneous memory read/write operations.
Error handling in case of CPU read/write violations, correctable & uncorrectable memory errors has been
demonstrated. Correctable memory errors & violations can generate SYS_INT interrupt to CPU while
uncorrectable errors lead to NMI generation.
External Connections
• None
Watch Variables
• testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to TEST_FAIL
• errCountGlobal - Error counter
3.15.11 INTERRUPT Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/interrupt
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.11.1 External Interrupts (ExternalInterrupt)
FILE: interrupt_ex1_external.c
This program sets up GPIO0 as XINT1 and GPIO1 as XINT2. Two other GPIO signals are used to trigger the
interrupt (GPIO10 triggers XINT1 and GPIO11 triggers XINT2). The user is required to externally connect these
signals for the program to work properly.
XINT1 input is synced to SYSCLKOUT.
XINT2 has a long qualification - 6 samples at 510*SYSCLKOUT each.
GPIO16 will go high outside of the interrupts and low within the interrupts. This signal can be monitored on a
scope.
Each interrupt is fired in sequence - XINT1 first and then XINT2
External Connections
• Connect GPIO10 to GPIO0. GPIO0 will be assigned to XINT1
• Connect GPIO11 to GPIO1. GPIO1 will be assigned to XINT2
Monitor GPIO16 with an oscilloscope. GPIO16 will be high outside of the ISRs and low within each ISR.
Watch Variables
• xint1Count for the number of times through XINT1 interrupt
• xint2Count for the number of times through XINT2 interrupt
• loopCount for the number of times through the idle loop
3.15.11.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
FILE: interrupt_ex2_with_i2c_sci_spi_loopback.c
This program is used to demonstrate how to handle multiple interrupts when using multiple communication
peripherals like I2C, SCI & SPI Digital Loopback all in a single example. The data transfers would be done with
FIFO Interrupts.
It uses the internal loopback test mode of these modules. Both the TX and RX FIFOs and their interrupts are
used. Other than boot mode pin configuration, no other hardware configuration is required.
A stream of data is sent and then compared to the received stream. The sent data looks like this for I2C and
SCI:
0000 0001
0001 0002
0002 0003

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....
00FE 00FF
00FF 0000
etc..
The sent data looks like this for SPI:
0000 0001
0001 0002
0002 0003
....
FFFE FFFF
FFFF 0000
etc..
This pattern is repeated forever.
External Connections
• None
Watch Variables
• sDatai2cA - Data to send through I2C
• rDatai2cA - Received I2C data
• rDataPoint - Used to keep track of the last position in the receive I2C stream for error checking
• sDataspiA - Data to send through SPI
• rDataspiA - Received SPI data
• rDataPointspiA - Used to keep track of the last position in the receive SPI stream for error checking
• sDatasciA - SCI Data being sent
• rDatasciA - SCI Data received
• rDataPointA - Keep track of where we are in the SCI data stream. This is used to check the incoming data
3.15.11.3 CPU Timer Interrupt Software Prioritization
FILE: interrupt_ex3_sw_prioritization.c
This examples demonstrates the software prioritization of interrupts through CPU Timer Interrupts. Software
prioritization of interrupts is achieved by enabling interrupt nesting.
In this device, hardware priorities for CPU Timer 0, 1 and 2 are set as timer 0 being highest priority and timer 2
being lowest priority. This example configures CPU Timer0, 1, and 2 priority in software with timer 2 priority being
highest and timer 0 being lowest in software and prints a trace for the order of execution.
For most applications, the hardware prioritizing of the interrupts is sufficient. For applications that need custom
prioritizing, this example illustrates how this can be done through software.User specific priorities can be
configured in sw_prioritized_isr_level.h header file.
To enable interrupt nesting, following sequence needs to followed in ISRs. Step 1: Set the global priority: Modify
the IER register to allow CPU interrupts with a higher user priority to be serviced. Note: at this time IER has
already been saved on the stack. Step 2: Set the group priority: (optional) Modify the appropriate PIEIERx
register to allow group interrupts with a higher user set priority to be serviced. Do NOT clear PIEIER register bits
from another group other than that being serviced by this ISR. Doing so can cause erroneous interrupts to occur.
Step 3: Enable interrupts: There are three steps to do this: a. Clear the PIEACK bits b. Wait at least one cycle c.
Clear the INTM bit. Step 4: Run the main part of the ISR Step 5: Set INTM to disable interrupts. Step 6: Restore
PIEIERx (optional depending on step 2) Step 7: Return from ISR
Refer to below link on more details on Interrupt nesting in C28x devices:
<C2000Ware>\docs\c28x_interrupt_nesting\html\index.html
External Connections
• None
Watch Variables

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• traceISR - shows the order in which ISRs are executed.

3.15.11.4 EPWM Real-Time Interrupt
FILE: interrupt_ex4_epwm_realtime_interrupt.c
This example configures the ePWM1 Timer and increments a counter each time the ISR is executed. ePWM
interrupt can be configured as time critical to demonstrate real-time mode functionality and real-time interrupt
capability.
The example uses 2 LEDs - LED1 is toggled in the main loop and LED2 is toggled in the EPWM Timer
Interrupt. FREE_SOFT bits and DBGIER.INT3 bit must be set to enable ePWM1 interrupt to be time critical and
operational in real time mode after halt command
How to run the example?
• Add the watch variables as mentioned below and enable Continuous Refresh.
• Enable real-time mode (Run->Advanced->Enable Silicon Real-time Mode)
• Initially, the DBGIER register is set to 0 and the EPWM emulation mode is set to
EPWM_EMULATION_STOP_AFTER_NEXT_TB (FREE_SOFT = 0)
• When the application is running, you will find both LEDs toggling and the watch variables
EPwm1TimerIntCount, EPwm1Regs.TBCTR getting updated.
• When the application is halted, both LEDs stop toggling and the watch variables remain constant. EPWM
counter is stopped on debugger halt.
• To enable EPWM counter run during debugger halt, set emulation mode as
EPWM_EMULATION_FREE_RUN (FREE_SOFT = 2). You will find EPwm1Regs.TBCTR is running, but
EPwm1TimerIntCount remains constant. This means, the EPWM counter is running, but the ISRs are not
getting serviced.
• To enable real-time interrupts, set DBGIER.INT3 = 1 (EPWM1 interrupt is part of PIE Group 3). You will
find that the EPwm1TimerIntCount is incrementing and the LED starts toggling. The EPWM ISR is getting
serviced even during a debugger halt.
For more details, watch this video : C2000 Real-Time Features
External Connections
• None
Watch Variables
• EPwm1TimerIntCount - EPWM1 ISR counter
• EPwm1Regs.TBCTR.TBCTR - EPWM1 Time Base counter
• EPwm1Regs.TBCTL.FREE_SOFT - Set this to 2 to enable free run
• DBGIER.INT3 - Set to 1 to enable real time interrupt
3.15.12 LPM Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/lpm
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.12.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
FILE: lpm_ex1_idlewake_gpio.c
This example puts the device into IDLE mode and then wakes up the device from IDLE using XINT1 which
triggers on a falling edge of GPIO0.
The GPIO0 pin must be pulled from high to low by an external agent for wakeup. GPIO0 is configured as an
XINT1 pin to trigger an XINT1 interrupt upon detection of a falling edge.

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Initially, pull GPIO0 high externally. To wake device from IDLE mode by triggering an XINT1 interrupt, pull GPIO0
low (falling edge). The wakeup process begins as soon as GPIO0 is held low for the time indicated in the device
datasheet.
GPIO1 is pulled high before entering the IDLE mode and is pulled low when in the external interrupt ISR.
External Connections
• GPIO0 needs to be pulled low to wake up the device.
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
FILE: lpm_ex2_idlewake_watchdog.c
This example puts the device into IDLE mode and then wakes up the device from IDLE using watchdog timer.
The device wakes up from the IDLE mode when the watchdog timer overflows, triggering an interrupt. A pre
scalar is set for the watchdog timer to change the counter overflow time.
GPIO1 is pulled high before entering the IDLE mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
FILE: lpm_ex3_standbywake_gpio.c
This example puts the device into STANDBY mode. If the lowest possible current consumption in STANDBY
mode is desired, the JTAG connector must be removed from the device board while the device is in STANDBY
mode.
This example puts the device into STANDBY mode and then wakes up the device from STANDBY using an LPM
wakeup pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse. Initially, pull GPIO0 high externally. To wake device from STANDBY mode, pull GPIO0 low for at least
(2+QUALSTDBY), OSCLKS, then pull it high again.
The example then wakes up the device from STANDBY using GPIO0. GPIO0 wakes the device from STANDBY
mode when a low pulse (signal goes high->low->high)is detected on the pin. This pin must be pulsed by an
external agent for wakeup.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• GPIO0 needs to be pulled low to wake up the device.
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
FILE: lpm_ex4_standbywake_watchdog.c
This example puts the device into STANDBY mode. If the lowest possible current consumption in STANDBY
mode is desired, the JTAG connector must be removed from the device board while the device is in STANDBY
mode.
This example puts the device into STANDBY mode then wakes up the device from STANDBY using watchdog
timer.
The device wakes up from the STANDBY mode when the watchdog timer overflows triggering an interrupt. In the
ISR, the GPIO1 is pulled low. the GPIO1 is toggled to indicate the device is out of STANDBY mode. A pre scalar
is set for the watchdog timer to change the counter overflow time.

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GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.5 Low Power Modes: Halt Mode and Wakeup using GPIO
FILE: lpm_ex5_haltwake_gpio.c
This example puts the device into HALT mode. If the lowest possible current consumption in HALT mode is
desired, the JTAG connector must be removed from the device board while the device is in HALT mode.
For applications that require minimal power consumption during HALT mode, application software should power
off the XTAL prior to entering HALT by setting the XTALCR.OSCOFF bit or by using the driverlib function
SysCtl_turnOffOsc(SYSCTL_OSCSRC_XTAL);. If the OSCCLK source is configured to be XTAL, the application
should first switch the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.
This example puts the device into HALT mode and then wakes up the device from HALT using an LPM wakeup
pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse.The GPIO0 pin must be pulled from high to low by an external agent for wakeup.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.6 Low Power Modes: Halt Mode and Wakeup
FILE: lpm_ex6_haltwake_gpio_watchdog.c
This example puts the device into HALT mode. If the lowest possible current consumption in HALT mode is
desired, the JTAG connector must be removed from the device board while the device is in HALT mode.
For applications that require minimal power consumption during HALT mode, application software should power
off the XTAL prior to entering HALT by setting the XTALCR.OSCOFF bit or by using the driverlib function
SysCtl_turnOffOsc(SYSCTL_OSCSRC_XTAL);. If the OSCCLK source is configured to be XTAL, the application
should first switch the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.
This example puts the device into HALT mode and then wakes up the device from HALT using an LPM wakeup
pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse.The GPIO0 pin must be pulled from high to low by an external agent for wakeup.
In this example, the watchdog timer is clocked, and is configured to produce watchdog reset as a timeout
mechanism.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.13 WATCHDOG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/watchdog
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.13.1 Watchdog
FILE: watchdog_ex1_service.c

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This example shows how to service the watchdog or generate a wakeup interrupt using the watchdog. By default
the example will generate a Wake interrupt. To service the watchdog and not generate the interrupt, uncomment
the SysCtl_serviceWatchdog() line in the main for loop.
External Connections
• None.
Watch Variables
• wakeCount - The number of times entered into the watchdog ISR
• loopCount - The number of loops performed while not in ISR
3.16 SYSCTRL Registers
This Section describes the SYSCTRL Registers.
3.16.1 SYSCTRL Base Address Table
Table 3-26. SYSCTRL Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1
Instance Structure Protected

CPUTIMER_REG
CpuTimer0Regs CPUTIMER0_BASE 0x0000_0C00 YES - - -
S
CPUTIMER_REG
CpuTimer1Regs CPUTIMER1_BASE 0x0000_0C08 YES - - -
S
CPUTIMER_REG
CpuTimer2Regs CPUTIMER2_BASE 0x0000_0C10 YES - - -
S
PieCtrlRegs PIE_CTRL_REGS PIECTRL_BASE 0x0000_0CE0 YES - - -
PieVectTable PIE_VECT_TABLE PIEVECTTABLE_BASE 0x0000_0D00 YES - - -
WdRegs WD_REGS WD_BASE 0x0000_7000 YES - - YES
NMI_INTRUPT_R
NmiIntruptRegs NMI_BASE 0x0000_7060 YES - - YES
EGS
XintRegs XINT_REGS XINT_BASE 0x0000_7070 YES - - YES
SYNC_SOC_REG
SyncSocRegs SYNCSOC_BASE 0x0000_7940 YES - - YES
S
DmaClaSrcSelReg DMA_CLA_SRC_
DMACLASRCSEL_BASE 0x0000_7980 YES - - YES
s SEL_REGS
LfuRegs LFU_REGS LFU_BASE 0x0000_7FE0 YES - YES YES
DevCfgRegs DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - - YES
ClkCfgRegs CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES - - YES
CpuSysRegs CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES - - YES
SYS_STATUS_RE
SysStatusRegs SYSSTAT_BASE 0x0005_D400 YES - - YES
GS
PERIPH_AC_REG
PeriphAcRegs PERIPHAC_BASE 0x0005_D500 YES - - YES
S
MemCfgRegs MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES - - YES
AccessProtectionR ACCESS_PROTE ACCESSPROTECTION_BA
0x0005_F500 YES - - YES
egs CTION_REGS SE
MEMORY_ERRO
MemoryErrorRegs MEMORYERROR_BASE 0x0005_F540 YES - - YES
R_REGS
TEST_ERROR_R
TestErrorRegs TESTERROR_BASE 0x0005_F590 YES - - YES
EGS
UidRegs UID_REGS UID_BASE 0x0007_2168 YES - - -

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3.16.2 CPUTIMER_REGS Registers

Table 3-27 lists the memory-mapped registers for the CPUTIMER_REGS registers. All register offset addresses
not listed in Table 3-27 should be considered as reserved locations and the register contents should not be
modified.
Table 3-27. CPUTIMER_REGS Registers
Offset Acronym Register Name Write Protection Section
0h TIM CPU-Timer, Counter Register Go
2h PRD CPU-Timer, Period Register Go
4h TCR CPU-Timer, Control Register Go
6h TPR CPU-Timer, Prescale Register Go
7h TPRH CPU-Timer, Prescale Register High Go

Complex bit access types are encoded to fit into small table cells. Table 3-28 shows the codes that are used for
access types in this section.
Table 3-28. CPUTIMER_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W Write
1C 1 to clear
Reset or Default Value
-n Value after reset or the default
value

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3.16.2.1 TIM Register (Offset = 0h) [Reset = 0000FFFFh]

TIM is shown in Figure 3-21 and described in Table 3-29.
Return to the Summary Table.
CPU-Timer, Counter Register
Figure 3-21. TIM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-29. TIM Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Counter Registers
The TIMH register holds the high 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Counter Registers
The TIM register holds the low 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

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3.16.2.2 PRD Register (Offset = 2h) [Reset = 0000FFFFh]

PRD is shown in Figure 3-22 and described in Table 3-30.
Return to the Summary Table.
CPU-Timer, Period Register
Figure 3-22. PRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-30. PRD Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Period Registers
The PRDH register holds the high 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Period Registers
The PRD register holds the low 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

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3.16.2.3 TCR Register (Offset = 4h) [Reset = 0001h]

TCR is shown in Figure 3-23 and described in Table 3-31.
Return to the Summary Table.
CPU-Timer, Control Register
Figure 3-23. TCR Register
15 14 13 12 11 10 9 8
TIF TIE RESERVED FREE SOFT RESERVED
R/W1C-0h R/W-0h R-0h R/W-0h R/W-0h R-0h

7 6 5 4 3 2 1 0
RESERVED TRB TSS RESERVED
R-0h R/W-0h R/W-0h R-1h

Table 3-31. TCR Register Field Descriptions

Bit Field Type Reset Description
15 TIF R/W1C 0h CPU-Timer Overflow Flag.
TIF indicates whether a timer overflow has happened since TIF was
last cleared. TIF is not cleared automatically and does not need to be
cleared to enable the next timer interrupt.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1h (R/W) = This flag gets set when the CPU-timer decrements to
zero.
Writing a 1 to this bit clears the flag.
14 TIE R/W 0h CPU-Timer Interrupt Enable.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer interrupt is disabled.
1h (R/W) = The CPU-Timer interrupt is enabled. If the timer
decrements to zero, and TIE is set, the timer asserts its interrupt
request.
13-12 RESERVED R 0h Reserved
11 FREE R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run. If FREE is 0, then the SOFT bit controls the
emulation behavior.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop)
(SOFT bit controls the emulation behavior)
1h (R/W) = Free Run
(SOFT bit is don't care, counter is free running)
10 SOFT R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run (that is, free runs). In this case, SOFT is a
don't care. But if FREE is 0, then SOFT takes effect.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
1h (R/W) = Stop after the TIMH:TIM decrements to 0 (soft stop)
In the SOFT STOP mode, the timer generates an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
9-6 RESERVED R 0h Reserved

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Table 3-31. TCR Register Field Descriptions (continued)

Bit Field Type Reset Description
5 TRB R/W 0h Timer reload
Reset type: SYSRSn
0h (R/W) = The TRB bit is always read as zero. Writes of 0 are
ignored.
1h (R/W) = When you write a 1 to TRB, the TIMH:TIM is loaded with
the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in
the timer dividedown
register (TDDRH:TDDR).
4 TSS R/W 0h CPU-Timer stop status bit.
TSS is a 1-bit flag that stops or starts the CPU-timer.
Reset type: SYSRSn
0h (R/W) = Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is
cleared to 0 and the
CPU-timer immediately starts.
1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.
3-0 RESERVED R 1h Reserved

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3.16.2.4 TPR Register (Offset = 6h) [Reset = 0000h]

TPR is shown in Figure 3-24 and described in Table 3-32.
Return to the Summary Table.
CPU-Timer, Prescale Register
Figure 3-24. TPR Register
15 14 13 12 11 10 9 8
PSC
R-0h

7 6 5 4 3 2 1 0
TDDR
R/W-0h

Table 3-32. TPR Register Field Descriptions

Bit Field Type Reset Description
15-8 PSC R 0h CPU-Timer Prescale Counter.
These bits hold the current prescale count for the timer. For every
timer clock source cycle that the PSCH:PSC value is greater than
0, the PSCH:PSC decrements by one. One timer clock (output
of the timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and
the timer counter register (TIMH:TIM) decrements by one. The
PSCH:PSC is also reloaded whenever the timer reload bit (TRB)
is set by software. The PSCH:PSC can be checked by reading the
register, but it cannot be set directly. It must get its value from the
timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
Reset type: SYSRSn
7-0 TDDR R/W 0h CPU-Timer Divide-Down.
Every (TDDRH:TDDR + 1) timer clock source cycles, the timer
counter register (TIMH:TIM) decrements by one. At reset, the
TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC)
value is 0, one timer clock source cycle later, the contents
of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC
whenever the timer reload bit (TRB) is set by software.
Reset type: SYSRSn

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3.16.2.5 TPRH Register (Offset = 7h) [Reset = 0000h]

TPRH is shown in Figure 3-25 and described in Table 3-33.
Return to the Summary Table.
CPU-Timer, Prescale Register High
Figure 3-25. TPRH Register
15 14 13 12 11 10 9 8
PSCH
R-0h

7 6 5 4 3 2 1 0
TDDRH
R/W-0h

Table 3-33. TPRH Register Field Descriptions

Bit Field Type Reset Description
15-8 PSCH R 0h See description of TIMERxTPR.
Reset type: SYSRSn
7-0 TDDRH R/W 0h See description of TIMERxTPR.
Reset type: SYSRSn

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3.16.3 PIE_CTRL_REGS Registers

Table 3-34 lists the memory-mapped registers for the PIE_CTRL_REGS registers. All register offset addresses
not listed in Table 3-34 should be considered as reserved locations and the register contents should not be
modified.
Table 3-34. PIE_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h PIECTRL ePIE Control Register Go
1h PIEACK Interrupt Acknowledge Register Go
2h PIEIER1 Interrupt Group 1 Enable Register Go
3h PIEIFR1 Interrupt Group 1 Flag Register Go
4h PIEIER2 Interrupt Group 2 Enable Register Go
5h PIEIFR2 Interrupt Group 2 Flag Register Go
6h PIEIER3 Interrupt Group 3 Enable Register Go
7h PIEIFR3 Interrupt Group 3 Flag Register Go
8h PIEIER4 Interrupt Group 4 Enable Register Go
9h PIEIFR4 Interrupt Group 4 Flag Register Go
Ah PIEIER5 Interrupt Group 5 Enable Register Go
Bh PIEIFR5 Interrupt Group 5 Flag Register Go
Ch PIEIER6 Interrupt Group 6 Enable Register Go
Dh PIEIFR6 Interrupt Group 6 Flag Register Go
Eh PIEIER7 Interrupt Group 7 Enable Register Go
Fh PIEIFR7 Interrupt Group 7 Flag Register Go
10h PIEIER8 Interrupt Group 8 Enable Register Go
11h PIEIFR8 Interrupt Group 8 Flag Register Go
12h PIEIER9 Interrupt Group 9 Enable Register Go
13h PIEIFR9 Interrupt Group 9 Flag Register Go
14h PIEIER10 Interrupt Group 10 Enable Register Go
15h PIEIFR10 Interrupt Group 10 Flag Register Go
16h PIEIER11 Interrupt Group 11 Enable Register Go
17h PIEIFR11 Interrupt Group 11 Flag Register Go
18h PIEIER12 Interrupt Group 12 Enable Register Go
19h PIEIFR12 Interrupt Group 12 Flag Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-35 shows the codes that are used for
access types in this section.
Table 3-35. PIE_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value

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Table 3-35. PIE_CTRL_REGS Access Type Codes

(continued)
Access Type Code Description
-n Value after reset or the default
value

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3.16.3.1 PIECTRL Register (Offset = 0h) [Reset = 0000h]

PIECTRL is shown in Figure 3-26 and described in Table 3-36.
Return to the Summary Table.
ePIE Control Register
Figure 3-26. PIECTRL Register
15 14 13 12 11 10 9 8
PIEVECT
R-0h

7 6 5 4 3 2 1 0
PIEVECT ENPIE
R-0h R/W-0h

Table 3-36. PIECTRL Register Field Descriptions

Bit Field Type Reset Description
15-1 PIEVECT R 0h These bits indicate the vector address of the vector fetched from the
ePIE vector table. The least significant bit of the address is ignored
and only bits 1 to 15 of the address are shown. The vector value
can be read by the user to determine which interrupt generated the
vector fetch.
Note: When a NMI is serviced, the PIEVECT bit-field does not reflect
the vector as it does for other interrupts.
Reset type: SYSRSn
0 ENPIE R/W 0h Enable vector fetching from ePIE block. This bit must be set to 1
for peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR,
PIEIER) can be accessed even when the ePIE block is disabled.
Reset type: SYSRSn

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3.16.3.2 PIEACK Register (Offset = 1h) [Reset = 0000h]

PIEACK is shown in Figure 3-27 and described in Table 3-37.
Return to the Summary Table.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is set. This
prevents other interrupts in that group from propagating to the CPU while the first interrupt is handled. Writing a
1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to propagate. ISRs for PIE
interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.
Figure 3-27. PIEACK Register
15 14 13 12 11 10 9 8
RESERVED ACK12 ACK11 ACK10 ACK9
R-0-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

7 6 5 4 3 2 1 0
ACK8 ACK7 ACK6 ACK5 ACK4 ACK3 ACK2 ACK1
R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

Table 3-37. PIEACK Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 ACK12 R/W1S 0h Acknowledge PIE Interrupt Group 12
Reset type: SYSRSn
10 ACK11 R/W1S 0h Acknowledge PIE Interrupt Group 11
Reset type: SYSRSn
9 ACK10 R/W1S 0h Acknowledge PIE Interrupt Group 10
Reset type: SYSRSn
8 ACK9 R/W1S 0h Acknowledge PIE Interrupt Group 9
Reset type: SYSRSn
7 ACK8 R/W1S 0h Acknowledge PIE Interrupt Group 8
Reset type: SYSRSn
6 ACK7 R/W1S 0h Acknowledge PIE Interrupt Group 7
Reset type: SYSRSn
5 ACK6 R/W1S 0h Acknowledge PIE Interrupt Group 6
Reset type: SYSRSn
4 ACK5 R/W1S 0h Acknowledge PIE Interrupt Group 5
Reset type: SYSRSn
3 ACK4 R/W1S 0h Acknowledge PIE Interrupt Group 4
Reset type: SYSRSn
2 ACK3 R/W1S 0h Acknowledge PIE Interrupt Group 3
Reset type: SYSRSn
1 ACK2 R/W1S 0h Acknowledge PIE Interrupt Group 2
Reset type: SYSRSn
0 ACK1 R/W1S 0h Acknowledge PIE Interrupt Group 1
Reset type: SYSRSn

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3.16.3.3 PIEIER1 Register (Offset = 2h) [Reset = 0000h]

PIEIER1 is shown in Figure 3-28 and described in Table 3-38.
Return to the Summary Table.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-28. PIEIER1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-38. PIEIER1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 1.2
Reset type: SYSRSn

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Table 3-38. PIEIER1 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 1.1
Reset type: SYSRSn

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3.16.3.4 PIEIFR1 Register (Offset = 3h) [Reset = 0000h]

PIEIFR1 is shown in Figure 3-29 and described in Table 3-39.
Return to the Summary Table.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-29. PIEIFR1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-39. PIEIFR1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 1.4
Reset type: SYSRSn

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Table 3-39. PIEIFR1 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 1.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 1.1
Reset type: SYSRSn

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3.16.3.5 PIEIER2 Register (Offset = 4h) [Reset = 0000h]

PIEIER2 is shown in Figure 3-30 and described in Table 3-40.
Return to the Summary Table.
Interrupt Group 2 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-30. PIEIER2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-40. PIEIER2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 2.2
Reset type: SYSRSn

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Table 3-40. PIEIER2 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 2.1
Reset type: SYSRSn

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3.16.3.6 PIEIFR2 Register (Offset = 5h) [Reset = 0000h]

PIEIFR2 is shown in Figure 3-31 and described in Table 3-41.
Return to the Summary Table.
Interrupt Group 2 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-31. PIEIFR2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-41. PIEIFR2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 2.4
Reset type: SYSRSn

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Table 3-41. PIEIFR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 2.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 2.1
Reset type: SYSRSn

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3.16.3.7 PIEIER3 Register (Offset = 6h) [Reset = 0000h]

PIEIER3 is shown in Figure 3-32 and described in Table 3-42.
Return to the Summary Table.
Interrupt Group 3 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-32. PIEIER3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-42. PIEIER3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 3.2
Reset type: SYSRSn

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Table 3-42. PIEIER3 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 3.1
Reset type: SYSRSn

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3.16.3.8 PIEIFR3 Register (Offset = 7h) [Reset = 0000h]

PIEIFR3 is shown in Figure 3-33 and described in Table 3-43.
Return to the Summary Table.
Interrupt Group 3 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-33. PIEIFR3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-43. PIEIFR3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 3.4
Reset type: SYSRSn

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Table 3-43. PIEIFR3 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 3.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 3.1
Reset type: SYSRSn

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3.16.3.9 PIEIER4 Register (Offset = 8h) [Reset = 0000h]

PIEIER4 is shown in Figure 3-34 and described in Table 3-44.
Return to the Summary Table.
Interrupt Group 4 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-34. PIEIER4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-44. PIEIER4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 4.2
Reset type: SYSRSn

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Table 3-44. PIEIER4 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 4.1
Reset type: SYSRSn

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3.16.3.10 PIEIFR4 Register (Offset = 9h) [Reset = 0000h]

PIEIFR4 is shown in Figure 3-35 and described in Table 3-45.
Return to the Summary Table.
Interrupt Group 4 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-35. PIEIFR4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-45. PIEIFR4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 4.4
Reset type: SYSRSn

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Table 3-45. PIEIFR4 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 4.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 4.1
Reset type: SYSRSn

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3.16.3.11 PIEIER5 Register (Offset = Ah) [Reset = 0000h]

PIEIER5 is shown in Figure 3-36 and described in Table 3-46.
Return to the Summary Table.
Interrupt Group 5 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-36. PIEIER5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-46. PIEIER5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 5.2
Reset type: SYSRSn

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Table 3-46. PIEIER5 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 5.1
Reset type: SYSRSn

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3.16.3.12 PIEIFR5 Register (Offset = Bh) [Reset = 0000h]

PIEIFR5 is shown in Figure 3-37 and described in Table 3-47.
Return to the Summary Table.
Interrupt Group 5 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-37. PIEIFR5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-47. PIEIFR5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 5.4
Reset type: SYSRSn

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Table 3-47. PIEIFR5 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 5.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 5.1
Reset type: SYSRSn

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3.16.3.13 PIEIER6 Register (Offset = Ch) [Reset = 0000h]

PIEIER6 is shown in Figure 3-38 and described in Table 3-48.
Return to the Summary Table.
Interrupt Group 6 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-38. PIEIER6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-48. PIEIER6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 6.2
Reset type: SYSRSn

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Table 3-48. PIEIER6 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 6.1
Reset type: SYSRSn

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3.16.3.14 PIEIFR6 Register (Offset = Dh) [Reset = 0000h]

PIEIFR6 is shown in Figure 3-39 and described in Table 3-49.
Return to the Summary Table.
Interrupt Group 6 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-39. PIEIFR6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-49. PIEIFR6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 6.4
Reset type: SYSRSn

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Table 3-49. PIEIFR6 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 6.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 6.1
Reset type: SYSRSn

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3.16.3.15 PIEIER7 Register (Offset = Eh) [Reset = 0000h]

PIEIER7 is shown in Figure 3-40 and described in Table 3-50.
Return to the Summary Table.
Interrupt Group 7 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-40. PIEIER7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-50. PIEIER7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 7.2
Reset type: SYSRSn

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Table 3-50. PIEIER7 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 7.1
Reset type: SYSRSn

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3.16.3.16 PIEIFR7 Register (Offset = Fh) [Reset = 0000h]

PIEIFR7 is shown in Figure 3-41 and described in Table 3-51.
Return to the Summary Table.
Interrupt Group 7 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-41. PIEIFR7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-51. PIEIFR7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 7.4
Reset type: SYSRSn

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Table 3-51. PIEIFR7 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 7.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 7.1
Reset type: SYSRSn

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3.16.3.17 PIEIER8 Register (Offset = 10h) [Reset = 0000h]

PIEIER8 is shown in Figure 3-42 and described in Table 3-52.
Return to the Summary Table.
Interrupt Group 8 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-42. PIEIER8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-52. PIEIER8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 8.2
Reset type: SYSRSn

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Table 3-52. PIEIER8 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 8.1
Reset type: SYSRSn

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3.16.3.18 PIEIFR8 Register (Offset = 11h) [Reset = 0000h]

PIEIFR8 is shown in Figure 3-43 and described in Table 3-53.
Return to the Summary Table.
Interrupt Group 8 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-43. PIEIFR8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-53. PIEIFR8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 8.4
Reset type: SYSRSn

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Table 3-53. PIEIFR8 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 8.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 8.1
Reset type: SYSRSn

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3.16.3.19 PIEIER9 Register (Offset = 12h) [Reset = 0000h]

PIEIER9 is shown in Figure 3-44 and described in Table 3-54.
Return to the Summary Table.
Interrupt Group 9 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-44. PIEIER9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-54. PIEIER9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 9.2
Reset type: SYSRSn

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Table 3-54. PIEIER9 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 9.1
Reset type: SYSRSn

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3.16.3.20 PIEIFR9 Register (Offset = 13h) [Reset = 0000h]

PIEIFR9 is shown in Figure 3-45 and described in Table 3-55.
Return to the Summary Table.
Interrupt Group 9 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-45. PIEIFR9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-55. PIEIFR9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 9.4
Reset type: SYSRSn

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Table 3-55. PIEIFR9 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 9.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 9.1
Reset type: SYSRSn

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3.16.3.21 PIEIER10 Register (Offset = 14h) [Reset = 0000h]

PIEIER10 is shown in Figure 3-46 and described in Table 3-56.
Return to the Summary Table.
Interrupt Group 10 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-46. PIEIER10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-56. PIEIER10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 10.2
Reset type: SYSRSn

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Table 3-56. PIEIER10 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 10.1
Reset type: SYSRSn

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3.16.3.22 PIEIFR10 Register (Offset = 15h) [Reset = 0000h]

PIEIFR10 is shown in Figure 3-47 and described in Table 3-57.
Return to the Summary Table.
Interrupt Group 10 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-47. PIEIFR10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-57. PIEIFR10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 10.4
Reset type: SYSRSn

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Table 3-57. PIEIFR10 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 10.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 10.1
Reset type: SYSRSn

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3.16.3.23 PIEIER11 Register (Offset = 16h) [Reset = 0000h]

PIEIER11 is shown in Figure 3-48 and described in Table 3-58.
Return to the Summary Table.
Interrupt Group 11 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-48. PIEIER11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-58. PIEIER11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 11.2
Reset type: SYSRSn

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Table 3-58. PIEIER11 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 11.1
Reset type: SYSRSn

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3.16.3.24 PIEIFR11 Register (Offset = 17h) [Reset = 0000h]

PIEIFR11 is shown in Figure 3-49 and described in Table 3-59.
Return to the Summary Table.
Interrupt Group 11 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-49. PIEIFR11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-59. PIEIFR11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 11.4
Reset type: SYSRSn

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Table 3-59. PIEIFR11 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 11.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 11.1
Reset type: SYSRSn

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3.16.3.25 PIEIER12 Register (Offset = 18h) [Reset = 0000h]

PIEIER12 is shown in Figure 3-50 and described in Table 3-60.
Return to the Summary Table.
Interrupt Group 12 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-50. PIEIER12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-60. PIEIER12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 12.2
Reset type: SYSRSn

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Table 3-60. PIEIER12 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 12.1
Reset type: SYSRSn

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3.16.3.26 PIEIFR12 Register (Offset = 19h) [Reset = 0000h]

PIEIFR12 is shown in Figure 3-51 and described in Table 3-61.
Return to the Summary Table.
Interrupt Group 12 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-51. PIEIFR12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-61. PIEIFR12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 12.4
Reset type: SYSRSn

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Table 3-61. PIEIFR12 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 12.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 12.1
Reset type: SYSRSn

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3.16.4 NMI_INTRUPT_REGS Registers

Table 3-62 lists the memory-mapped registers for the NMI_INTRUPT_REGS registers. All register offset
addresses not listed in Table 3-62 should be considered as reserved locations and the register contents should
not be modified.
Table 3-62. NMI_INTRUPT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMICFG NMI Configuration Register EALLOW Go
1h NMIFLG NMI Flag Register (SYSRsn Clear) Go
2h NMIFLGCLR NMI Flag Clear Register EALLOW Go
3h NMIFLGFRC NMI Flag Force Register EALLOW Go
4h NMIWDCNT NMI Watchdog Counter Register Go
5h NMIWDPRD NMI Watchdog Period Register EALLOW Go
6h NMISHDFLG NMI Shadow Flag Register Go
7h ERRORSTS Error pin status Go
8h ERRORSTSCLR ERRORSTS clear register EALLOW Go
9h ERRORSTSFRC ERRORSTS force register EALLOW Go
Ah ERRORCTL Error pin control register EALLOW Go
Bh ERRORLOCK Lock register to Error pin registers. EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-63 shows the codes that are used for
access types in this section.
Table 3-63. NMI_INTRUPT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.4.1 NMICFG Register (Offset = 0h) [Reset = 0000h]

NMICFG is shown in Figure 3-52 and described in Table 3-64.
Return to the Summary Table.
NMI Configuration Register
Figure 3-52. NMICFG Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED NMIE
R-0-0h R/W1S-0h

Table 3-64. NMICFG Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 NMIE R/W1S 0h When set to 1 any condition will generate an NMI interrupt to the
C28 CPU and kick off the NMI watchdog counter. As part of boot
sequence this bit should be set after the device security related
initialization is complete.
0 NMI disabled
1 NMI enabled
Reset type: SYSRSn

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3.16.4.2 NMIFLG Register (Offset = 1h) [Reset = 0000h]

NMIFLG is shown in Figure 3-53 and described in Table 3-65.
Return to the Summary Table.
NMI Flag Register (SYSRsn Clear)
Figure 3-53. NMIFLG Register
15 14 13 12 11 10 9 8
RESERVED RESERVED SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED RESERVED RESERVED UNCERR CLOCKFAIL NMIINT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-65. NMIFLG Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R-0 0h Reserved
14 RESERVED R 0h Reserved
13 SWERR R 0h SW Error Force NMI Flag: This bit indicates if an NMI was forced
through the NMIFLGFRC register. This bit can only be cleared by the
user writing to the respective bit in the NMIFLGCLR register or by an
SYSRSn reset:
0 No SW Error force Generated
1 SW Error NMI is forced by SW.
No further NMI pulses are generated until this flag is cleared by the
user.
Reset type: SYSRSn
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 CLBNMI R 0h Reconfigurable Logic NMI Flag: This bit indicates if an NMI was
generated by the Reconfigurable Logic. This bit can only be cleared
by the user writing to the corresponding clear bit in the NMIFLGCLR
register or by SYSRSn reset:
0,No Reconfigurable Logic NMI pending
1,Reconfigurable Logic NMI generated
Reset type: SYSRSn
7 SYSDBGNMI R 0h System Debug Module NMI Flag: This bit indicates if an NMI was
generated by the System Debug Module. This bit can only be
cleared by the user writing to the corresponding clear bit in the
NMIFLGCLR register or by SYSRSn reset:
0,No System Debug NMI pending
1,System Debug NMI generated
Reset type: SYSRSn
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved

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Table 3-65. NMIFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
2 UNCERR R 0h Flash/RAM/ROM Uncorrectable Error NMI Flag: This bit indicates
if an uncorrectable error occurred on a memory access (by any
master) and that condition is latched. This bit can only be cleared
by the user writing to the corresponding clear bit in the NMIFLGCLR
register or by SYSRSn reset:
0,No uncorrectable error condition pending
1, uncorrectable error condition generated
Reset type: SYSRSn
1 CLOCKFAIL R 0h Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL
condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by
SYSRSn reset:
0,No CLOCKFAIL Condition Pending
1,CLOCKFAIL Condition Generated
Reset type: SYSRSn
0 NMIINT R 0h NMI Interrupt Flag: This bit indicates if an NMI interrupt was
generated. This bit can only be cleared by the user writing to the
respective bit in the NMIFLGCLR register or by SYSRSn reset:
0 No NMI Interrupt Generated
1 NMI Interrupt Generated
No further NMI interrupts pulses are generated until this flag is
cleared by the user.
Reset type: SYSRSn

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3.16.4.3 NMIFLGCLR Register (Offset = 2h) [Reset = 0000h]

NMIFLGCLR is shown in Figure 3-54 and described in Table 3-66.
Return to the Summary Table.
NMI Flag Clear Register
Figure 3-54. NMIFLGCLR Register
15 14 13 12 11 10 9 8
RESERVED RESERVED SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED RESERVED RESERVED UNCERR CLOCKFAIL NMIINT
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-66. NMIFLGCLR Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R-0 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 SWERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 CLBNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
7 SYSDBGNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved

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Table 3-66. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
2 UNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
0 NMIINT R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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3.16.4.4 NMIFLGFRC Register (Offset = 3h) [Reset = 0000h]

NMIFLGFRC is shown in Figure 3-55 and described in Table 3-67.
Return to the Summary Table.
NMI Flag Force Register
Figure 3-55. NMIFLGFRC Register
15 14 13 12 11 10 9 8
RESERVED RESERVED SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED RESERVED RESERVED UNCERR CLOCKFAIL RESERVED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h

Table 3-67. NMIFLGFRC Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R-0 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 SWERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 CLBNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
7 SYSDBGNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 UNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
0 RESERVED R-0 0h Reserved

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3.16.4.5 NMIWDCNT Register (Offset = 4h) [Reset = 0000h]

NMIWDCNT is shown in Figure 3-56 and described in Table 3-68.
Return to the Summary Table.
NMI Watchdog Counter Register
Figure 3-56. NMIWDCNT Register
15 14 13 12 11 10 9 8
NMIWDCNT
R-0h

7 6 5 4 3 2 1 0
NMIWDCNT
R-0h

Table 3-68. NMIWDCNT Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDCNT R 0h NMI Watchdog Counter: This 16-bit incremental counter will start
incrementing whenever any one of the enabled FAIL flags are set.
If the counter reaches the period value, an NMIRSn signal is fired
which will then resets the system. The counter will reset to zero
when it reaches the period value and will then restart counting if any
of the enabled FAIL flags are set.
If no enabled FAIL flag is set, then the counter will reset to zero and
remain at zero until an enabled FAIL flag is set.
Normally, the software would respond to the NMI interrupt generated
and clear the offending FLAG(s) before the NMI watchdog triggers
a reset. In some situations, the software may decide to allow the
watchdog to reset the device anyway.
The counter is clocked at the SYSCLKOUT rate.
Reset type: SYSRSn

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3.16.4.6 NMIWDPRD Register (Offset = 5h) [Reset = FFFFh]

NMIWDPRD is shown in Figure 3-57 and described in Table 3-69.
Return to the Summary Table.
NMI Watchdog Period Register
Figure 3-57. NMIWDPRD Register
15 14 13 12 11 10 9 8
NMIWDPRD
R/W-FFFFh

7 6 5 4 3 2 1 0
NMIWDPRD
R/W-FFFFh

Table 3-69. NMIWDPRD Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDPRD R/W FFFFh NMI Watchdog Period: This 16-bit value contains the period value at
which a reset is generated when the watchdog counter matches. At
reset this value is set at the maximum. The software can decrease
the period value at initialization time.
Writing a PERIOD value that is smaller then the current counter
value will automatically force an NMIRSn and hence reset the
watchdog counter.
Reset type: SYSRSn

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3.16.4.7 NMISHDFLG Register (Offset = 6h) [Reset = 0000h]

NMISHDFLG is shown in Figure 3-58 and described in Table 3-70.
Return to the Summary Table.
NMI Shadow Flag Register
Figure 3-58. NMISHDFLG Register
15 14 13 12 11 10 9 8
RESERVED RESERVED SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED RESERVED RESERVED UNCERR CLOCKFAIL RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0-0h

Table 3-70. NMISHDFLG Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R-0 0h Reserved
14 RESERVED R 0h Reserved
13 SWERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 CLBNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
7 SYSDBGNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved

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Table 3-70. NMISHDFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
2 UNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
1 CLOCKFAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
0 RESERVED R-0 0h Reserved

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3.16.4.8 ERRORSTS Register (Offset = 7h) [Reset = 0000h]

ERRORSTS is shown in Figure 3-59 and described in Table 3-71.
Return to the Summary Table.
Error pin status
Figure 3-59. ERRORSTS Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED PINSTS ERROR
R-0-0h R-0h R-0h

Table 3-71. ERRORSTS Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R-0 0h Reserved
1 PINSTS R 0h 0, Error Pin is 0
1, Error Pin is 1
Reset type: PORESETn
0 ERROR R 0h 0,None of the error sources were triggered.
1, One or more of the error sources triggered, or
ERRORSTS.ERROR was set by a write of 1 to
ERRORSTSFRC.ERROR bit. Once set, the ERROR flag can be
cleared by writing 1 to ERRORSTSCLR.ERROR bit. Following are
the events/triggers which can set this bit:
1. nmi interrupt on C28x
2. Watchdog reset
3. Error on a Pie vector fetch
4. Efuse error
On a read of this bit, the pin Error pin state will be returned.
Reset type: PORESETn

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3.16.4.9 ERRORSTSCLR Register (Offset = 8h) [Reset = 0000h]

ERRORSTSCLR is shown in Figure 3-60 and described in Table 3-72.
Return to the Summary Table.
ERRORSTS clear register
Figure 3-60. ERRORSTSCLR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERROR
R-0-0h R-0/W1S-0h

Table 3-72. ERRORSTSCLR Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is cleared to 0
Reset type: PORESETn

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3.16.4.10 ERRORSTSFRC Register (Offset = 9h) [Reset = 0000h]

ERRORSTSFRC is shown in Figure 3-61 and described in Table 3-73.
Return to the Summary Table.
ERRORSTS force register
Figure 3-61. ERRORSTSFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERROR
R-0-0h R-0/W1S-0h

Table 3-73. ERRORSTSFRC Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is set to 1
Reset type: PORESETn

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3.16.4.11 ERRORCTL Register (Offset = Ah) [Reset = 0000h]

ERRORCTL is shown in Figure 3-62 and described in Table 3-74.
Return to the Summary Table.
Error pin control register
Figure 3-62. ERRORCTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERRORPOLSE
L
R-0-0h R/W-0h

Table 3-74. ERRORCTL Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERRORPOLSEL R/W 0h 0, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
0, else 1.
1, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
1, else 0.
Reset type: PORESETn

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3.16.4.12 ERRORLOCK Register (Offset = Bh) [Reset = 0000h]

ERRORLOCK is shown in Figure 3-63 and described in Table 3-75.
Return to the Summary Table.
Lock register to Error pin registers.
Figure 3-63. ERRORLOCK Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERRORCTL
R-0-0h R/WSonce-0h

Table 3-75. ERRORLOCK Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERRORCTL R/WSonce 0h 0, Writes to ERRORCTL register allowed.
1, Writes to ERRORCTL register is blocked.
Writes of 0 to this bit has no effect. Write of 1 will set this bit, cleared
only on a SYSRSn.
Reset type: SYSRSn

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3.16.5 XINT_REGS Registers

Table 3-76 lists the memory-mapped registers for the XINT_REGS registers. All register offset addresses not
listed in Table 3-76 should be considered as reserved locations and the register contents should not be modified.
Table 3-76. XINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h XINT1CR XINT1 configuration register Go
1h XINT2CR XINT2 configuration register Go
2h XINT3CR XINT3 configuration register Go
3h XINT4CR XINT4 configuration register Go
4h XINT5CR XINT5 configuration register Go
8h XINT1CTR XINT1 counter register Go
9h XINT2CTR XINT2 counter register Go
Ah XINT3CTR XINT3 counter register Go

Complex bit access types are encoded to fit into small table cells. Table 3-77 shows the codes that are used for
access types in this section.
Table 3-77. XINT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.5.1 XINT1CR Register (Offset = 0h) [Reset = 0000h]

XINT1CR is shown in Figure 3-64 and described in Table 3-78.
Return to the Summary Table.
XINT1 configuration register
Figure 3-64. XINT1CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-78. XINT1CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.2 XINT2CR Register (Offset = 1h) [Reset = 0000h]

XINT2CR is shown in Figure 3-65 and described in Table 3-79.
Return to the Summary Table.
XINT2 configuration register
Figure 3-65. XINT2CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-79. XINT2CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.3 XINT3CR Register (Offset = 2h) [Reset = 0000h]

XINT3CR is shown in Figure 3-66 and described in Table 3-80.
Return to the Summary Table.
XINT3 configuration register
Figure 3-66. XINT3CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-80. XINT3CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.4 XINT4CR Register (Offset = 3h) [Reset = 0000h]

XINT4CR is shown in Figure 3-67 and described in Table 3-81.
Return to the Summary Table.
XINT4 configuration register
Figure 3-67. XINT4CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-81. XINT4CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.5 XINT5CR Register (Offset = 4h) [Reset = 0000h]

XINT5CR is shown in Figure 3-68 and described in Table 3-82.
Return to the Summary Table.
XINT5 configuration register
Figure 3-68. XINT5CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-82. XINT5CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.6 XINT1CTR Register (Offset = 8h) [Reset = 0000h]

XINT1CTR is shown in Figure 3-69 and described in Table 3-83.
Return to the Summary Table.
XINT1 counter register
Figure 3-69. XINT1CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-83. XINT1CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.5.7 XINT2CTR Register (Offset = 9h) [Reset = 0000h]

XINT2CTR is shown in Figure 3-70 and described in Table 3-84.
Return to the Summary Table.
XINT2 counter register
Figure 3-70. XINT2CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-84. XINT2CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.5.8 XINT3CTR Register (Offset = Ah) [Reset = 0000h]

XINT3CTR is shown in Figure 3-71 and described in Table 3-85.
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XINT3 counter register
Figure 3-71. XINT3CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-85. XINT3CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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