The ICFAI Foundation for Higher Education, Hyderabad
IcfaiTech (Faculty of Science and Technology)
First Semester, A.Y.,2024 - 2025
Test-II Examination
Course Code: EC 414 Course Title: VLSI Testing and testability
Date: 07/11/2024 Maximum Marks: 20 Marks
Note: Answer ALL questions
Part-A
[6*1=6 Marks]
1. Define the following terms
a. D- Frontier
b. SC0(N), SC1(N), and SO(N)
c. Testability measures
d. Deterministic-ATPG
e. Fault Simulation
Fault simulation is a technique used in VLSI (Very Large Scale Integration)
design to evaluate how faults affect a system's behavior:
How it works
Simulated faults are injected into a model of the system, and the resulting behavior
is observed.
Purpose
Fault simulation helps VLSI engineers understand a system's reliability,
vulnerability, and fault tolerance. It can also be used to:
Measure the effectiveness of test patterns
Guide the generation of test patterns
f. Serial-fault simulation
Serial fault simulation is a fault simulation technique that simulates faults
one at a time to test a circuit:
1. Simulate the fault-free circuit: First, simulate the original circuit without any
faults to get the fault-free output responses.
2. Simulate faults: For each fault, inject a fault into the circuit to mimic the
behavior of a faulty circuit.
3. Evaluate the circuit: Evaluate the circuit's behavior in the presence of the
fault.
4. Repeat: Repeat the process for each fault in the fault list.
Part-B
[3*2=6 Marks]
1. Explain parallel fault simulation with example. [2 M]
2. Propagate the fault list in AND and OR Gate using deductive fault simulation. [2 M]
3. Outline the CC and CO of any 6 logic gates. [2 M]
Part-C
[2*4=8 Marks]
1. compute the combinational SCOAP testability measures (both controllability
and observability.) [4M]
2. Propagate D through the path efhl using D algorithm and find test pattern. [4M]
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