(Logic Design)

Lec. # 9

Dr. Ahmed Helmi

Accredited to: Dr. Tamer Samy Gaafr

Boolean Algebra and Logic Gates 1

 Sequential Circuits
▪ Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

▪ Synchronous

Inputs Outputs
Combinational
Circuit

Flip-flops
Clock

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 Latches
▪ SR Latch S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
1 10
Q=0
R Q
0 1 1 0 1
1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’

S Q
1 0

Transition Table
Or
Action Tble
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 Latches
▪ SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset

1 0 1 Set

S Q 1 1 Q=Q’=0 Invalid

S’ S S R Q
Q Invalid
0 0 Q=Q’=1
Set
0 1 1
Q 1 0 0 Reset
R’ R 1 1 Q0 No change
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 Latches
▪ SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset

1 0 1 Set

S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set

Q 1 0 0 Reset
R Q0
1 1 No change
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 Gated Latches
▪ SR Latch with Control Input
R R S S
Q Q
C C
S Q R Q
S R

C S R Q
No change
0 x x Q0
No change
1 0 0 Q0
Reset
1 0 1 0
1 1 0 1 Set

1 1 1 Q=Q’ Invalid
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Exercise 1

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 Gated Latches
▪ D Latch (D = Data) Timing Diagram

C
D S
Q
D
C
R Q
Q

t
EN or C C D Q
No change Output may change
0 x Q0
1 0 0 Reset

1 1 1 Set

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 Gated Latches
▪ D Latch (D = Data) Timing Diagram

C
D S
Q
D
C
R Q
Q

EN or C C D Q Output may change

No change
0 x Q0
1 0 0 Reset

1 1 1 Set

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Exercise 2

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 Flip-Flops
▪ Controlled latches are level-triggered

▪ Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

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 Flip-Flops
▪ Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
C (Master) C (Slave)

Master Slave
CLK
CLK

Looks like it is negative edge-triggered QMaster

QSlave
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 Flip-Flops
▪ Edge-Triggered D Flip-Flop
D Q

Q Positive Edge

CLK
D Q
Q

D Negative Edge

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 Flip-Flops
▪ JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q

D = JQ’ + K’Q K Q

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 Flip-Flops
▪ T- Flip-Flop

T J Q T D Q

Q
K Q

T Q

D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q
Q

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Flip-Flop Characteristic Tables
D Q D Q(t+1)
Reset
0 0
Q 1 1 Set

J K Q(t+1)
J Q No change
0 0 Q(t)
0 1 0 Reset

K Q 1 0 1 Set

1 1 Q’(t) Toggle

T Q T Q(t+1)
No change
0 Q(t)
Q
1 Q’(t) Toggle
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Flip-Flop Characteristic Equations
D Q D Q(t+1)
0 0
Q 1 1 Q(t+1) = D

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)
T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
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Exercise 3

Boolean Algebra and Logic Gates 18

Exercise 4

Boolean Algebra and Logic Gates 19

 Registers
I0 D Q A0
▪ Group of D Flip-Flops
▪ Synchronized (Single Clock) R

▪ Store Data I1 D Q A1

I2 D Q A2

I3 D Q A3

CLK
R
Reset
 Ripple Counters
▪ Ripple Asynchronous
 Ripple Counters
▪ Ripple Asynchronous
3-bit Synchronous Counter