ASIC DESIGN FLOW
Name : Onkar Sanjay Mane
ASIC (Application Specific Integrated Circuits)
Definition: A type of integrated circuit (IC) designed for a specific
application or task, rather than general-purpose use.
Importance: Why ASIC design is crucial?
Performance Optimization: Tailored for specific tasks, enhancing efficiency.
Power Efficiency: Designed to consume less power compared to general-
purpose processors.
Size and Integration: Reduces physical size and cost by integrating multiple
functions.
Security: Customizable security features enhance protection against
attacks.
Customization: Allows for specific features and interfaces unique to the
application.
ASIC Design Flow: Optimized
RTL
Code Netlist
Design
Specification Synthesis Verification
Entry
Front End RTL
GDS
Physical
ASIC Testing Fabrication
Design
Foundary
GDS II
1. Specification:
1. Functional Requirements
Purpose: Define the ASIC’s primary functions and features.
Inputs/Outputs: Specify data formats, protocols, and interface connections.
Behaviour: Describe operational behavior with state diagrams or flowcharts.
2. Performance Requirements
Speed: Maximum and minimum clock frequencies or data processing rates.
Latency: Acceptable delays for processing or response times.
Throughput: Data volume or operations per unit time.
3. Power, Area, and Timing Constraints
Power Consumption: Limits for active and idle states; thermal requirement.
Area: Maximum physical dimensions and gate count.
Timing Constraints: Setup/hold times, clock skew, and propagation delays.
2. Design Entry Design Entry
1. Architectural 3. RTL
Design Verification
2. RTL Design
(code)
Architectural Design:
• High-Level Design: Develop block diagrams and data flow models.
• Architecture Definition: Specify the organization of major
components and their interactions.
• IP Integration: Identify and incorporate pre-designed IP blocks if
applicable.
RTL Design:
• RTL Coding: Write detailed RTL code in HDL (Verilog/VHDL).
Modules & Interfaces: Define and implement functional blocks and
their interfaces.
Testbenches: Create initial testbenches for unit testing.
Design Validation:
• Simulation: Verify functionality with testbenches.
• Debugging: Identify and resolve issues.
• Formal Verification: Use formal methods to ensure correctness.
Tools & Methodologies:
• HDL Languages: Verilog, VHDL
• EDA Tools
• Simulation Tools
3. Synthesis
Objective:
• Convert RTL code into a optimized gate-level netlist suitable for physical
design.
Synthesis Process:
• RTL to Gate-Level: Translate RTL code (Verilog/VHDL) into a gate-level
representation using logic gates and flip-flops.
• Optimization: Optimize the design for area, speed, and power
consumption.
• Area Optimization: Reduce the silicon area required.
• Speed Optimization: Improve timing performance.
• Power Optimization: Minimize power consumption.
• Technology Mapping: Map the synthesized design to standard cell
libraries specific to the target ASIC technology.
STEPS:
OPTIMIZATION OF
INPUTS: 1. Translation NETLIST:
2. Logical OUTPUT
OUTPUT
1. RTL Code Optimization (Optimization Optimized Netlist
2. Timing Library 3. Technology Netlist
according to design
3. Physical Library Mapping constraints)
Synthesis Tool
•Translation: Build a complete, integrated view of the design.
•Optimize: Apply algorithms to improve area, speed, and power.
•Generate Netlist: Produce a gate-level netlist that includes all the logic
gates and connections.
•Technology mapping: Mapping of the netlist with the library files.
•Netlist Optimization: optimizing the netlist generated with respect to the
constraitns given by designer.
4. Verification
Objective:
• Ensure the synthesized design meets functional and timing requirements.
Verification Processes:
1. Functional Verification:
• Post-Synthesis Simulation: Verify that the gate-level netlist behaves
as expected.
• Testbenches: Reuse or adapt testbenches from the RTL phase to test
the synthesized design.
• Assertion-Based Verification: Use assertions to check properties and
behaviours.
2. Timing Verification:
• Static Timing Analysis (STA): Analyse timing paths to ensure the
design meets speed requirements.
• Setup and Hold Checks: Validate that setup and hold times are
satisfied.
3. Formal Verification:
• Equivalence Checking: Confirm that the RTL and synthesized
netlist are functionally equivalent.
• Property Checking: Verify that design properties hold true.
Tools & Methodologies:
• Simulation Tools
• Timing Analysis Tools
• Formal Verification Tools:
5. Physical Design
Objective:
• Convert the gate-level netlist into a physical layout ready for fabrication
Netlist
(Optimized Clock Tree
Floorplanning Placement
and Synthesis
Verified
Routing
LVS (Layout vs. DRC (Design
GDS II Signoff
Schematic) Rule Checking)
PnR Tool
Physical Design Stages:
1. Floorplanning:
Define the placement of major functional blocks and I/O pads.
Optimize space and layout for area efficiency.
2. Placement:
Place standard cells and IP blocks on the chip.
Ensure optimal placement to minimize wire lengths and delay.
3. Clock Tree Synthesis (CTS):
Design and insert a clock distribution network to ensure balanced clock signals
throughout the design.
4. Routing:
Global Routing: Plan the routing of signals across the chip.
Detailed Routing: Implement precise routing of interconnections between cells.
5. DRC (Design Rule Checking):
Verify that the layout adheres to fabrication rules and constraints.
Ensure spacing, width, and other design rules are met.
6. LVS (Layout vs. Schematic):
Compare the physical layout to the schematic to ensure they match.
7. Signoff:
Timing Signoff: Verify that the design meets timing requirements after routing.
Power Signoff: Ensure adequate power delivery and verify power integrity.
Output: GDS II
The GDSII file format is the industry standard for representing the layout of
integrated circuits in a detailed, hierarchical manner. It contains the geometric
and layer information necessary for photolithography in semiconductor
fabrication.
6. Fabrication and Testing
Objective:
Manufacture the physical integrated circuit (IC) based on the design
specified in the GDSII file.
STEPS:
1. Wafer Preparation:
2. Photolithography:
3. Etching:
GDS II Packaging ASIC
4. Deposition:
5. Doping:
6. Metallization:
7.Testing
Foundry
