Section 2-7 Memory Unit - Solved Answers
2-18:
The connections between four 4-bit binary counters to produce a 16-bit binary counter with a parallel
load can be designed as follows:
1. Each 4-bit counter is connected in cascading form, where the carry-out (CO) of one counter is
connected to the clock input of the next counter.
2. All counters have parallel load functionality connected to the same load control line.
The block diagram includes:
- Four 4-bit counters connected serially (Counter 1 to Counter 4).
- A control line for parallel load functionality.
For a divide-by-N counter with parallel load:
- Connect an AND gate to check when the counter reaches N.
- Use this signal to reset the counter to 0000.
2-19:
Address lines and input-output data lines:
(a) 2K x 16:
Address lines = log2(2K) = 11 (2^11 = 2K)
Data lines = 16
(b) 64K x 8:
Address lines = log2(64K) = 16 (2^16 = 64K)
Data lines = 8
(c) 16M x 32:
Address lines = log2(16M) = 24 (2^24 = 16M)
Data lines = 32
(d) 4G x 64:
Address lines = log2(4G) = 32 (2^32 = 4G)
Data lines = 64
2-20:
Number of bytes stored:
(a) 2K x 16: 2K * (16/8) = 4 KB
(b) 64K x 8: 64K * (8/8) = 64 KB
(c) 16M x 32: 16M * (32/8) = 64 MB
(d) 4G x 64: 4G * (64/8) = 32 GB
2-21:
Number of 128 x 8 chips needed:
Total memory = 4096 x 16 bits = 8192 bytes
One chip capacity = 128 x 8 bits = 128 bytes
Number of chips = Total memory / Chip capacity = 8192 / 128 = 64 chips
2-22:
To construct 128 x 8 ROM:
1. A 32 x 8 ROM chip requires 5 address lines (log2(32) = 5).
2. Use 2 additional address lines to select one of the four ROM chips.
3. Use a 2-to-4 decoder to generate the enable signals for the ROM chips.
2-23:
4096 x 8 ROM with 2 enable inputs:
- Address lines = log2(4096) = 12 (2^12 = 4096)
- Data lines = 8
- Enable inputs = 2
- Power supply = 2 (Vcc and GND)
Total pins = Address lines + Data lines + Enable lines + Power supply = 12 + 8 + 2 + 2 = 24 pins.
Block Diagram:
- Include address, data, enable, and power connections to the ROM chip.
