Subject Name: Computer Organization

Subject Code:BSC20010
Unit No. :-2
Topic Name :- CPU Organization

Dr. Sumit Gupta

Department of Computer Science & Applications
1
 Content
1. Von Neumann Architecture

2. Harvard Architecture

3. Concept of RISC and CISC

4. Functions of CPU

5. General registers used in CPU

6. Concept of stack

7. Instructions used with stack

8. Block diagram of ALU

2
 Architecture of CPU

The architecture of any computer mainly refers to the overall arrangement of the CPU. Here, Von Neumann and
Harvard architecture serve as the two major ways using which the microprocessor gets its CPU arrangement with the
memory. We will discuss Von Neumann and Harvard Architecture in detail.

Von Neumann Architecture:

 The famous physicist and mathematician John Von Neumann designed this architecture back in the year 1945.

 It is a type of computer architecture in which the design follows the concept of the computers with stored programs
where they store the program data along with the instruction data in the same memory. This memory is usually
implemented as random access memory (RAM) and is connected to the CPU and I/O devices through a common
bus. The CPU executes instructions by fetching them from memory, decoding them, and then executing them.

 In this architecture, the central processing unit (CPU), memory, and I/O devices, all are used a single shared bus for
communication.

3
 Architecture of CPU
Von Neumann Architecture: The architecture contains different functional
units like CPU, Input, Output and Memory unit as shown in figure.

Advantages of Von Neumann Architecture:

 The Von Neumann architecture has several advantages, including
simplicity, flexibility, and efficiency.
 Because instructions and data are stored in the same memory system, the
CPU can easily access both of them without having to switch between
different memory systems. This makes it easier to write programs and
reduces the complexity of the system as a whole.

Disadvantages of Von Neumann Architecture:

 One of the main limitations is that the shared bus can become a
bottleneck if too many devices are connected to it. This can lead to slow
performance and reduced scalability.
 Additionally, the CPU can only execute one instruction at a time, which
can limit the overall speed of the system. Von Neumann Architecture

4
 Architecture of CPU
Harvard Architecture:

 Harvard architecture is a type of computer architecture that has separate memory spaces for instructions and data.

 It was developed at Harvard University in the 1930s, and it is named after this institution.

 In a Harvard architecture system, the CPU accesses instruction and data memory spaces separately, which can lead to
improved performance.

 It consists of the following main components:

 CPU: The central processing unit performs all the calculations and operations required to execute instructions.
 Instruction memory: This memory holds instructions that the CPU needs to execute. It is typically implemented as
read-only memory (ROM) or flash memory.
 Data memory: This memory holds data that the CPU needs to perform computations. It is typically implemented as
random access memory (RAM).I
 I/O devices: These devices are used to communicate with the outside world. Examples include keyboards, displays,
and printers.
 System bus: The system bus is a collection of wires that connect the CPU, instruction memory, data memory, and
I/O devices. It is used to transmit data, instructions, and control signals between these components. 5
 Architecture of CPU
Advantages of Harvard Architecture

 The CPU can access both instruction and data memory simultaneously.

 This can lead to improve performance because the CPU does not have to
switch between memory spaces as often as in a Von Neumann
architecture.
 Additionally, because the instruction memory is typically implemented
as ROM or flash memory, it is non-volatile, meaning that it does not lose
its contents when power is turned off.
 This makes it well-suited for embedded systems that need to operate
without a constant power source.

Disadvantages of Harvard Architecture

 As the CPU accesses instruction and data memory separately, it can be

more difficult to write programs that require the CPU to modify its own
code.
Harvard Architecture
 Additionally, because the instruction and data memories are separate, it
can be more difficult to share data between different parts of a program. 6
 The Difference between them is given as:

Parameters Von Neumann Architecture Harvard Architecture

Access to CPU The CPU is not able to read/write data and The CPU can easily read/write data as well as
access instructions at the same time. access the instructions at any given time.

Uses This method comes to play in the case of small This architecture is best for signal processing
computers and personal computers. as well as microcontrollers.

Requirement of Von Neumann Architecture requires lesser This one requires more hardware. It is because
Hardware architecture. It is because it only needs to it requires separate sets of data as well as
reach one common memory. address buses for individual memory.

Requirement of Space This architecture basically requires less space. This architecture comparatively requires more
space.
Usage of Space This architecture does not waste any space. It This type of architecture can result in space
is because the instruction memory can utilize wastage. It is because the instruction memory
the left space of the data memory. It can also cannot utilize the leftover space in the data
happen vice-versa. memory. It also cannot happen vice-versa. 7
 The Difference between them is given as:

Parameters Von Neumann Architecture Harvard Architecture

Physical Address It uses one single physical address for It uses two separate physical addresses for
accessing and storing both data and storing and accessing both instructions and
instructions. data.

Buses (Signal Paths) One common signal bus helps in the transfer It uses separate buses for the transfer of both
of both instruction and data. data and instructions.

Number of Cycles It requires two clock cycles for executing a It executes any instruction using only one
single instruction. single cycle.
Cost It is comparatively cheaper in cost than It is comparatively more expensive than the
Harvard Architecture. Von Neumann Architecture.

8
 Instruction Set Architecture

RISC:
In computer science, a Reduced Instruction Set Computer (RISC) is a
computer architecture designed to simplify the individual instructions
given to the computer to accomplish the tasks. A RISC computer might
require more instructions (more code) in order to accomplish a task
because the individual instructions are written in simpler manner.
The conceptual developments of the RISC computer architecture began
with the IBM 801 project in the late 1970s, but these were not
immediately put into use. Designers in California picked up the 801
concepts in two seminal projects, Stanford MIPS and Berkeley RISC.
These were commercialized in the 1980s as the MIPS and SPARC
systems. John Cocke of IBM Research who proved that about 20% of
instructions in a computer did 80% of the work.
Popular examples of RISC-based processors include PowerPC , ARM
and MIPS .

9
 Instruction Set Architecture

CISC:
A complex instruction set computer (CISC) is a computer
architecture in which single instruction can execute several
low-level operations (such as a load from memory, an
arithmetic operation, or a memory store) or are capable of
multi-step operations or addressing modes within single
instructions, developed by the Intel. It has a large collection
of complex instructions that range from simple to very
complex and specialized in the assembly language level,
which takes a long time to execute the instructions.
So, CISC approaches reducing the number of instruction on
each program and ignoring the number of cycles per
instruction. It emphasizes to build complex instructions
directly in the hardware because the hardware is always
faster than software. Examples of CISC processors are VAX,
AMD, Intel x86, PDP-11 and the System/360.
10
The Difference between RISC and CISC is given as

Sr No RISC CISC
1 Stands for Reduced Instruction Set Computer Stands for Complex Instruction Set Computer
2 An instruction set architecture that designed to perform a Full set of Computer instructions that intends to provide
smaller number of computer instruction so that it can necessary capabilities in efficient way
operate at high speed
3 Utilizes small , highly optimized set of instructions Utilizes large , specialized and a complex set of instructions
4 More machine oriented More programmer oriented
5 Simple and requires one clock cycle to execute the Complex and requires more clock cycle to execute the
instruction instruction
6 More Registers Fewer Registers
7 Instructions are simple , fixed format with less Instructions have variable formats with complex addressing
addressing modes modes
8 Has simple instruction – program length is large Has complex instructions – program length is small
9 Requires more RAM Requires minimum amount of RAM
10 Used in Hardwired Control Unit , used in applications Used in Microprogrammed Control Unit , used in
such as mobile phone , tablets, ARM. applications such as Desktop Computer and Laptops
Intel x86 , Motorola family 11
 Central Processing Unit

 The central processing unit (CPU) is the primary component of any digital computer system, consisting of the main
memory, the control unit, and the arithmetic-logic unit.

 It is the physical heart of the entire computer system, to which various peripheral equipment, such as input/output devices
and auxiliary storage units, are connected.

 The CPU in modern computers is housed on an integrated circuit chip known as a microprocessor.

 It’s control unit regulates and integrates the computer’s operations.

 It selects and retrieves instructions from the main memory in the correct sequence and interprets them so that the other
functional elements of the system can perform their respective operations at the appropriate time.

 All input data are transferred via main memory to the arithmetic-logic unit for processing, which includes the four basic
arithmetic functions (addition, subtraction, multiplication, and division) as well as certain logic operations such as data
comparison and selection of the desired problem-solving procedure or a viable alternative based on predetermined
decision criteria.
12
 Central Processing Unit

The Central Processing Unit (CPU) has the following characteristics:

 The CPU is responsible for all data processing operations.

 It saves information such as data, intermediate results, and program

instructions.

 It directs the operation of all computer components.

A typical CPU has three major components:

 Register Set

 Arithmetic Logic Unit (ALU)

 Control Unit (CU)

13
 Central Processing Unit

 The register set differs from one computer architecture to another.

 It is usually a combination of general-purpose and special purpose registers.

 General-purpose registers are used for any purpose, hence the name general purpose.

 Special-purpose registers have specific functions within the CPU.

 For example, the program counter (PC) is a special-purpose register that is used to hold the address of the
instruction to be executed next.
 Another example of special-purpose registers is the instruction register (IR), which is used to hold the instruction
that is currently executed.

 The ALU provides the circuitry needed to perform the arithmetic, logical and shift operations demanded of the
instruction set.

 The control unit is the entity responsible for fetching the instruction to be executed from the main memory and
decoding and then executing it.
14
 Central Processing Unit

Function of CPU :

A typical and simple execution cycle can be summarized as follows:

 The next instruction to be executed, whose address is obtained from the PC, is fetched from the memory and
stored in the IR.
 The instruction is decoded.
 Operands are fetched from the memory and stored in CPU registers, if needed.
 The instruction is executed.
 Results are transferred from CPU registers to the memory, if needed.

 The execution cycle is repeated as long as there are more instructions to execute.

 The actions of the CPU during an execution cycle are defined by micro-orders issued by the control unit.

 These micro-orders are individual control signals sent over dedicated control lines.

15
 Central Processing Unit

Function of CPU :

A typical and simple execution cycle can be summarized as follows:

 The next instruction to be executed, whose address is obtained from the PC, is fetched from the memory and
stored in the IR.
 The instruction is decoded.
 Operands are fetched from the memory and stored in CPU registers, if needed.
 The instruction is executed.
 Results are transferred from CPU registers to the memory, if needed.

 The execution cycle is repeated as long as there are more instructions to execute.

 The actions of the CPU during an execution cycle are defined by micro-orders issued by the control unit.

 These micro-orders are individual control signals sent over dedicated control lines.

16
 Central Processing Unit

REGISTER SET:

 Registers are essentially extremely fast memory locations within the CPU that are used to create and store the results of
CPU operations and other calculations.
 Different computers have different register sets.
 They differ in the number of registers, register types, and the length of each register.
 They also differ in the usage of each register.
 General-purpose registers can be used for multiple purposes and assigned to a variety of functions by the programmer.
 Special-purpose registers are restricted to only specific functions.
 Another type of registers is used to hold processor status bits, or flags. The status bits can be tested at a later time as
part of another operation.
 The length of a data register must be long enough to hold values of most data types.
 Address registers may be dedicated to a particular addressing mode or may be used as address general purpose.
 Address registers must be long enough to hold the largest address.
17
 Central Processing Unit

REGISTER SET: Memory Access Registers

Two registers are essential in memory write and read operations: the memory data register (MDR) and memory address
register (MAR). The MDR and MAR are used exclusively by the CPU and are not directly accessible to programmers.
In order to perform a write operation into a specified memory location, the MDR and MAR are used as follows:

 The word to be stored into the memory location is first loaded by the CPU into MDR.
 The address of the location into which the word is to be stored is loaded by the CPU into a MAR.
 A write signal is issued by the CPU.

Similarly, to perform a memory read operation, the MDR and MAR are used as follows:

 The address of the location from which the word is to be read is loaded into the MAR.
 A read signal is issued by the CPU.
 The required word will be loaded by the memory into the MDR ready for use by the CPU. 18
 Central Processing Unit

REGISTER SET: Instruction Fetching Registers

 Three main registers are involved in fetching an instruction for execution: Program Counter (PC), Instruction Register
(IR) and Instruction Decoder (ID).
 The PC is the register that contains the address of the next instruction to be fetched.
 The fetched instruction is loaded in the instruction register (IR) for execution.
 After a successful instruction fetch, the PC is updated to point to the next instruction to be executed.
 In the case of a branch operation, the PC is updated to point to the branch target instruction after the branch is resolved,
i.e., the target address is known.
 The ID will decode the operation and execute the operation.

19
 Central Processing Unit

REGISTER SET: Condition Registers

 Condition registers, or flags, are used to maintain status information.

 Some architectures contain a special program status word (PSW) register.
 The PSW contains bits that are set by the CPU to indicate the current status of an executing program.
 These indicators are typically for arithmetic operations, interrupts, memory protection information, or processor status.

20
 Central Processing Unit

REGISTER SET: Special-Purpose Address Registers

 Index Register In index addressing, the address of the operand is obtained by adding a constant to the content of a register,
called the index register. The index register holds an address displacement. Index addressing is indicated in the instruction by
including the name of the index register in parentheses and using the symbol X to indicate the constant to be added.
 Segment Pointers In order to support segmentation, the address issued by the processor should consist of a segment number
(base) and a displacement (or an offset) within the segment. A segment register holds the address of the base of the segment.
 Stack Pointer A stack is a data organization mechanism in which the last data item stored is the first data item retrieved.
Two specific operations can be performed on a stack. These are the Push and the Pop operations. A specific register, called
the stack pointer (SP), is used to indicate the stack location that can be addressed. In the stack push operation, the SP value is
used to indicate the location (called the top of the stack). After storing (pushing) this value, the SP is incremented (in some
architectures, e.g. X86, the SP is decremented as the stack grows low in memory).
21
 Central Processing Unit

STACK
 A computer program often needs to perform a particular subtask using the familiar subroutine structure.
 In order to organize the control and information linkage between the main program and the subroutine, a data structure
called a stack is used.
 A stack is a list of data elements, usually words or bytes, with the accessing restriction that elements can be added or
removed at one end of the list only.
 This end is called the top of the stack, and the other end is called the bottom.
 The structure is sometimes referred to as a pushdown stack.
 Last-in-First-out (LIFO) stack is used to describe this type of storage mechanism. The last data item placed on the stack is
the first one removed when retrieval begins.
 The terms PUSH and POP are used to describe placing a new item on the stack and removing the top item from the stack,
respectively.
22
 Central Processing Unit

STACK

Data stored in the memory of a computer can be organized as a stack, with

successive elements occupying successive memory locations. Assume that the
first element is placed in location BOTTOM, and when new elements are
pushed onto the stack, they are placed in successively lower address locations.
Example:
It contains numerical values, with 43 at the bottom and -28 at the top. A
processor register is used to keep track of the address of the element of the
stack that is at the top at any given time. This register is called the stack pointer
(SP). It could be one of the general-purpose registers or a register dedicated to
this function. If we assume a byte-addressable memory with a 32-bit word
length, the push operation can be implemented as
Subtract #4,SP
Move NEWITEM,(SP)
where the Subtract subtracts the source operand 4 from the destination
operand contained in SP and places the result in SP. These two instructions
move the word from location NEWITEM onto the top of the stack,
decrementing the stack pointer by 4 before the move.
23
 Central Processing Unit

STACK

The pop operation can be implemented as

Move (SP),ITEM
Add #4,SP

These two instructions move the top value from the stack into
location ITEM and then increment the stack pointer by 4
so that it points to the new top element.

When a stack is used in a program, it is usually allocated a

fixed amount of space in the memory. In this case, we must
avoid pushing an item onto the stack when the stack has
reached its maximum size. Also, we must avoid attempting
to pop an item off an empty stack, which could result from
a programming error.
24
 Central Processing Unit

Advantages of Stack Memory:

 It helps us to manage the data in a Last In First Out(LIFO) method.

 It allows you to control how memory is allocated and deallocated.

 Stack automatically cleans up the data.

 It is not easily corrupted

Disadvantages of Stack Memory:

 Stack memory is very limited.

 Random access is not possible.

 Creating too many objects on the stack can increase the risk of stack overflow.

 The stack will fall outside of the memory area, which might lead to an abnormal termination.
25
 Central Processing Unit

The computer’s Arithmetic Logic Unit (ALU) is the mathematical brain. The first ALU was indeed the INTEL 74181, which
was implemented as part of the 7400 series TTL (Transistor-Transistor Logic) integrated circuits. It was released by Intel in
1970.

 ALU is the fundamental building block of the central processing unit of a computer.

 A modern central processing unit(CPU) has a very powerful ALU and it is complex in design.

 In addition to modern ALU, CPU contains a control unit and a set of registers.

 Most of the operations are performed by one or more ALUs, which load data from the input register.

 Registers have small amount of storage to the CPU. These registers can be accessed very fast.

 The control unit tells ALU what operation to perform on the available data.

 After calculation/manipulation, the ALU stores the output in an output register.

26
 Central Processing Unit

 The inputs to an ALU are the data to be operated on,

called operands, and a code indicating the operation to
be performed.

 The ALU's output is the result of the performed

operation.

 In many designs, the ALU also has status inputs or

outputs, or both, which convey information about a
previous operation or the current operation,
respectively, between the ALU and external status
registers.

 A basic ALU has three parallel data buses consisting of Simplest Block Diagram of ALU
two input operands (A and B) and a result output (Y).

27
General CPU Register Organization

28