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Lecture 8 FPGA LUT Programming

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Kallu kalia
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240 views21 pages

Lecture 8 FPGA LUT Programming

Uploaded by

Kallu kalia
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPSX, PDF, TXT or read online on Scribd
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CKV

Reconfigurable Computing
CS G553

Lecture 8 –FPGA Fabrics, LUT Programming


LUT

1
0
0
1
0
0

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LUT

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LUT

3-input, one output LUT 3-input, two output LUT


Implementation of AB, AB+C and AB+CD
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LUT
Implementation of AB+CD

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LUT
k
p w

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LUT
k
p x
w
s
t
d

3 inputs and 1 3 inputs and 1


output output
x=kps’ w=x+t+d

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LUT
kk
pp xx
w
w
ss
tt
dd

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LUT
9-input Circuit

LUT

512x1LUT
9-input LUT LUT

LUT

1 , 512x1 Mem 4 , 8x1 Mem CKV


LUT
LUT Typically has 2 or more outputs

Example: Partitioning among 3-input, 2-output LUTs

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LUT

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LUT
Example: Implement 2x4 decoder using 3-input 2-output
LUTs

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LUT
Example: Implement 2x4 decoder using 3-input 2-output
LUTs

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LUT

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LUT
Can You Design?

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LUT
Can You Design?

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LUT

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LUT

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LUT

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Consider a 2-bit comparator, which compares 2-bit numbers A(A 2A1) and B(B2B1). The
output of this comparator are two 1-bit signals as mentioned below:
(a) G which is logic 1 if A is greater than B else it is logic 0.
(b) E which is logic 1 if A is equal to B else it is logic 0.
Assuming that there are 3-input, 2-output LUTs available (8x2 Mem as in figure below),
Implement the comparator with above specifications using least number of LUTs.

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Thank You
CKV

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