Parallel Register VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity parallelRegister is
port( D: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end parallelRegister;
architecture architect of parallelRegister is
component dflipflop
Port( d,clk,reset: in std_logic ;
q: out std_logic
);
end component;
begin
df0: dflipflop port map(d=>D(0), reset=>reset, clk=>clk, q=>Q(0));
df1: dflipflop port map(d=>D(1), reset=>reset, clk=>clk, q=>Q(1));
df2: dflipflop port map(d=>D(2), reset=>reset, clk=>clk, q=>Q(2));
df3: dflipflop port map(d=>D(3), reset=>reset, clk=>clk, q=>Q(3));
end architect;
-----------------------dflipflop-------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dflipflop is
port( d,clk,reset: in std_logic;
q: out std_logic
);
end dflipflop;
architecture behaviour of dflipflop is
begin
dflip: process(d,clk,reset)
begin
if reset='1' then
q<='0';
elsif rising_edge(clk) then
if(d='0') then
q<='0';
elsif(d='1') then
q<='1';
end if;
end if;
end process;
end behaviour;
Parallel Register Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY parallelRTest IS
END parallelRTest;
ARCHITECTURE behavior OF parallelRTest IS
COMPONENT parallelRegister
PORT(
D : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
reset : IN std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
signal D : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal Q : std_logic_vector(3 downto 0);
BEGIN
uut: parallelRegister PORT MAP (
D => D,
clk => clk,
reset => reset,
Q => Q
);
clk_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
stim_proc: process
begin
reset<='0';
D<="1001";
wait for 100 ns;
reset<='0';
D<="0000";
wait for 100 ns;
reset<='0';
D<="1011";
wait for 100 ns;
reset<='0';
D<="0101";
wait for 100 ns;
end process;
END;
Output
Figure 01: Output of Parallel Register Circuit
Parallel Register VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity parallelAdder is
port( A,B: in std_logic_vector(3 downto 0);
cin: in std_logic;
cout: out std_logic;
S: out std_logic_vector(3 downto 0)
);
end parallelAdder;
architecture Behavioral of parallelAdder is
component FA
Port( a,b,cin: in std_logic;
s,cout: out std_logic
);
end component;
signal c1,c2,c3: std_logic;
begin
PA: FA port map(a=>A(0),b=>B(0),cin=>cin,s=>S(0),cout=>c1);
PA1: FA port map(a=>A(1),b=>B(1),cin=>c1,s=>S(1),cout=>c2);
PA2: FA port map(a=>A(2),b=>B(2),cin=>c2,s=>S(2),cout=>c3);
PA3: FA port map(a=>A(3),b=>B(3),cin=>c3,s=>S(3),cout=>cout);
end Behavioral;
-------------FA (Full Adder)--------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
Port ( a,b,cin : in STD_LOGIC;
s,cout : out STD_LOGIC);
end FA;
architecture dataflow of FA is
begin
s <= a xor b xor cin;
cout <= ((a and b) or (a and cin) or (cin and b));
end dataflow;
Parallel Register Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY parallelATest IS
END parallelATest;
ARCHITECTURE behavior OF parallelATest IS
COMPONENT parallelAdder
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
cin : IN std_logic;
cout : OUT std_logic;
S : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal cin : std_logic := '0';
signal cout : std_logic;
signal S : std_logic_vector(3 downto 0);
BEGIN
uut: parallelAdder PORT MAP (
A => A,
B => B,
cin => cin,
cout => cout,
S => S
);
stim_proc: process
begin
A<="1001";
B<="1000";
cin<='1';
wait for 100 ns;
A<="1010";
B<="1000";
cin<='0';
wait for 100 ns;
A<="1011";
B<="1001";
cin<='1';
wait for 100 ns;
A<="0101";
B<="0010";
cin<='1';
wait for 100 ns;
end process;
END;
Output
Figure 02: Output of Parallel Adder Circuit
