Birla Institute of Technology and Science – Pilani
Pilani | Goa
First Semester 2019-2020
CS G553-Reconfigurable Computing
Component: Regular (Closed Book)
Duration: 90 min MIDTERM TEST Max. Marks: 25
Q1. What are SPLDs and CPLDs? [01]
Q2. Compare temporal computing vs spatial computing with an example? [02]
Q3. Should the LUT circuitry be made of DEMUX or MUX based circuits? Justify your answer [02]
Q4. Compare SRAM vs Anti-fuse based FPGAs [02]
Q5. Assume that your design did not meet the timing constraints, propose different methods to
fix it for FPGA implementation and what are its implications? [03]
Q6. Explain how to implement the fastest 96-bit adder in Virtex-5 FPGA fabric. [04]
Q7. Is it possible to map the following Boolean expression to the CLB structure shown in figure-1?
If so, prove it by labeling the inputs with the appropriate variables and the internal wires with the
corresponding Boolean expressions. Complemented inputs are not available.
F = ac + ad + a’e’f [04]
Figure-1
Q8. Figure-2 shows the circuit diagram for a simple 3-bit pseudo-random counter. Figure-3 shows the
basic block (CLB) of an FPGA. Use minimum number of CLBs and show the implementation of this
counter. [07]
Figure-2: 3-bit pseudo-random counter
Figure-3: basic block (CLB)
