Expt.
5: PRIORITY ENCODER
Aim:
• To design Priority Encoder of 4Inputs and 3Outputs.
• To write the Verilog HDL code for the realization of multiplexer.
• To write the testbench and simulate the design in Xilinx ISE environment
for verifying its functionality.
• To synthesize the design, implement it on ARTIX7 FPGA kit and verify
its functionality.
Apparatus:
• Computer System
• Xilinx Vivado 2018.2
• Artix 7 NEXYS DDR4 FPGA Boards
Logic Diagram:
Experimental Procedure:
1. Write a Verilog program for the design of Logic Gate Functionalities
2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its
functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation board
(ARTIX 7 FPGA).
7. Create Timing constraints for the design.
8. Implement the design with the user constraints specified in step 6 and 7.
9. Properly connect the FPGA evaluation board to the PC.
10.Generate the FPGA bitmap file and configure the device using iMPACT
tool.
11.Verify the functionality of the design in the FPGA Board.
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Verilog Source Code:
module pe(
input wire [4:1] A, //input declaration
output reg [2:0] pcode //output declaration
);
always @ *
casez (A) // start case
4'b1zzz :
pcode = 3'b100;
4'b01zz :
pcode = 3'b011 ;
4'b001z :
pcode = 3'b010;
4'b0001 :
pcode = 3'b001;
4'b0000 :
pcode = 3'b000;
end
endcase // end case
endmodule // end module
Verilog Testbench Code:
module pe_test( );
reg [4:1] A;
wire [2:0] pcode; // Instantiate the Unit Under Test (UUT)
pe uut (.A(A), .pcode(pcode));
initial begin // Initialize Inputs
A = 4'b0000;
#20 A = 4'b0001;
#20 A = 4'b0010;
#20 A = 4'b0011;
#20 A = 4'b0100;
#20 A = 4'b0101;
#20 A = 4'b0110;
#20 A = 4'b0111;
#20 A = 4'b1000;
#20 A = 4'b1001;
#20 A = 4'b1010;
#20 A = 4'b1011;
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#20 A = 4'b1100;
#20 A = 4'b1101;
#20 A = 4'b1110;
#20 A = 4'b1111;
#40 ;
end
initial begin
$monitor("t=%3d A=%4b,pcode=%3b",$time,A,pcode );
end
endmodule
RTL Schematic:
Fig.5.1 RTL of the Priority Encoder
Register-transfer-level abstraction is used in hardware description languages
(HDLs) like Verilog and VHDL to create high-level representations of a circuit,
from which lower-level representations and ultimately actual wiring can be
derived. In digital circuit design, register-transfer level (RTL) is a design
abstraction which models a digital circuit in terms of the flow of digital signals
(data) between hardware registers, and the logical operations performed on those
signals. Viewing an RTL schematic opens an NGR file that can be viewed as a
gate-level schematic.
This schematic is generated after the HDL synthesis phase of the synthesis
process. It shows a representation of the pre-optimized design in terms of generic
symbols, such as adders, multipliers, counters, AND gates, and OR gates, that are
independent of the targeted Xilinx device.
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Technology Schematic:
Fig.5.2 Technology Schematic of the Priority Encoder
Viewing a Technology schematic opens an NGC file that can be viewed as an
architecture-specific schematic.This schematic is generated after the optimization
and technology targeting phase of the synthesis process. It shows a representation
of the design in terms of logic elements optimized to the target Xilinx device or
"technology"; for example, in terms of of LUTs, carry logic, I/O buffers, and
other technology-specific components. Viewing this schematic allows you to see
a technology-level representation of your HDL optimized for a specific Xilinx
architecture, which might help you discover design issues early in the design
process. We should always refer to technology schematic for synthesized result.
Simulated Waveforms:
Fig.5.3 Simulated Waveform of the module
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Simulation is a technique of applying different input stimulus to the design at
different times to check if the rtl code behaves the intended way. It is used to
verify the robustness of the design.It is also similar to how a fabricated chip will
be used is the real world andf how it reacts to different inputs
Synthesis Reports:
Power Report:
Fig.5.4 Power Report of the module
Power report gives us an insight into the power consumed by the module, a report
like this helps to know where the power is consumed and if any redesigning is
necessary.
XDC REPORT:
Fig.5.5 XDC Report of the module
It explains about the input and output pins of the module.
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Device utilization summary:
Fig.5.6 Utilisation Report of the module
Utilisation report gives us an insight into the no. of LUTs, sliced registers and
Bonded IOB consumed by the module.
Result:
The design of a Priority encoder is obtained and simulated using Verilog HDL
in Xilinx ISE environment. The design is then synthesized, implemented in
Artix 7 FPGA kit and its functionality is verified.
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